CN1209656A

CN1209656A - Semiconductor storage device having multiple storage bodies

Info

Publication number: CN1209656A
Application number: CN98117380A
Authority: CN
Inventors: 荒井実成
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1997-08-25
Filing date: 1998-08-25
Publication date: 1999-03-03
Also published as: JPH1166838A; KR19990023826A; KR100302939B1

Abstract

A semiconductor memory storage includes at least two of the storage and a storage of identification code ID register. This semiconductor memory also includes a signature-recognition circuitry for comparing the external request identifier input from the semiconductor memory and the identifier stored in the ID identifier. When the external input from the semiconductor memory are in mutual agreement with the identifier stored in the ID identifier, the requested identification code corresponding to the storage body was accessed.

Description

The semiconductor storage that contains a plurality of memory banks

The present invention relates to a kind of dynamic random access memory that constitutes by a plurality of memory banks (hereinafter referred to as " DRAM ") device, more particularly, relate to a kind of semiconductor storage with a plurality of device identification code holding units.

Recently developed DRAM with device identification code.Among a plurality of DRAM which be the device identification code be used to discern by access.Fig. 7 shows this dynamic random access memory that is defined as rumbusDRAM (bright nurse bus DRAM) especially.

As shown in Figure 7, a DRAM has a device identification code and two memory banks.DRAM00A by memory bank 01A, memory bank 02A, comprise device identification code (ID) declare the bright nurse bus interface 03A that recognizes circuit 05, and the ID register circuit 04A that preserves the device identification code formed.

To the initialization of dynamic random access memory DRAM00A device identification code shown in Figure 7 with declare and recognize process and be explained as follows.When initialization control signal SIn placed logic high " H ", DRAM was initialised.In this state, delay register is set to certain periodicity, and as the write cycle of data, data read cycle or the like also presets mode register in addition, waits with definite different pattern as setting ID register (device identification code).Like this, in ID initialization of register process, the device identification code is set among the ID register circuit 04A.After initialization was finished, initialization control signal SOut became logic high " H ", showed that the initialization of DRAM device is finished.

Adopt device identification to declare and recognize circuit 05A, (in DRAM, be called request package by device identification code and the external instruction that relatively is stored in the ID register circuit when the DRAM00A initialization, hereinafter to be referred as " request package ") in the device identification code that comprises, thereby realize declaring of DRAM00A device identification code shown in Figure 7 recognized.If the storing value of device identification code that comprises in the request package and ID register meets mutually, then DRAM00A confirms that this is request and the instruction of execution request package that it is sent, so that its memory bank A1 and A2 are carried out access.

Fig. 8 shows by two DRAM and is attached to the system that is formed on the controller that each DRAM has a device identification code and two memory banks.DRAM00C and DRAM06C are by as the BusEnable/BusCtrl (enabling bus/control bus) of control signal, as the BusData (data/address bus) of data and control signal, be connected on the controller 12C as the TxClk/RxClk of clock signal and as the SIn/SOut of initialization control signal.DRAM00C comprises memory bank 01C, and memory bank 02C preserves the ID register circuit 04C of DRAM device identification code of relevant memory bank 01C and 02C and a device identification code that is arranged among the interface 03C and declares and recognize circuit 05C.DRAM06C comprises memory bank 07C, and memory bank 08C preserves the ID register circuit 10C of device identification code of relevant memory bank 07C and 08C and a device identification code that is arranged among the interface 09C and declares and recognize circuit 11C.

It is as described below that process is recognized in the initialization of the device identification code system of DRAM shown in Figure 8 and declaring.When initialization control signal SIn placed logic high " H ", initialization procedure began to carry out.In this state, initialization is carried out in setting of the setting of the setting of the delay register of DRAM0C, mode register and ID register etc.When setting the ID register, the device identification code is stored among the ID register circuit 04C.When the initialization of DRAM00C was finished, the initialization control signal SOut that expression DRAM00C initialization is finished became logic high " H ".The SOut of DRAM00C links to each other with the SIn of DRAM06C.Therefore, in case DRAM00C finishes initialization, the initialization of DRAM06C promptly begins to start.In this state, the setting of getting device, mode register and ID register etc. is posted in the time-delay of DRAM06C and carry out initialization; And when the ID register is set, the device identification code is stored among the ID register circuit 10C.

Implement the declaring of DRAM device identification code of system shown in Figure 8 recognized by the device identification code that is stored among ID register 04C and the 10C in the device identification code in the request package that relatively is included in the controller transmission and DRAM00C and the 06C initialization.In above-mentioned comparison, if the storing value of device identification code in the request package and ID register is consistent with each other, can confirm that then this request is at the request with ID register circuit 04C or 10C (wherein in store corresponding to DRAM device identification code) corresponding D RAM00C and 06C.In case confirm by the specific DRAM device of access, then the instruction of relevant this DRAM can obtain to carry out in the request package.

In the system shown in Figure 9, two respectively have the DRAM of a device identification code and a single bank structure to be connected with controller, also have also same this controller of DRAM with a device identification code and two bank structure to link to each other simultaneously.By the BusEnable/BusCtrl control signal, BusData data and control signal, TxClk/RxClk clock signal and SIn/SOut initialization control signal, DRAM00E, DRAM05E link to each other with the same controller 16E of DRAM10E.DRAM00E comprises a memory bank 01E, and one comprises the interface 02E of ID register circuit (preserve device identification code) 03E, and a device identification code is declared and recognized circuit 04E.DRAM05E comprises a memory bank 06E, and one comprises the interface 07E of ID register circuit 08E (preserve device identification code), and a device identification code is declared and recognized circuit 09E.DRAM device 10E comprises memory bank 11E and 12E, and one comprises the ID register circuit 14E interface 13E of (being used to preserve the device identification code), and a device identification code is declared and recognized circuit 15E.

The initialization of this system and that declaring of each DRAM identification code recognized process is as described below.When initialization control signal SIn placed high level " H ", initialization began to start.In this case, initialization is carried out in setting of the setting of the setting of DRAM00E delay register, mode register and ID register etc.When the ID register was set, the device identification code was stored among the ID register circuit 03E.After the initialization of DRAM00E is finished, show that the initialization control signal SOut that the DRAM00E initialization is finished becomes high level " H ", cause the SIn of DRAM05E also to become high level " H ".Thereby DRAM05E begins to carry out initialization.In this case, initialization is carried out in the setting of the setting of DRAM05E delay register, the setting of mode register and ID register etc., and the device identification code is stored in (when the ID register is set) among the ID register circuit 08E.In the initialization of DRAM05E finishes, show that the initialization control signal SOut of the DRAM05E that the DRAM05E initialization is finished becomes high level " H ", the SIn of DRAM10E also becomes high level " H " thus.Thereby the initialization of DRAM10E begins to start.In this case, initialization is carried out in setting of the setting of DRAM10E delay register, the setting of mode register and ID register or the like, and the device identification code is stored in (when the ID register is set) among the ID register circuit 14E.

Be kept at the device identification code among ID register circuit 03E, 08E and the 14E during by the device identification code in the request package that comparison controller sent and DRAM00E, 05E and 10E initialization, the device identification code of system shown in Fig. 9 carried out to declare recognize.This relatively in, if the device identification code that is included in the request package is consistent with each other with the value in the ID register that is kept at specific DRAM, then can confirm DRAM00E corresponding to ID register circuit 03E, 08E or 14E (preserving corresponding to device identification code), the operation requests of DRAM05E or DRAM10E is received, and the instruction in the request package can be performed by the specific DRAM of its ID controlled device request.

Figure 10 represents that a kind of conventional device identification code that is requested DRAM device identification code that is used for storing more DRAM device identification code and request package middle controller and provides is declared and recognizes (affirmation) circuit.This device identification code is declared and is recognized circuit and comprise a change-over gate 01G, one inverter 02G, one inverter 03G, an inverter 04G, a dual input exclusive-OR gate 05G, change-over gate 06G, inverter 07G, inverter 08G, a P channel MOS transistor 09G, an one N-channel MOS transistor 10G and a N-channel MOS transistor 11G.

Change-over gate 01G imports PD (bag data), and PD is a part that is included in the device identification code in the request package, and PD latch signal LATCH and LATCHB are inputed to the grid of N-channel MOS transistor and P channel MOS transistor respectively.The output of change-over gate 01G is imported into the grid of inverter 02G.The output PD-b that is used to latch the inverter 02G of PD is imported into the grid of inverter 03G, and the output of inverter 03G links to each other with the input of inverter 02G.PD-b is input to the grid of inverter 04G.

The output of dual input exclusive-OR gate 05G input inverter 04G and from the IDREG of ID register, IDREG writes among the ID register circuit when initialization.The output of change-over gate 06G input dual input exclusive-OR gate 05G, the output of EVAL and inverter 07G is connected with the grid of N raceway groove with the P channel MOS transistor respectively.The input gate receiving inputted signal EVAL of inverter 07G.Inverter 08G input makes output signal IDHIT be precharged to the input signal PC of high level " H ".

The grid of P channel MOS transistor 09G links to each other with the output of inverter 08G, and source electrode links to each other with power supply, and its drain electrode links to each other with output signal IDHIT.The grid of N-channel MOS transistor 10G links to each other with the output ID-XOR of change-over gate 06G, its source ground (abbreviating " GND " later on as), and its drain electrode links to each other with output signal IDHIT.The same respectively PC of grid, source electrode and the drain electrode of N-channel MOS transistor 11G, GND link to each other with ID-XOR.

It is as described below that device identification code shown in Figure 10 is declared the working condition of recognizing circuit.When external request package, the PC signal becomes high level " H ", and EVAL is low level " L ", and LATCH is high level " H ", and LATCHB becomes low level " L ".In this case, output signal IDHIT is precharged to high level " H ", and the output node ID-XOR of change-over gate is position, the end " L ".When precharge and request package finished receiving, the PC signal became low level " L ", and EVAL becomes high level " H ", and LATCH becomes low level " L ", and LATCHB becomes high level " H ".In this case, PD (bag data) is latched by

inverter

02G and 03G, by dual input exclusive-OR gate 05G value and the IDREG signal (being kept at the part of the ID register in the ID register circuit during initialization) of PD is compared.Result as a comparison, as consistent with each other between them, then ID-XOR will keep low level " L ", just maintain high level " H " when constant when the IDHIT signal, promptly be in " choosing " state, and the instruction in the request package obtains carrying out.If IDREG signal and PD signal value are inconsistent, then ID-XOR becomes high level " H ", and the IDHIT signal becomes low level " L ".That is to say that it is in " sign is chosen (ID-Hit) " state, the instruction in the request package will can be not performed by this DRAM.

As mentioned above, each conventional dram chip has only a device identification code.If so include a plurality of memory banks on the dram chip, its function can not be utilized effectively,, the device identification code recognizes each memory bank because can not declaring respectively.Therefore, if system only has the semiconductor memory chips of a device identification code to constitute by many, the memory cell array block number increases, when simultaneously the control circuit of semiconductor memory does not have any variation, the problem that the storage capacity (quantity of memory cell array block) of increase can not be utilized effectively then will appear.

The object of the present invention is to provide a kind of semiconductor storage, it is characterized in that it can effectively utilize storage (quantity of the cell array blocks) ability of increase.

Semiconductor storage of the present invention comprises: the many memory cell array bodies on a memory chip; And a plurality of identification code registers that are used to discern particular bank or set of memory banks.

That is to say that identification code of the present invention is not to be used to discern certain concrete memory chip, and be used for each independently memory bank or set of memory banks on the recognition memory chip.

By description, will more clearly understand above-mentioned purpose of the present invention and other purpose and advantage thereof and characteristic below in conjunction with accompanying drawing.In the accompanying drawing:

Fig. 1 is the semiconductor memory block diagram according to first embodiment of the invention.

Fig. 2 declares first exemplary circuit figure that recognizes circuit for device identification code in Fig. 1 semiconductor memory.

Fig. 3 declares the operating time figure that recognizes circuit for device identification code among Fig. 2.

Fig. 4 declares second the exemplary circuit figure that recognizes circuit for device identification code in Fig. 1 semiconductor memory.

Fig. 5 is the semiconductor memory block diagram according to second embodiment of the invention.

Fig. 6 is the semiconductor memory block diagram according to third embodiment of the invention.

Fig. 7 is first kind of semiconductor memory block diagram in original technology.

Fig. 8 is second kind of semiconductor memory block diagram in original technology.

Fig. 9 is the third semiconductor memory block diagram in original technology.

Figure 10 is that the semiconductor storage identification code in original technology is declared the circuit diagram of recognizing circuit shown in Fig. 7-9.

Fig. 1 to Fig. 3 represents the first embodiment of the present invention.As shown in Figure 1, first kind of embodiment according to the present invention.As shown in Figure 1, the semiconductor memory according to the first embodiment of the present invention has four memory banks (memory cell array) and two ID register circuits.A DRAM, for example Rumbus DRAM00B comprises

memory bank

01B, 02B, 03B and 04B.ID register circuit 06B in interface 05B preserves the device identification code of relevant memory bank Q (01B) and memory bank R (02B).In interface 05B, also be provided an ID register circuit 07B among this DRAM, be used to preserve the device identification code of relevant memory bank S (03B) and memory bank T (04B).At last, this DRAM also has been provided a device identification code and has declared and recognize circuit 08B, is used for the device identification code of more external request package and the value of the device identification code among ID register circuit 06B and the 07B.

Now, describe initialization and the declaring of device identification code of DRAM00B and recognize at device shown in Figure 1.When initialization control signal SIn placed high level " H ", memory bank 01B and the 02B of DRAM00B obtained initialization.Under this feelings, set delay register, set mode register and setting ID register or the like and obtain initialization.When the ID register was set, the device identification code was stored among the ID register circuit 06B of device identification code of relevant memory bank 01B of preservation among the interface 05B and 02B.After the initialization of finishing

memory bank

01B and 02B,

memory bank

03B and 04B obtain initialization.In this case, set delay register, setting mode register and setting ID register or the like and obtain initialization.When the ID register was set, the device identification code was stored among the ID register circuit 07B that preserves

relevant memory bank

03B and 04B device identification code among the interface 05B.After finishing the initialization of

memory bank

03B and 04B, initialization control signal SOut becomes high level " H ", can start the initialization to other device.

Whether the device identification code that is kept in the ID register circuit during with initialization by the device identification code in the relatively outside request package that transmits conforms to, and whether the device identification code is declared and recognized device that circuit 08B determines DRAM00B shown in Figure 1 and discern and be requested.This relatively in, if the device identification code in the request package conforms to the storage values in

ID register circuit

06B or 07B (storing corresponding to device identification code), can confirm that then this is the request of memory bank Q (01B) and memory bank R (02B) or memory bank S (03B) and memory bank T (04B), and the instruction of request package obtains carrying out (sign is chosen (ID-Hit) executing state).If they are not consistent, request can not obtain carrying out (sign is not chosen (ID-Miss) state).

Fig. 2 declares first example of recognizing circuit 08B for device identification code shown in Figure 1.The device identification code is declared and is recognized circuit 08B and comprise change-over gate 01H, inverter 02H, inverter 03H, inverter 04H, two-way input exclusive-OR gate 05H, inverter 07H, change-over gate 06H, N-channel MOS transistor 11H, N-channel MOS transistor 10H, inverter 08H, P channel MOS transistor 09H, two-way input exclusive-OR gate 12H, change-over gate 13H, N-channel MOS transistor 17H, N-channel MOS transistor 16H, inverter 14H, P channel MOS transistor 15H and dual input exclusive-OR gate 18H.

Change-over gate 01H input is as the PD (bag data) of request package data, and latch signal LATCH and LATCHB are input to the grid of N raceway groove and P channel MOS transistor respectively.An output of this change-over gate is input to the input of inverter 02H.For latching PD, the output PD-b of inverter 02H is input to the grid of inverter 03H, and the output of inverter 03H links to each other with the input of inverter 02H.Inverter 04H imports PD-b, output PD-t.

Dual input exclusive-OR gate 05H is input as IDREG-QR and PD-t, and the former is for being kept among the ID register circuit IP-X (06B) part about the device identification code of

memory bank

01B and 02B, and the latter is the output of inverter 04H.Inverter 07H is at its input received signal EVAL.The output that is input as dual input exclusive-OR gate 05H of change-over gate 06H, the output of EVAL and inverter 07H are input to the grid of N-channel MOS transistor and P channel MOS transistor respectively.The output BANK-QR-XOR of change-over gate 06H links to each other with the drain electrode of N-channel MOS transistor 11H, and PC (precharge) signal links to each other with its grid, and GND is connected with its source electrode.

The grid of N-channel MOS transistor 10H links to each other with the output BANK-QR-XOR of change-over gate 06H, and its source electrode links to each other with GND, and its drain electrode is connected with output signal BANK-QR.Inverter 08H is input to PC its grid.The grid of P channel MOS transistor 09H is connected with the output of inverter 08H.Source electrode links to each other with power supply, and its drain electrode is connected with the BANK-QR output signal.Dual input exclusive-OR gate 12H is input as IDREG-ST signal and PD-t signal, and the former is for being kept in the ID register circuit part about the device identification code of memory bank S (03B) and T (04B), and the latter is the output of inverter 04H.The N-channel MOS transistor of change-over gate 13H and the grid of P channel MOS transistor are imported in the output that is input as dual input exclusive-OR gate 12H of change-over gate 13H, the output of EVAL and inverter 07H respectively.

The drain electrode of N-channel MOS transistor 17H links to each other with the output signal BANK-ST-XOR of change-over gate 13H, and the same PC of its grid (precharge) signal links to each other, and its source electrode is connected with GND.The output BANK-ST-XOR of change-over gate 13H also links to each other with the grid of N-channel MOS transistor 16H simultaneously.The source electrode of N-channel MOS transistor 16H links to each other with GND, and its drain electrode links to each other with output signal BANK-ST.The grid of inverter 14H receives the PC signal.The grid of P channel MOS transistor 15H is connected with the output of inverter 14H, and its source electrode links to each other with power supply, and its drain electrode is connected with the BANK-ST output signal.Dual input or door 18H input BANK-QR signal and BANK-ST signal, output IDHIT signal.

Narration now utilize shown in Figure 2 declare recognize device identification code that circuit 08B realizes and declare and recognize process.As shown in Figure 3, as from the request package of outside the time, the PC signal is high level " H ", and EVAL is in low level " L ", and LATCH is high level " H ", and LATCH is in low level " L ".In this case, output signal BANK-QR and BANK-ST are precharged to high level " H ", and BANK-QR-XOR node and BANK-ST-XOR node are in low level " L ".On the other hand, the PD as a part of device identification code in the request package data is latched by inverter 02H and 03H.Device identification code IDREG-QR and IDREG-ST that the PD that is latched is kept in the ID register circuit during with initialization by two-way input exclusive-

OR gate

05H and 12H compare.As this result relatively, if consistent with each other between them, then the dual input exclusive-OR gate is exported a low level " L ".On the other hand, if different between them, then the dual input exclusive-OR gate is exported a logic-high signal " H ".Thereby when terminal BANKQR exported a high level signal,

memory bank

01B and 02B can work, and allowed memory bank Q (01B) and R (02B) are carried out access as reading or writing etc.On the other hand, if logic-high signal is exported by terminal BANK ST, then memory bank S (03B) and T (04B) can work, and allow these memory banks of access.

When high level signal was exported by terminal BANK ST or terminal BANK QR, signal IDHIT was by the output output of OR circuit 18H.The device identification code that this signal IDHIT is kept in the ID register circuit when showing device identification code in the external request package and initialization is consistent with each other.When sign was agreed with, instruction was able to comprising

memory bank

01B, 02B in the request package, and 03B and 04B carry out at interior DRAM memory chip, even the output signal of terminal BANK ST makes

memory bank

03B and 04B for can not start attitude.That is to say that signal IDHIT relates to is request to dram chip 00B, and signal BANK-QR and BANK-ST reflection is the state of activation of

particular bank

01B, 02B, 03B and 04B or the state of activation of set of

memory banks

01B and 02B and 03B and 04B.

Fig. 4 declares second example recognizing circuit 08B for the device identification code.Device identification is declared and is recognized circuit 08B and comprise change-over gate 01J, inverter 02J, inverter 03J, inverter 04J, three tunnel input exclusive-OR gate 05J, inverter 07J, change-over gate 0JH, N-channel MOS transistor 11J, N-channel MOS transistor 10J, inverter 08J, P channel MOS transistor 09J, dual input exclusive-OR gate 12J, change-over gate 13J, N-channel MOS transistor 17J, N-channel MOS transistor 16J, inverter 14J, and P channel MOS transistor 15J.

Change-over gate 01J comprises a P channel MOS transistor that receives the N-channel MOS transistor of LATCH signal input and receive the input of LATBH signal.The output of change-over gate 01J is imported into the grid of inverter 02J.For latching PD, the output PD-b of inverter 02J delivers to the grid of inverter 03J, and the output of inverter 03J links to each other with the input of inverter 02J.Inverter 04J input PD-b signal, output PD-t signal.Three tunnel input exclusive-OR gate 05J inputs be as the IDREG-QR that is kept in the ID register circuit about the device identification code part of

memory bank

01B and 02B, as the TDREG-ST that remains in the ID register circuit about the device identification code part of

memory bank

03B and 04B, and the output PD-t of inverter 04J.The input receiving inputted signal EVAL of inverter 07J.The output that is input as three tunnel input exclusive-OR gate 05J grid, response EVAL signal that delivered to N-channel MOS transistor and P channel MOS transistor respectively of change-over gate 06J and the output of inverter 07J.

The drain electrode of N-channel MOS transistor 11J links to each other with the output ID-XOR of change-over gate 06J, and grid inserts precharge PC signal, and source electrode links to each other with GND.The grid of N-channel MOS transistor 10J links to each other with the output ID-XOR of change-over gate 06J, and source electrode links to each other with GND, and drain electrode links to each other with output signal IDHIT.The input of inverter 08J receives the PC signal.The output of inverter 08J links to each other with the grid of P channel MOS transistor 09J, and the source electrode of transistor 09J and power supply join, and the drain electrode of output signal IDHIT and transistor 09J is joined.Two-way input exclusive-OR gate 12J input IDREG-QR signal, this signal are a part that is kept in the ID register circuit about the device identification code of

memory bank

03B and 04B; Another is input as the PD-t signal, and it is the output of inverter 04J.

The grid of N-channel MOS transistor and P channel MOS transistor is delivered in the output that is input as dual input exclusive-OR gate 12J of change-over gate 13J, the output of EVAL signal and inverter 07J respectively.The drain electrode of N-channel MOS transistor 17J links to each other with the output BANK-XOR of change-over gate 13J, and grid links to each other with the PC precharging signal, and source electrode joins with GND.The grid of N-channel MOS transistor 16J links to each other with the output BANK-XOR of change-over gate 13J, and source electrode joins with GND, and drain electrode links to each other with output signal BANK-QR.The input of inverter 14J receives the PC signal.The grid of P channel MOS transistor 15J links to each other with the output of inverter 14J, and source electrode links to each other with power supply, and drain electrode links to each other with output signal BANK-QR.

Illustrate that now device identification code shown in Figure 4 declares the course of work of recognizing circuit 08B.The device identification code is declared and recognized circuit 08B is that declaring of whether meeting mutually between a kind of device identification code that is used to differentiate the request device identification code of confirming each memory bank or set of memory banks and preservation recognized circuit.When external request package, precharging signal PC is high logic level " H ", and the EVAL signal is low level " L ", and the LATCH signal is high level " H ", and the LATBHB signal is low level " L ".In this case, output signal IDHIT and BANK-QR are precharged to high logic level " H ".Simultaneously, ID-XOR and BANK-XOR node become low logic level " L ".On the other hand, the PD as an identification code part in the request package data is latched by inverter 02J and 03J.Three tunnel input exclusive-OR gate 05J compare IDREG-QR and the IDREG-ST that the PD that latchs is kept at the device identification code part in the ID register circuit with as initialization the time.Deposit in during by dual input exclusive-OR gate 12J between the IDREG-QR of the device identification code part in the ID register circuit and the latch signal PD-t of IDREG-ST signal and whether conform to, among judging memory bank Q (01B) and R (02B) or memory bank S (03B) and T (04B), whether have a memory bank selected with PD relatively as initialization.By precharge, and when latching of request package also finished, the PC signal became low level " L " at IDHIT and BANK-QR, and the EVAL signal becomes high level " H ", and latch signal LATCH becomes low level " L ", and LATCHB becomes high level " H ".At this moment, the result who compares by three tunnel input exclusive-OR gate 05J and dual input exclusive-OR gate 12J is sent to ID-XOR and BANK-XOR respectively.

Result as a comparison, if three values PD, IDREG-QR and IDREG-ST are different, then three tunnel input exclusive-OR gate 05J are output as low level " L ", and the output signal of IDHIT is maintained at high level " H " (the high level here " H " expression sign is not chosen (ID-Miss) state).In other words, request package instruction is not stored the device chip and accepts and carry out.If there is one to conform to PD among IDREG-QR and the IDREG-ST, the outputs of three tunnel input exclusive-OR gate 05J then are high level " H ", and output signal IDHIT is low level " L " (sign is chosen (ID-Hit) state).In other words, the instruction in the request package can be stored the device chip and accepts and carry out.Comparative result as dual input exclusive-OR gate 12J, if IDREG-QR is consistent with latch signal PD, then the output of dual input exclusive-OR gate 12J becomes low level " L ", and output signal BANK-QR is maintained at high level " H ", thereby chooses memory bank Q (01B) and R (02B).In addition, if result relatively for IDREG-QR with latch PD and do not conform to mutually, then dual input exclusive-OR gate 12J is output as high level " H ", output signal BANK-QR becomes low level " L ", thereby chooses memory bank S (03B) and T (04B).Declare the time diagram of recognizing operation in second example and be omitted, similar because of it with situation shown in Figure 3, can get rid of signal BANK-ST.

The present invention both had been applicable to selected single memory bank, was applicable to selected a plurality of memory banks too, only needed as Fig. 2 and dual circuit A, B, C and the D of utilizing shown in Figure 4, for each memory bank of memory cell array provides output signal.

Figure 5 shows that the semiconductor storage in the second embodiment of the invention.The design feature of this semiconductor memory is: dram chip 00D is by control signal BusEnable, the TxClk and the RxClk of BusCtrl and BusData (data and control signal), clock signal, and the SIn of initialization control signal is connected with controller 09D.The formation of DRAM 00D comprises memory bank 01D, memory bank 02D, memory bank 03D, memory bank 04D, preserve the ID register 06D of the device identification code of

relevant memory

01D and 02D among the interface 05D, preserve the ID register circuit 07D of the device identification code of

relevant memory

03D and 04D among the interface 05D, and one is configured in device identification code among the interface 05D and declares and recognize circuit 08D.

Initialization and declaring of device identification code that DRAM 00D shown in Figure 5 now is described are recognized process.When initialization control signal SIn was set in high level " H ", memory bank 01D and memory bank 02D were able to initialization.In this case, set a delay register, setting one mode register and setting ID register or the like and be able to initialization, and the device identification code is stored among the ID register circuit 06D.After the initialization of finishing memory bank Q (01D) and memory bank R (02D), the initialization of memory bank S (03D) and memory bank T (04D) starts.In this case, set delay register, setting mode register and setting ID register or the like and be able to initialization, the device identification code is stored among the ID register circuit 07D.After this, show that the initialization control signal SOut that initialization is finished becomes high level " H ".

Utilize identification code to declare and recognize circuit 08D, by in the request package of relatively coming self-controller 09D be requested device identification code and initialization the time DRAM 00D be kept at the device identification code among the ID register ID-C of memory bank Q (01D) and R (02D) and be kept at device identification code among the ID register ID-D of memory bank S (03D) and T (04D), the declaring of device identification code of DRAM 00D shown in the embodiment 5 recognized in the time of can carrying out.Result as a comparison, if in the ID register of device identification code and memory bank Q (01D) and R (02D) or with the ID register of memory bank S (03D) and T (04D) in device identification code (sign is chosen (ID-Hit) state) consistent with each other, then come the request package instruction of self-controller 09D performed by the DRAM memory chip.Yet if their inconsistent (sign are not chosen (ID-Miss) state), request is not performed.Among Fig. 5 the device identification code declare the structure of recognizing circuit 08D can be as Fig. 2 or shown in Figure 4, also can adopt the structure of logical operation of necessity of other any memory bank ID that carries out the memory bank ID that relatively preserves and request.

Fig. 6 represents the semiconductor memory according to third embodiment of the invention.The design feature of this semiconductor memory is: DRAM 00F is by control signal BusEnable, the TxClk and the RxClk of BusCtrl signal and BusData signal (data and control signal), clock signal, and the SIn of initialization control signal is connected with controller 10F.The formation of DRAM00F comprises memory bank 01F, memory bank 02F, memory bank 03F, memory bank 04F, preserve the ID register 06F of relevant memory 01F device identification code among the interface 05F, preserve the ID register circuit 07F of relevant memory bank 02F device identification code among the interface 05F, preserve the ID register circuit 08F of relevant memory bank 03F and memory bank 04F device identification code among the interface 05F, and be configured in identification code in the interface 05F and declare and recognize circuit 09F.

Initialization and declaring of device identification code that DRAM 00F shown in Figure 6 now is described are recognized process.When initialization control signal SIn placed high level " H ", memory bank 01F obtained initialization.In this case, set delay register, setting one mode register and setting ID register or the like operation and be achieved, identification code is kept among the ID register circuit 06F.After memory bank 01F realizes initialization, memory bank 02F is begun to carry out initialization, implement setting to delay register, mode register and ID register or the like, identification code is stored among the ID register circuit 07F.After the initialization of finishing memory bank 02F, begin to start the initialization of memory bank 03F and memory bank 04F, to implement to set delay register, mode register, ID register or the like, identification code is kept among the ID register circuit 08F.After this, show that the initialization control signal SOut that initialization had been finished already becomes high level " H ".

Because the identification code among Fig. 6 is declared and recognized circuit 09F and include three ID register circuits, it can add the circuit that dotted line A surrounds by an output of circuit that dotted line B among Fig. 2 is surrounded and this circuit and obtains, so that one three tunnel input exclusive-OR gate to be provided.Perhaps, identification code among Fig. 6 is declared and is recognized circuit 09F and also can constitute by following manner: add the device identification code data in the ID register circuit that is added on the dual input exclusive-OR gate that Fig. 4 dotted line C is enclosed, so that one three tunnel input exclusive-OR gate to be provided, increase the circuit that is used to discern memory bank shown in another dotted line D simultaneously.

According to the present invention, because semiconductor memory chips have the structure of the device identification code of preserving each cell array memory bank (or set of memory banks) of many identifications, the increase of the storage capacity of the semiconductor storage unit that integrated level improves constantly (as DRAM) can be utilized effectively.

Above-mentioned explanation clearly illustrates that the present invention is not limited to the foregoing description, can make amendment and change it, and not departing from scope of the present invention and aim.For example, memory bank 01B can combine by identical address date with 03B.In addition, can adopt with above-mentioned declare recognize other different various logic circuitry of circuit so that the matching between the ID request numerical value that provides in the ID numerical value stored in the memory bank recognized in the single memory chip or the set of memory banks and the request package to be provided, as long as circuit can provide correct discriminating to wanting selecteed memory bank.

Claims

1, a kind of semiconductor storage is characterized in that, it comprises:

A plurality of memory banks on a semiconductor chip; And

Have the structure of preservation corresponding to a plurality of identification codes of each memory bank.

2, semiconductor storage as claimed in claim 1 is characterized in that, the wherein said device that is used to preserve described identification code is made up of many registers.

3, semiconductor storage as claimed in claim 2 is characterized in that, it also comprises:

The request identification code is recognized structure with being kept at declaring that described identification code in the described register compares.

4, semiconductor storage as claimed in claim 3, it is characterized in that, when the described identification code of preserving in described request identification code and at least 1 the described register meets mutually, be stored in the corresponding described memory bank of identification code described in the described register can be by access.

5, semiconductor storage as claimed in claim 4 is characterized in that, wherein said identification code is stored in the described register when carrying out initialization.

6, semiconductor storage as claimed in claim 4 is characterized in that, wherein said a plurality of memory banks comprise first and second memory banks at least; Described a plurality of register comprises first and second registers at least; Described declare recognize structure and comprise: be used for when the identification code that is stored in described first register and described request identification code meet mutually, described first memory bank being exported first logical circuit of first request signal; When the identification code that is stored in described second register and described request identification code are consistent with each other, described second memory bank is exported second logical circuit of second request signal with being used for.

7, semiconductor storage as claimed in claim 6, it is characterized in that, wherein said declare recognize structure and further comprise and be used to the storage device chip to produce the 3rd request signal, to respond one of them the 3rd logical circuit of output of described first and second request signals.

8, semiconductor storage as claimed in claim 4 is characterized in that, wherein said a plurality of memory banks comprise first and second memory banks; Described identification code is declared and is recognized circuit and comprise: when being used for identification code in being stored in described first register of a plurality of register and described request identification code and meeting mutually, export first logical circuit of first request signal for described first memory bank; Be used for a identification code in being stored in described a plurality of register when consistent with the described request identification code, be second logical circuit of one second request signal of its device output.

9, a kind of semiconductor storage is characterized in that, it comprises:

The semiconductor chip that a plurality of memory banks are arranged thereon;

First register of storage first identification code;

One second register; And

The request identification code be stored in described first identification code in described first register when consistent with each other, produce one in order at least 1 memory bank in described a plurality of memory banks and described device itself are carried out the request signal of access.

10, semiconductor storage as claimed in claim 9 is characterized in that,

Described second register-stored, second identification code; And further comprise

The sign that the identification code of described request identification code and described first and second storages is compared is declared and is recognized circuit.

11, semiconductor storage as claimed in claim 10 is characterized in that, described sign is declared and recognized circuit output described request signal.

12, semiconductor storage as claimed in claim 11 is characterized in that, described sign is declared and recognized circuit and comprise:

Be used for when described first identification code that is stored in described first register and described request identification code are consistent with each other, exporting first logical circuit of first signal; Be used for when described second identification code that is stored in described second register and described request identification code are consistent with each other second logical circuit of output secondary signal;

Wherein said first signal is used as the described request signal of described first memory bank of request and described device itself, and described secondary signal is used as the described request signal of described second memory bank of request and described semiconductor chip.

13, semiconductor storage as claimed in claim 11 is characterized in that, described sign is declared and recognized circuit and comprise:

Be used for recognizing first logical circuit that sign indicating number is exported one first signal when consistent with the described request identification code when described first mark that is stored in described first register, second logical circuit that is used for output secondary signal when described first and second identification codes have to conform to the described request identification code

Described first signal is used as described first memory bank of request, and described secondary signal is used as the described semiconductor chip of request.

14, a kind of semiconducter memory system is characterized in that, it comprises a controller; The semiconductor memory chip, described semiconductor memory chips comprise:

At least one first memory bank and second memory bank;

Storage is used to declare first register of recognizing first identification code whether described first memory bank asked;

Storage is used to declare second register of recognizing second identification code whether described second memory bank asked; And

Identification code with following operating function is declared and recognized circuit: when the 3rd identification code that receives from described controller conformed to described first identification code, described identification code was declared and is recognized first request signal of asking described first memory bank and described semiconductor memory chips of circuit output; When described the 3rd identification code that receives from described controller conformed to described second identification code, described identification code was declared second request signal of recognizing described second memory bank of request of circuit output and described semiconductor memory chips.

15, system as claimed in claim 14 is characterized in that, described identification code is declared and recognized circuit and comprise:

Be used to latch the latch cicuit of described the 3rd identification code;

Respond described first identification code that is stored in described first register produces first signal with being latched in described the 3rd identification code in the described latch cicuit first logical circuit;

Respond described second identification code that is stored in described second register produces secondary signal with being latched in described the 3rd identification code in the described latch cicuit second logical circuit;

Receive described first signal and control signal and have first semiconductor circuit of first output, when described control signal is in first logic level, described first semiconductor circuit is no matter how described first signal makes described first output in a certain voltage levvl, and when described control signal was in second logic level, it was at one of described first output output and corresponding the 3rd signal of described first signal;

Receive described secondary signal and described control signal and have second semiconductor circuit of second output, when described control signal is in described first logic level, described second semiconductor circuit is no matter how described secondary signal makes described second output in a certain voltage levvl, and when described control signal was in second logic level, it was at one of described second output output and corresponding the 4th signal of described secondary signal; And

Respond described third and fourth signal and produce oppose described semiconductor memory chips of a usefulness and propose the 3rd logical circuit of the 5th signal of described request.

16, system as claimed in claim 14 is characterized in that, described identification code is declared and recognized circuit and comprise:

Be used to latch the latch cicuit of described the 3rd identification code;

Response is stored in described first identification code in described first register, is stored in described second identification code in described second register and is latched in described the 3rd identification code in the described latch cicuit and produces first logical circuit of first signal;

Respond described first identification code that is stored in described first register produces secondary signal with being latched in described the 3rd identification code in the described latch cicuit second logical circuit;

Receive described first signal and control signal and have first semiconductor circuit of first output, when described control signal is in first logic level, described first semiconductor circuit is no matter how described first signal makes described first output in a certain voltage levvl, when described control signal was in second logic level, it was at one of described first output output and corresponding the 3rd signal of described first signal;

Receive described secondary signal and described control signal and have second semiconductor circuit of second output, when described control signal is in described first logic level, described second semiconductor circuit is no matter how described secondary signal makes described second output in a certain voltage levvl, when described control signal was in second logic level, it was at one of described second output output and corresponding the 4th signal of described secondary signal;

Wherein said the 3rd signal described request of the described semiconductor memory chips of opposing, described the 4th signal described request of described first memory bank of opposing.

17, a kind of access method at least one memory bank in the semiconductor memory chips is characterized in that, said method comprising the steps of:

The a plurality of identification codes of storage in each register of described semiconductor chip;

Described identification code of importing outside described semiconductor storage and the described a plurality of identification codes that are stored in each register are compared;

From the described identification code of the described outside input of described semiconductor storage unit be stored in each register described a plurality of identification codes in one of when identical, for the request access at least one with corresponding described memory bank of the described identification code that conforms to and the described semiconductor memory chips of access, produce one first signal.

18, as the method that claim 17 proposed, it is characterized in that it further comprises the execution in step of instruction, promptly respond described first signal carry out to the instruction of the described corresponding described memory bank of identification code that conforms to.