CN1208901C - Test method and circuit for successive approximation A/D conversion integrated circuit - Google Patents
Test method and circuit for successive approximation A/D conversion integrated circuit Download PDFInfo
- Publication number
- CN1208901C CN1208901C CN 01110247 CN01110247A CN1208901C CN 1208901 C CN1208901 C CN 1208901C CN 01110247 CN01110247 CN 01110247 CN 01110247 A CN01110247 A CN 01110247A CN 1208901 C CN1208901 C CN 1208901C
- Authority
- CN
- China
- Prior art keywords
- voltage
- value
- integrated circuit
- successive approximation
- conversion integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to a test method and a circuit for a successively approximate A/D conversion integrated circuit, which is suitable for the detection of the successively approximate A/D conversion integrated circuit allowing a voltage error value. The method firstly proposes a simulation sampling voltage and a digital sampling value representing the simulation sampling voltage; subsequently, an upper-limit value/ a lower-limit value of the voltage obtained by adding/subtracting the digital sampling value to/from the voltage error value is input; finally, whether the successively approximate A/D conversion integrated circuit is in accordance with the specification or not is judged by respectively comparing the simulation sampling voltage with the upper-limit value / the lower-limit value of the voltage.
Description
Technical field
The present invention relates to the method for testing of a kind of mould/number conversion integrated circuit, relate in particular to the method for testing of a kind of successive approximation mould/number conversion integrated circuit.
Background technology
Figure 1A illustrates the circuit diagram of the mould/number conversion integrated circuit (hereinafter referred to as ADCIC) of common application.Figure 1B is illustrated among the ADCIC, is the sequential chart of digital signal with analog signal conversion.Must more just can obtain the digital translation value by layering by the mould among this ADCIC of what/number conversion method, successive approximation mould/number conversion integrated circuit therefore is otherwise known as.
Successive approximation ADCIC 100 comprises a comparator 105 and an A/D converter integrated circuit 110.Usually the ADCIC 100 that uses has several digital output ends, the digital signal that these output outputs are become by analog signal conversion.In transfer process, shown in Figure 1B, successive approximation mould/number conversion integrated circuit 100 at first is set at 1 with highest significant position, compares Hou in the analog signal voltage value with input, smaller by what analog signal voltage value, so the highest significant position of numeral output is set at 0.Your Hou is carried out same operation to follow-up position, up to all digital output bits all be set finish till.The Analog signals'digital conversion value of resulting numeral output this moment bit group (as the output of the numeral among Figure 1B 01101011) expression input.
After obtaining such set of number output bit group, just can begin the index test program.Fig. 1 C illustrates the method flow diagram of using when usually the successive approximation A/D converter being detected.At first, in step S100, must at first be provided for the digital preset value of comparing, and set the sampling value that a digital therewith preset value is equal to, so that carry out follow-up operation with above-mentioned digital translation value.In addition, going back the specification error coefficient is 0.Next, among step S105, judge whether sampling value and digital translation value be identical.If identical, then this A/D converter is up to specification; As if different, just must carry out next step testing process, just step S110.Among step S110, error coefficient is added 1.The purposes of this error coefficient is to multiply each other with least significant bit, draws error amount.Afterwards, in step S115, will whether default fixed value of big what be judged to error coefficient, to guarantee that just error amount is still in the scope of allowing.And when this default fixed value of the big what of error coefficient, then this successive approximation A/D converter just falls short of specifications, otherwise then need carry out next step test.
In step S120, digital preset value is added that the value that obtains after the error amount is set at sampling value.Afterwards, in step S125, again sampling value and digital translation value are compared.If both are identical, then this successive approximation A/D converter is up to specification; And work as both not simultaneously, just must carry out step S130.Step S130 deducts digital preset value that resulting value is set at sampling value after the error amount, turns back to step S105 afterwards, continues to carry out test operation, up to judge this successive approximation A/D converter whether up to specification till.
Whether suppose admissible error amount within 3 least significant bits, then must do 7 tests altogether at most, it is up to specification just to determine this successive approximation A/D converter.And along with the increase of the ratio between tolerance and the least significant bit value, number of times that must test will be more.
In sum, usually when whether test successive approximation A/D converter is up to specification, must repeatedly tests just and can finish.And the number of times of test can increase along with the increase of the ratio between tolerance value and the least significant bit value.
Summary of the invention
The objective of the invention is to propose the method for testing of a kind of successive approximation mould/number conversion integrated circuit, this method is applicable to the test to the successive approximation mould/number conversion integrated circuit of allowing a voltage error value.
The technical scheme that realizes purpose of the present invention is as follows: the method for testing of a kind of successive approximation mould/number conversion integrated circuit, be applicable to allowing the successive approximation mould/number conversion integrated circuit of a voltage error value, comprise: propose an analog sample voltage and represent a digital sampling value of this analog sample voltage; Import the upper voltage limit value that this digital sampling value adds that this voltage error value draws, and import this digital sampling value and deduct the lower voltage limit value that this voltage error value draws; This analog sample voltage is compared with this upper voltage limit value and this lower voltage limit value respectively; When this simulation test voltage during greater than this upper voltage limit value, then this successive approximation mould/number conversion integrated circuit falls short of specifications; And when this analog sample voltage during less than this lower voltage limit value, then this successive approximation mould/number conversion integrated circuit falls short of specifications.
According to the further design of method of testing of the present invention, wherein upper voltage limit value system is added after the voltage error value by digital sampling value, the aanalogvoltage that draws via D/A switch.And lower voltage limit value system is deducted by this digital sampling value after the voltage error value, the aanalogvoltage that draws via D/A switch.
In sum, the present invention is greater than or less than the digital voltage of a voltage error value of analog sample voltage by input, through after the D/A switch, directly detects whether successive approximation mould/number conversion integrated circuit is up to specification.Therefore, the step and the time of many tests have been saved.
Description of drawings
Also the present invention is described further in conjunction with the accompanying drawings will to contrast preferred embodiment below, so that deepen the above-mentioned purpose of invention, the understanding of feature and advantage.Shown in the figure:
Figure 1A is the circuit diagram of common applied mould/number conversion integrated circuit;
Figure 1B is for becoming analog signal conversion the sequential chart of digital signal in successive approximation mould/number conversion integrated circuit;
Fig. 1 C detects the employed method flow diagram of successive approximation A/D converter usually;
Fig. 2 is an implementation method flow chart according to one preferred embodiment of the present invention;
Fig. 3 is the circuit structure diagram of another preferred embodiment of the present invention; With
Fig. 4 A-4C is that the various of result's output of the present invention may situation.
Wherein:
100,200: successive approximation mould/number conversion integrated circuit
105,210: comparator
110,205: D/A
Embodiment
A kind of method flow diagram of one embodiment of the present invention shown in Fig. 2.Present embodiment is applicable to the test to the successive approximation mould/number conversion integrated circuit of allowing a voltage error value.At first, in step S200, the analog sample voltage Vat that system's proposition is used to detect, and according to the rules, Vat carries out mould/number conversion to this analog sample voltage, draws the digital sampling value Dat of this analog sample voltage of expression Vat.Afterwards, in step S205, digital sampling value Dat adds tolerance value Err, and by D/A switch, draws upper voltage limit value Vup; In addition, deduct tolerance value Err, pass through D/A switch again, draw lower voltage limit value Vdn by digital sampling value Dat.Next, in step S210, analog sample voltage Vat is compared with upper voltage limit value Vup and lower voltage limit value Vdn respectively.Only when analog sample voltage Vat was between upper voltage limit value Vup and lower voltage limit value Vdn, then successive approximation mould/number conversion integrated circuit was just up to specification.If analog sample voltage Vat is bigger than upper voltage limit value Vup, or littler than lower voltage limit value Vdn, then this successive approximation mould/number conversion integrated circuit falls short of specifications.
Wherein, when the size to upper voltage limit value Vup and analog sample voltage Vat compares, at first digital sampling value Dat is added the admissible error value, become upper voltage limit value Vup through D/A switch, afterwards, compare with analog sample voltage Vat with this upper voltage limit value Vup again.Equally, when the size to lower voltage limit value Vdn and analog sample voltage Vat compares, at first digital sampling value Dat is deducted the admissible error value, become lower voltage limit value Vdn through D/A switch, afterwards, again lower voltage limit value Vdn and analog sample voltage Vat are compared.
The circuit structure diagram of one embodiment of the present invention shown in Fig. 3.This circuit structure is applicable to and utilizes an analog sample voltage that the successive approximation mould/number conversion integrated circuit of allowing a voltage error value is detected.In addition, analog sample voltage can convert a digital sampling value to according to the preset value of setting in accordance with regulations.
In the present embodiment, successive approximation mould/number conversion integrated circuit 200 comprises a comparator 210 and a D/A 205.Wherein, be transfused in the D/A 205 by digital I/O end DI/O digital voltage value, and convert this digital voltage value to analog voltage.The analog sample voltage that is used for detecting this successive approximation mould/number conversion integrated circuit 200 is transfused to comparator 210 by analog input end IN.Comparator 210 will be compared this analog sample voltage and above-mentioned analog voltage, and the comparative result that draws after will be relatively is by output Ro output.
Wherein, above-mentioned digital voltage value is to be added digital higher limit drawing behind the error amount or deducted a digital lower limit that draws behind the error amount by digital sampling value by digital sampling value.In addition, the comparative result by output Ro output has several situations.As shown in Fig. 4 A-4C, several possible comparative result output situations are arranged.In Fig. 4 A, between the time T 0 to T1, because digital input voltage (being above-mentioned digital voltage value) is less than analog input voltage (being above-mentioned analog sample voltage), the current potential of exporting via comparator 210 is electronegative potential (or generally being commonly referred to as 0 in binary system).And between time T 1 to T2, because digital input voltage is greater than analog input voltage, so the current potential of exporting via comparator 210 is high potential (or generally being commonly referred to as 1 in binary system).If the result is identical with above-mentioned condition in test output, illustrate that then this successive approximation mould/number conversion integrated circuit is up to specification.
Must be noted that in Fig. 4 A it is to compare with digital higher limit and analog sample voltage earlier, compare with digital lower limit and analog sample voltage again, so the comparator that draws output result is 01.But if compare with digital lower limit and analog sample voltage earlier, more digital higher limit and analog sample voltage are compared, if successive approximation mould/number conversion integrated circuit is up to specification, then exporting the result should be 10.
Output result at successive approximation mould shown in Fig. 4 B and the 4C/may occur when the number conversion integrated circuit falls short of specifications.In Fig. 4 B, because digital input voltage (comprising digital higher limit and digital lower limit) is always less than analog input voltage, so the output result is high potential (with 1 expression).On the contrary, in Fig. 4 C, because digital input voltage (comprising digital higher limit and digital lower limit) is always all greater than analog input voltage, so the output result is electronegative potential (with 0 expression).Thus also as can be seen, according to different output results, can also judge this reason that successive approximation mould/the number conversion integrated circuit falls short of specifications.
In sum, advantage of the present invention is very tangible.The present invention not only can save the step and the time of many tests, and when finding after tested to fall short of specifications, can also further learn the reason that falls short of specifications.
Though only the preferred embodiments of the present invention are disclosed above, yet above preferred embodiment does not play the qualification effect to the present invention.Any one of skill in the art can make change and change to above preferred embodiment, still can not depart from the spirit and scope of the present invention.
Claims (1)
1. the method for testing of successive approximation mould/number conversion integrated circuit is applicable to the test of the successive approximation mould/number conversion integrated circuit of allowing a voltage error value, comprising:
Propose an analog sample voltage and represent a digital sampling value of this analog sample voltage;
Import this digital sampling value adds that this voltage error value draws behind D/A switch a upper voltage limit value, and import this digital sampling value deduct the lower voltage limit value that this voltage error value draws behind D/A switch;
This analog sample voltage is compared with this upper voltage limit value and this lower voltage limit value respectively;
When this analog sample voltage during greater than this upper voltage limit value, then this successive approximation mould/number conversion integrated circuit falls short of specifications; And
When this analog sample voltage during less than this lower voltage limit value, then this successive approximation mould/number conversion integrated circuit falls short of specifications.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110247 CN1208901C (en) | 2001-04-04 | 2001-04-04 | Test method and circuit for successive approximation A/D conversion integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110247 CN1208901C (en) | 2001-04-04 | 2001-04-04 | Test method and circuit for successive approximation A/D conversion integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1378344A CN1378344A (en) | 2002-11-06 |
| CN1208901C true CN1208901C (en) | 2005-06-29 |
Family
ID=4658448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01110247 Expired - Fee Related CN1208901C (en) | 2001-04-04 | 2001-04-04 | Test method and circuit for successive approximation A/D conversion integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1208901C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438340C (en) * | 2006-01-24 | 2008-11-26 | 华为技术有限公司 | Method for detecting AD converter |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012191412A (en) * | 2011-03-10 | 2012-10-04 | Advantest Corp | Apparatus and method for testing a/d converter |
| US9362937B1 (en) * | 2014-11-26 | 2016-06-07 | Stmicroelectronics S.R.L. | Method of calibrating a SAR A/D converter and SAR-A/D converter implementing said method |
-
2001
- 2001-04-04 CN CN 01110247 patent/CN1208901C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438340C (en) * | 2006-01-24 | 2008-11-26 | 华为技术有限公司 | Method for detecting AD converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1378344A (en) | 2002-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8477052B2 (en) | Method and apparatus for self-test of successive approximation register (SAR) A/D converter | |
| US7746262B2 (en) | Coding method for digital to analog converter of a SAR analog to digital converter | |
| CN1159587C (en) | Front-end architecture for measurement instrument | |
| CN1208901C (en) | Test method and circuit for successive approximation A/D conversion integrated circuit | |
| JPH08330959A (en) | Detection for fault of a-d input circuit | |
| CN113358997B (en) | MMC submodule IGBT open-circuit fault diagnosis method based on fault model | |
| CN106802293B (en) | Waveform peak detection method and device | |
| CN1244925A (en) | IC testing method and IC testing device using the same | |
| JP2003018007A (en) | Analog to digital signal conversion method | |
| CN1625841A (en) | Digital-to-analog converter with integrated test circuit | |
| US7439888B2 (en) | Method for digitally representing an integral non-linearity response for a device | |
| CN112910462B (en) | pipeline-SAR ADC digital interstage gain calibration method based on metastable state detection | |
| CN113960344A (en) | Method for detecting difference value of abrupt waveform | |
| CN112600561A (en) | Signal processing system in oscilloscope, oscilloscope and signal processing method | |
| CN1320532C (en) | Multiphase waveform generator capable of correcting phases, and method for correcting relevant phase | |
| CN109728816A (en) | A kind of ADC condition detecting system | |
| CN100336689C (en) | Off-line detecting method for ABS wheel speed sensor | |
| Huhn et al. | A Codeword-Based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Ntworks | |
| CN113433379B (en) | Ee voltage detection device and method for IGBT | |
| CN106712772A (en) | Successive approximation analog to digital converter testing method and circuit | |
| JP2001111423A (en) | Mechanism for integrating real time self-test failure detection method into a/d converter | |
| CN109510628A (en) | The recognition by pressing keys method of key circuit, matrix press-key circuit and matrix press-key circuit | |
| CN1967277A (en) | Integrated circuit test | |
| CN113364461B (en) | Analog-to-digital conversion calibration method and system for chip to be tested | |
| JP2003018006A (en) | Analog/digital conversion method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050629 Termination date: 20200404 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |