CN1208291A

CN1208291A - Protection equipment for data communication channel and service channel

Info

Publication number: CN1208291A
Application number: CN 98117324
Authority: CN
Inventors: 邹世敏
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 1998-08-17
Filing date: 1998-08-17
Publication date: 1999-02-17
Anticipated expiration: 2018-08-17
Also published as: CN1067823C

Abstract

The protection equipment includes one regulator circuit, which regulates the channel byte and service byte of digital communication in the overhead serial data terminated from line from the receiving terminal time sequence to the sending terminal time sequence, and one selector circuit, which is connected to the regulator circuit and selects one as output from the digital communication channel data and service data from the regulator circuit as well as local service unit and master unit. The equipment of the present invention is low in cost and easy to realize, and it can ensure normal DCC communication and service communication between network elements even in case of faulty local master unit or service unit.

Description

Data communication channel and service channel protection equipment

The invention belongs to the communications field, or rather, relate to data communication channel (hereinafter to be referred as DCC) and service channel protection equipment in a kind of SDH transmission system.

In the STM-1 frame structure of SDH, 81 overhead bytes are arranged, wherein totally 12 bytes are as data communication channel usefulness for D1～D12, and E1, E2 byte provide the communication of the public affair language between network element.By DCC, set up the bridge of data communication between network element, network management system can by DCC to each network element and subnet network element be configured, operation such as performance monitoring and alarming processing.In the general application, only use three bytes of D1～D3 can satisfy the communication requirement of DCC, be used between network element ac operation, administer and maintain (being OAM) information.These 81 overhead bytes after the unit, road terminate from circuit by the group of this locality, are reformulated an expense frame structure that repetition rate is 8KHZ, export with serial mode, and speed is 5.184Mbit/s.Group unit, road is with overhead data and corresponding clock and frame alignment signal is given main control unit and orderwire unit is handled, and main control unit takes out the DCC data according to the time location of D1, D2, D3, and handles or transmit by certain data scheme; Orderwire unit carries out this locality from the time location taking-up public affair data of E1, E2 equally and handles or transmit operation.

In the SDH transmission network,, stand to come and just can not send by the data that our station is transmitted, thereby cause DCC between network element to communicate by letter or the interruption of official traffic from the neighbour if the main control unit at a certain station or orderwire unit break down.Some producers are for fear of this situation, the problem that DCC communication or official traffic are interrupted when adopting main-standby mode to break down to solve main control unit or orderwire unit, but this method cost is too high.

Purpose of the present invention just provide a kind ofly overcome that above-mentioned shortcoming, cost are low, the simple data communication channel of circuit and service channel protection equipment.

The object of the present invention is achieved like this; Comprise and will be adjusted to the adjustment circuit of the timing sequential of making a start by the timing sequential of receiving end from the data communication channel byte the expense serial data that circuit terminates and public affair byte, and link to each other with described adjustment circuit, from respectively from selecting one tunnel selection circuit the data communication channel data of described adjustment circuit and local orderwire unit and main control unit and the public affair data as output.

Described adjustment circuit (103A) comprises producing respectively to be write enable signal and reads the write timing circuit (204) of enable signal and read timing circuit (205); Link to each other, store the first memory (201B) of writing enable signal with described write timing circuit (204); Link to each other with input, the output of described first memory (201B), select the first selector (202B) of one tunnel output; Storage is from the second memory (201A) of the overhead byte that terminates from circuit of unit, group road; Link to each other with input, the output of described second memory (201A), select the second selector (202A) of one tunnel output to link to each other with described first memory (201B), described second memory (201A) and the described timing circuit (205) of reading, writing the data communication channel byte and the public affair byte in the overhead byte that writes described second selector (202A) output under the enable signal control of writing of clock and described first selector (202B) output, reading clock and reading sense data communication port byte and public affair bytes of memory unit (203) under the enable signal control; Link to each other with described first selector (202B) and the described timing circuit (205) of reading, relatively give writing enable signal and reading the phase discriminator (206) of the phase place of enable signal of described memory cell (203); Link to each other with described phase discriminator (206), produce the reverse circuit (207) of described first selector (202B) and the required control signal of described second selector (202A).

Described first memory (201B) and described second memory (201A) are shift register.

Described first memory (201B) and described second memory (201A) are eight bit shift register.

Described memory cell (203) is a buffer.

Described phase discriminator (206) be one with the door.

Described reverse circuit (207) is a pulse-detecting circuit.

Described adjustment circuit comprises producing respectively to be write enable signal and reads the write timing circuit (204) of enable signal and read timing circuit (205); Link to each other with described write timing circuit (204), write data communication channel byte and public affair byte the expense serial data that terminate from circuit down in the enable signal control write of writing the output of clock and described write timing circuit (204), read clock and described read that timing circuit (205) exports read enable signal control under the fifo register (301) of sense data communication port byte and public affair byte; Link to each other, produce the control circuit (302) of described fifo register (301) reset signal with the EF port of described fifo register (301) and FF port.

Described control circuit (302) is that a signal is along detector.

The present invention is similar to the framing control circuit in working mechanism, but is the byte adjustment herein, and each adjustment only damages one or several byte (capacity on described first memory and described second memory is decided).Because DCC adopts the high-level data link rules to transmit data, if this damage falls into some DCC packets,, transmit this packet again because receiving end has CRC check and repeat requests mechanism, communication efficiency is not had any influence.This damage is almost imperceptible to the influence of public affair language communication.

Therefore, the present invention has realized the protection to DCC communication and official traffic under the situation that does not adopt main-standby mode, economizes on resources, thereby greatly reduces cost; Implementation of the present invention in addition is simple and clear, is convenient to the design and the realization of circuit.

Describe embodiments of the invention in detail referring now to accompanying drawing, description of drawings is as follows:

Fig. 1 is the structured flowchart of data communication channel of the present invention and service channel protection apparatus embodiments;

Fig. 2 is a kind of circuit diagram of adjusting circuit 101A shown in Fig. 1;

Fig. 3 is an another kind of circuit diagram of adjusting circuit 101A shown in Fig. 1;

The writing enable signal WEN2, read the oscillogram of reading enable signal REN and phase discriminator 206 and reverse circuit 207 outputs of timing circuit output of first selector 202B output among Fig. 2 when the read-write operation that Fig. 4 A-Fig. 4 D is respectively buffer shown in Fig. 2 203 does not clash;

When the read-write operation that Fig. 5 A-Fig. 5 E is respectively buffer shown in Fig. 2 203 clashes among Fig. 2 first selector 202B output write enable signal WEN2, read timing circuit output read enable signal REN, the adjusted oscillogram of writing enable signal WEN2 and phase discriminator 206 and reverse circuit 207 outputs.

As shown in Figure 1, SDH equipment comprises that under add-drop multiplexer ADM mode two symmetrical fully group unit, road are to handle the data of both direction, for the purpose of difference, being referred to as unit, device cluster road 101 and unit, dual group road 102 respectively, below is that example is described present embodiment with the data processing of a direction.Data communication channel of the present invention and service channel protection equipment 103 are the part (other partial circuits of group unit, road 101,102 are not shown) in the group unit, road, comprise the selection circuit 103B that adjusts circuit 103A and be attached thereto.Overhead data that unit, device cluster road terminates from circuit and corresponding write clock signal WCK and write frame alignment signal and give main control unit and orderwire unit 104, main control unit and orderwire unit 104 take out DCC data and public affair data respectively and carry out that handle this locality or forwarding; Overhead data and corresponding clock WCK and frame alignment signal also are fed to the adjustment circuit 103A in the unit, dual group road 102 simultaneously, adjust circuit 103A DCC data and the public affair data of unit 101, device cluster road from the expense serial data that circuit terminates are adjusted to the timing sequential of making a start by the timing sequential of receiving end, DCC data and public affair data that the DCC data of its output and public affair data and main control unit and orderwire unit 102 need to send are given selection circuit 102B simultaneously, when main control unit and orderwire unit 102 operate as normal, selected cell is exported DCC data and the public affair data from main control unit and orderwire unit 102, otherwise then exports DCC data and the public affair data of self-adjusting circuit 101A.

Fig. 2 illustrates the circuit block diagram of adjusting a circuit 103A implementation shown in Fig. 1.As shown in the figure, overhead data Da gives the second shift register 201A and the second selector 202A of 8 bits simultaneously, another input of second selector 202A links to each other with the output of the second shift register 201A, under the output signal SEL of reverse circuit 207 control, second selector 202A selects one tunnel output to give buffer 203; Write timing circuit 204 is at write clock signal WCK and write to produce under the control of frame alignment signal WFR and write the first shift register 201B that enable signal WEN1 gives 8 bits, first selector 202B links to each other with input, the output of the first shift register 201B, under the output signal SEL of reverse circuit 207 control, select with corresponding one tunnel output of the output of second selector as buffer write enable signal WEN2, promptly first, second selector selects the input of first, second shift register or output end signal as output simultaneously; Write clock signal is also given buffer 203, and under the control of writing enable signal WEN2 of first selector 202B output, D1～D3 byte and E1, E2 byte during the overhead data Da-of second selector 202A output goes into are written into buffer 203; Read timing circuit 205 at read clock signal RCK that local node produces with read to produce under the control of frame alignment signal RFR and read enable signal REN, buffer 203 is at read clock signal RCK and read to read successively under the control of enable signal REN data in the buffer 203.Phase discriminator 206 be one with the door, input is for writing enable signal WEN2 and reading enable signal REN, if the read-write operation to buffer 203 is normal, phase discriminator 206 is output as " 0 ", the output SEL of reverse circuit 207 is " 0 " (referring to Fig. 4), and two selectors still select original a road to export as it; As read and write conflict taken place, read enable signal REN and write enable signal WEN2 phase place have overlapping, phase discriminator 206 outputs one positive pulse.Reverse circuit 207 is a pulse-detecting circuit, is turned to one state (participation Fig. 5) immediately when detecting the positive pulse of phase discriminator 206 output, and two selectors of this signal controlling select another road input signal to export as it.

Fig. 3 illustrates the circuit diagram of adjusting the another kind of implementation of circuit 101A shown in Fig. 1.As shown in Figure 3, the write timing circuit with read timing circuit all with Fig. 2 in the write timing circuit and to read timing circuit identical, but other circuit among Fig. 2 are replaced by fifo register 301 and control circuit 302.The enable signal WEN that writes that the write timing circuit produces directly gives fifo register 301, and the same with adjustment circuit among Fig. 2, DCC byte and public affair byte among the overhead data Da are written into fifo register 301; Similarly, at read clock signal RCK and reading under the control of enable signal REN, data Da-goes out from the other end of fifo register 301 to read.Fifo register 301 has two pins difference output registers " to expire " signal FF and register " sky " signal EF, these two signals are given control circuit 302, control circuit 302 is that a signal is along detector, when detecting signal EF or FF generation saltus step, export a reset pulse RES fifo register 301 is resetted again, the read-write operation of fifo register is restarted.

Claims

1. data communication channel and service channel protection equipment; it is characterized in that: comprise that data communication channel byte the expense serial data that will terminate from circuit and public affair byte are adjusted to the adjustment circuit (103A) of the timing sequential of making a start by the timing sequential of receiving end, and link to each other with described adjustment circuit (103A), from respectively from selecting one tunnel selection circuit (103B) the data communication channel data of described adjustment circuit (103A) and local orderwire unit and main control unit and the public affair data as output.

2. data communication channel as claimed in claim 1 and service channel protection equipment is characterized in that: described adjustment circuit (103A) comprises producing respectively to be write enable signal and the write timing circuit (204) of reading enable signal and reads timing circuit (205) and link to each other, store the first memory (201B) of writing enable signal with described write timing circuit (204); Link to each other with input, the output of described first memory (201B), select the first selector (202B) of one tunnel output; Storage is from the second memory (201A) of the overhead byte that terminates from circuit of unit, group road; Link to each other with input, the output of described second memory (201A), select the second selector (202A) of one tunnel output; Link to each other with described first memory (201B), described second memory (201A) and the described timing circuit (205) of reading, writing the data communication channel byte and the public affair byte in the overhead byte that writes described second selector (202A) output under the enable signal control of writing of clock and described first selector (202B) output, reading clock and reading sense data communication port byte and public affair bytes of memory unit (203) under the enable signal control; Link to each other with described first selector (202B) and the described timing circuit (205) of reading, relatively give writing enable signal and reading the phase discriminator (206) of the phase place of enable signal of described memory cell (203); Link to each other with described phase discriminator (206), produce the reverse circuit (207) of described first selector (202B) and the required control signal of described second selector (202A).

3. data communication channel as claimed in claim 2 and service channel protection equipment, it is characterized in that: described first memory (201B) and described second memory (201A) are shift register.

4. data communication channel as claimed in claim 3 and service channel protection equipment, it is characterized in that: described first memory (201B) and described second memory (201A) are eight bit shift register.

5. data communication channel as claimed in claim 2 and service channel protection equipment, it is characterized in that: described memory cell (203) is a buffer.

6. data communication channel as claimed in claim 2 and service channel protection equipment is characterized in that: described phase discriminator (206) be one with door.

7. data communication channel as claimed in claim 2 and service channel protection equipment, it is characterized in that: described reverse circuit (207) is a pulse-detecting circuit.

8. data communication channel as claimed in claim 1 and service channel protection equipment is characterized in that: described adjustment circuit comprises producing respectively to be write enable signal and reads the write timing circuit (204) of enable signal and read timing circuit (205); Link to each other with described write timing circuit (204), write data communication channel byte and public affair byte the expense serial data that terminate from circuit down in the enable signal control write of writing the output of clock and described write timing circuit (204), read clock and described read that timing circuit (205) exports read enable signal control under the fifo register (301) of sense data communication port byte and public affair byte; Link to each other, produce the control circuit (302) of described fifo register (301) reset signal with the EF port of described fifo register (301) and FF port.

9. data communication channel as claimed in claim 8 and service channel protection equipment, it is characterized in that: described control circuit (302) is that a signal is along detector.