CN1208291A - Protection equipment for data communication channel and service channel - Google Patents

Abstract

A data communication channel byte and service channel protection device, including an adjustment circuit for adjusting the data communication channel byte and service byte in the overhead serial data terminated from the line from the timing sequence of the receiving end to the timing sequence of the sending end , and a selection circuit that is connected with the adjustment circuit and selects one as an output from the data communication channel data and the business data respectively from the adjustment circuit, the local business unit and the main control unit. The invention has low equipment cost and is easy to realize, and can ensure normal DCC communication and business communication between network elements when a local main control unit or a business unit fails.

Description

Data communication channel and business channel protection equipment

The invention belongs to the communication field, and more precisely relates to a data communication channel (hereinafter referred to as DCC) and a service channel protection device in an SDH transmission system.

In the STM-1 frame structure of SDH, there are 81 overhead bytes, of which 12 bytes D1~D12 are used as data communication channels, and E1 and E2 bytes provide official voice communication between network elements. Through DCC, a data communication bridge is established between network elements, and the network management system can perform operations such as configuration, performance monitoring, and alarm handling on each network element and subnet network element through DCC. In general applications, only three bytes D1-D3 are used to meet the communication requirements of the DCC, and are used to exchange operation, management and maintenance (that is, OAM) information between network elements. After the 81 overhead bytes are terminated from the line by the local group circuit unit, an overhead frame structure with a repetition frequency of 8KHZ is reconstituted and output in serial mode at a rate of 5.184Mbit/s. The group unit sends the overhead data and the corresponding clock and frame positioning signals to the main control unit and the business unit for processing, and the main control unit takes out the DCC data according to the time positions of D1, D2, and D3, and processes or forwards them according to certain data regulations ; The business units also take out business data from the time positions of E1 and E2 for local processing or forwarding operations.

In the SDH transmission network, if the main control unit or service unit of a certain station fails, the data that needs to be forwarded by the station from neighboring stations cannot be sent out, resulting in the interruption of DCC communication or service communication between network elements. In order to avoid this situation, some manufacturers adopt the main backup mode to solve the problem of DCC communication or business communication interruption when the main control unit or business unit fails, but this method is too expensive.

The object of the present invention is to provide a data communication channel and service channel protection device which overcomes the above-mentioned shortcomings, has low cost and simple circuit.

The purpose of the present invention is achieved in this way; including an adjustment circuit that adjusts the data communication channel byte and the official byte in the overhead serial data terminated from the line from the timing sequence of the receiving end to the timing sequence of the sending end, and is compatible with the A selection circuit that is connected to the adjustment circuit and selects one of the data communication channel data and official data from the adjustment circuit, the local business unit and the main control unit as an output.

The adjustment circuit (103A) includes a write timing circuit (204) and a read timing circuit (205) that generate a write enable signal and a read enable signal respectively; it is connected to the write timing circuit (204) and stores the write enable signal The first memory (201B) of the first memory (201B); is connected to the input and output terminals of the first memory (201B), and selects the first selector (202B) of one output; stores the overhead word from the line termination from the group road unit The second memory (201A) of section; Be connected with the input of described second memory (201A), the output terminal, select the second selector (202A) of one output and described first memory (201B), described second The memory (201A) is connected to the read timing circuit (205), and the overhead output by the second selector (202A) is written under the control of the write clock and the write enable signal output by the first selector (202B) In the byte, the data communication channel byte and the official byte, read the storage unit (203) of the data communication channel byte and the official byte under the control of the read clock and the read enable signal; and the first selector (202B) Connected with the read timing circuit (205), compare the phase detector (206) of the phase of the write enable signal and the read enable signal sent to the storage unit (203); and the phase detector (206) connected to generate an inversion circuit (207) for the control signals required by the first selector (202B) and the second selector (202A).

The first memory (201B) and the second memory (201A) are shift registers.

The first memory (201B) and the second memory (201A) are 8-bit shift registers.

The storage unit (203) is a buffer.

The phase detector (206) is an AND gate.

The flipping circuit (207) is a pulse detection circuit.

The adjustment circuit includes a write timing circuit (204) and a read timing circuit (205) that respectively generate a write enable signal and a read enable signal; Under the control of the write enable signal output by the circuit (204), the data communication channel byte and the official byte in the overhead serial data terminated from the line are written, and the read clock output by the read clock and the read timing circuit (205) The FIFO register (301) of reading data communication channel byte and business byte under the control of enable signal; be connected with the EF port and FF port of described FIFO register (301), produce described FIFO register (301) reset signal Control circuit (302).

The control circuit (302) is a signal edge detector.

The working mechanism of the present invention is similar to the frame adjustment circuit, but here it is byte adjustment, and each adjustment only damages one or several bytes (depending on the capacity of the first memory and the second memory). Because DCC uses advanced data link procedures to transmit data, if this damage falls into a certain DCC data packet, since the receiving end has a CRC check and retransmission request mechanism, retransmitting this data packet will not affect communication efficiency. what effect. The impact of this impairment on official voice communications is almost imperceptible.

Therefore, the present invention realizes the protection of DCC communication and official communication without adopting the main standby mode and saving resources, thus greatly reducing the cost; in addition, the realization mode of the present invention is simple and convenient for circuit design and realization.

Embodiments of the present invention are now described in detail with reference to the accompanying drawings, which are as follows:

Fig. 1 is a structural block diagram of an embodiment of a data communication channel and an official channel protection device of the present invention;

FIG. 2 is a circuit diagram of the adjustment circuit 101A shown in FIG. 1;

FIG. 3 is another circuit diagram of the adjustment circuit 101A shown in FIG. 1;

4A-FIG. 4D respectively show the write enable signal WEN2 output by the first selector 202B in FIG. 2, the read enable signal REN output by the read timing circuit and The waveform diagram of phase detector 206 and flipping circuit 207 output terminals;

5A-FIG. 5E respectively show the write enable signal WEN2 output by the first selector 202B in FIG. 2, the read enable signal REN output by the read timing circuit, and the adjustment The waveform diagram of the final write enable signal WEN2 and the output terminals of the phase detector 206 and the flipping circuit 207 .

As shown in Figure 1, the SDH equipment includes two completely symmetrical group units in the ADM mode of the add-drop multiplexer to process data in two directions. For the sake of distinction, they are called the equipment group unit 101 and the dual group The road unit 102, the following describes this embodiment by taking data processing in one direction as an example. The data communication channel and service channel protection device 103 of the present invention is a part of the group circuit unit (other circuits of the group circuit unit 101 and 102 are not shown), including an adjustment circuit 103A and a selection circuit 103B connected thereto. The overhead data and the corresponding write clock signal WCK and write frame positioning signal terminated by the equipment group circuit unit are sent to the main control unit and the business unit 104, and the main control unit and the business unit 104 respectively take out the DCC data and business data for local processing. Processing or forwarding; at the same time, the overhead data and the corresponding clock WCK and frame alignment signal are also sent to the adjustment circuit 103A in the dual group circuit unit 102, and the adjustment circuit 103A terminates the overhead serial data from the equipment group circuit unit 101 on the line The DCC data and official data in the receiver are adjusted from the timing sequence of the receiving end to the timing sequence of the sending end, and the DCC data and official data output by it, as well as the DCC data and official data that the main control unit and the official unit 102 need to send are sent to the selection circuit 102B at the same time, When the main control unit and the business unit 102 work normally, the selection unit outputs the DCC data and business data from the main control unit and the business unit 102 , otherwise it outputs the DCC data and business data from the adjustment circuit 101A.

FIG. 2 shows a circuit block diagram of an implementation scheme of the adjustment circuit 103A shown in FIG. 1 . As shown in the figure, the overhead data Da is sent to the 8-bit second shift register 201A and the second selector 202A at the same time, and the other input end of the second selector 202A is connected to the output end of the second shift register 201A. Under the control of the output signal SEL of the flip circuit 207, the second selector 202A selects one output and sends it to the buffer 203; the write timing circuit 204 generates the write enable signal WEN1 under the control of the write clock signal WCK and the write frame alignment signal WFR and sends it to the The 8-bit first shift register 201B, the first selector 202B is connected to the input and output terminals of the first shift register 201B, and under the control of the output signal SEL of the flipping circuit 207, the output corresponding to the output of the second selector is selected. Output as the write enable signal WEN2 of the buffer, that is, the first and second selectors simultaneously select the input or output signal of the first and second shift registers as output; the write clock signal is also sent to the buffer 203, in Under the control of the write enable signal WEN2 output by the first selector 202B, the D1-D3 bytes and E1, E2 bytes of the overhead data Da-in output by the second selector 202A are written into the buffer memory 203; The circuit 205 generates the read enable signal REN under the control of the read clock signal RCK and the read frame alignment signal RFR generated by the local node, and the buffer 203 sequentially reads the data in the buffer 203 under the control of the read clock signal RCK and the read enable signal REN. The data. The phase detector 206 is an AND gate, and the input terminals are the write enable signal WEN2 and the read enable signal REN. If the read and write operations to the buffer 203 are normal, the output of the phase detector 206 is "0", and the output of the flipping circuit 207 SEL is "0" (referring to Fig. 4), and two selectors still select the original all the way as its output; As conflict occurs in reading and writing, read enable signal REN and write enable signal WEN2 phase overlap, phase detector 206 Output a positive pulse. The inverting circuit 207 is a pulse detection circuit, which immediately inverts to a "1" state when detecting the positive pulse output by the phase detector 206 (refer to FIG. 5 ), and this signal controls two selectors to select another input signal as its output.

FIG. 3 shows a circuit diagram of another implementation of the adjustment circuit 101A shown in FIG. 1 . As shown in FIG. 3 , both the write timing circuit and the read timing circuit are the same as those in FIG. 2 , but other circuits in FIG. 2 are replaced by FIFO register 301 and control circuit 302 . The write enable signal WEN generated by the write timing circuit is directly sent to the FIFO register 301, the same as the adjustment circuit in Fig. 2, the DCC byte and the official byte in the overhead data Da are written into the FIFO register 301; similarly, at the read clock Under the control of the signal RCK and the read enable signal REN, the data Da-out is read from the other end of the FIFO register 301 . The FIFO register 301 has two pins that respectively output the register "full" signal FF and the register "empty" signal EF. These two signals are sent to the control circuit 302. The control circuit 302 is a signal edge detector. When FF jumps, a reset pulse RES is output to reset the FIFO register 301, and the read and write operations on the FIFO register are restarted.

Claims (9)

1. A data communication channel and a service channel protection device, characterized in that: it includes adjusting the data communication channel byte and the service byte in the overhead serial data terminated from the line from the timing sequence of the receiving end to the timing of the sending end The timing adjustment circuit (103A), and being connected to the adjustment circuit (103A), selects one path as an output from the data communication channel data and the official data from the adjustment circuit (103A) and the local business unit and the main control unit respectively The selection circuit (103B). 2. The data communication channel and official channel protection equipment as claimed in claim 1, characterized in that: the adjustment circuit (103A) includes a write timing circuit (204) and a read timing circuit (204) that generate a write enable signal and a read enable signal respectively. The timing circuit (205) is connected with the write timing circuit (204) and stores the first memory (201B) of the write enable signal; it is connected with the input and output terminals of the first memory (201B), and selects the first memory (201B) for one output. A selector (202B); a second memory (201A) storing the overhead bytes terminated from the line from the group unit; connected to the input and output of the second memory (201A), and selecting one output The second selector (202A); is connected with the first memory (201B), the second memory (201A) and the read timing circuit (205), and the write clock and the first selector (202B) Under the control of the output write enable signal, write the data communication channel byte and the official byte in the overhead byte output by the second selector (202A), and read the data communication channel word under the control of the read clock and the read enable signal The storage unit (203) of section and business byte; Link to each other with described first selector (202B) and described read timing circuit (205), compare and send the write enable signal and read of described storage unit (203) The phase detector (206) of the phase of enabling signal; Connect with described phase detector (206), produce the inversion of the required control signal of described first selector (202B) and described second selector (202A) circuit (207). 3. The data communication channel and business channel protection device according to claim 2, characterized in that: the first memory (201B) and the second memory (201A) are shift registers. 4. The data communication channel and business channel protection device according to claim 3, characterized in that: the first memory (201B) and the second memory (201A) are 8-bit shift registers. 5. The data communication channel and service channel protection device according to claim 2, characterized in that: the storage unit (203) is a buffer. 6. The data communication channel and service channel protection device according to claim 2, characterized in that: the phase detector (206) is an AND gate. 7. The data communication channel and business channel protection device according to claim 2, characterized in that: the flipping circuit (207) is a pulse detection circuit. 8. data communication channel as claimed in claim 1 and official service channel protection equipment, it is characterized in that: described adjusting circuit comprises the write timing circuit (204) that produces write enable signal and read enable signal respectively and read timing circuit ( 205); connected to the write timing circuit (204), under the control of the write clock and the write enable signal output by the write timing circuit (204), write the data communication in the overhead serial data terminated from the line Passage byte and official duty byte, read the FIFO register (301) of data communication channel byte and official duty byte under the control of read enable signal output of read clock and described read timing circuit (205); The EF port of (301) is connected to the FF port, and the control circuit (302) that generates the reset signal of the FIFO register (301) is generated. 9. The data communication channel and service channel protection device according to claim 8, characterized in that: the control circuit (302) is a signal edge detector.

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