CN1206879A

CN1206879A - Interconnection bridge for external parts

Info

Publication number: CN1206879A
Application number: CN 98108323
Authority: CN
Inventors: 金宣吾
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1997-07-25
Filing date: 1998-05-21
Publication date: 1999-02-03

Abstract

A peripheral component interconnect (PCI) bridge which interfaces between PCI and local buses to provide a communicator for performing a communication between peripheral devices connected to the PCI bus and system devices connected to the local bus, is provided. The PCI bridge comprising a PCI register which is initialized according to a reset signal from the PCI bus and then stores configuration information on the PCI bus, a local register which is initialized according to a reset signal from the PCI bus and then stores configuration information on the local bus, PCI bus interface logic for performing interfacing according to the configuration information stored in the PCI register, local bus interface logic for performing interfacing according to the configuration information stored in the local register, and a logic transformer for reconstructing the PCI bus interface logic according to a command input from a user.

Description

Interconnection bridge for external parts

The present invention relates to be used for PCI (peripheral parts interconnected) bridge of interface pci bus and local bus, particularly relate to a kind of can the adaptation such as utilizing the reconstruction interface logic to change the PCI bridge of pci bus typical problem.

Usually, information handling system includes more than one bus and the equipment that is connected to each bus and is used for carrying out communicating by letter such as data transmission by bus.For example, a typical computer comprises a local bus, and this local bus is connected to central processing unit (CPU), and this CPU communicates by letter with the miscellaneous equipment that is connected to this local bus by this local bus.Simultaneously, a such system also can comprise one or more peripheral buses, for example a peripheral component interconnect (pci) bus.For example the peripherals of input-output apparatus etc. is connected with peripheral bus.

Yet local bus and peripheral bus have used different standards when carrying out data transmission between the equipment that is connected to these buses and distinct device.And each bus is come out according to different standards is manufactured.Being used for interface uses the equipment of the bus of various criterion to be called bridge (bridge).Bridge in particular for interface local bus and pci bus is called the PCI bridge.

Fig. 1 shows a brief block diagram that comprises the computer system of PCI bridge.Referring to Fig. 1, central processing unit (CPU) 101, storer 102 and local peripherals 103 are connected to local bus 100, and local bus 100 is connected with various miscellaneous equipment (not shown).PCI peripherals 111 is connected with pci bus 110.Local bus 100 is connected by PCI bridge 120 with pci bus 110.In this system, PCI bridge 120 interface local bus 100 and pci bus 110.That is to say, between two buses, transmit in the process of data, address and control signal that PCI bridge 120 has overcome the inconsistency between two bus standards.

Fig. 2 shows the block diagram of conventional PCI bridge 200.Conventional PCI bridge 200 comprises PCI and local register 210 and 220.When the PCI bridge was initialised according to the reset signal from pci bus, they stored the structural information on pci bus and the local bus respectively.And, this routine PCI bridge 200 also comprises pci bus interface logic 230, it reads the structural information and the output that are stored on the PCI register 210 according to pci bus cycle and specifies as the address, the request command of read command or write order, and comprising local bus interface logic 240, it reads the information that is stored on the local register 220 according to pci bus cycle and according to the request command executive's interface from pci bus interface logic 230.In having the conventional PCI bridge 200 of this parts, be stored in EEPROM (ROM (read-only memory) of the electric erasable and programmable program) (not shown) of the serial that is connected with PCI bridge 200 with local register 210 and the structural information in 220 being stored in PCI, and this structural information is written in PCI and

local register

210 and 220 according to the reset signal from pci bus 110.Aforesaid processing, wherein PCI bridge 200 reads from the structural information of serial EEPROM and the process that writes identical information in PCI and

local register

210 and 220 and is called as initialization.

The initialization of PCI bridge 200 will be with reference to explanation among the figure 3.

When energized, in the reset signal of step 300 reception from pci bus 110.Next, read structural information, then, PCI and

local bus

110 and 100 are set in step 320 from serial EEPROM at this PCI of step 310 and local register 210 and 220.After initialization was finished, PCI bridge 200 was according to the command cycle executive's interface from pci bus 110.

Conventional PCI bridge 200 is made of the logical circuit that only contains register, so, the standard of all PCI must be supported on design and the conventional PCI abutment plinth that produces on.But the PCI standard of manufacturing company is also inconsistent, but also is continuing upgrading.This upgrading will reduce compatibility, and still owing to the characteristic of technical development between the version, this is impossible usually.Therefore, bridge must continue upgrading, and the user must avoid using specific function, perhaps must change the BIOS (basic input/output) of application system.

The object of the present invention is to provide one can conversion pci bus interface logic so that adapt to the PCI bridge of the defective of the variation of pci bus standard and pci bus design easily.

For achieving the above object, the peripheral component interconnect (pci) bridge of an interface between PCI and local bus is provided, so that provide one to be used to carry out the peripherals that is connected to pci bus and to be connected to the communicator (communicator) that communicates between the system equipment of local bus, this PCI bridge comprises: a PCI register, and this PCI register root is initialised according to the reset signal from pci bus and structural information on the pci bus is stored; A local register, this this locality register root is initialised according to the reset signal from pci bus and structural information on the local bus is stored; According to the pci bus interface logic that is stored in the structural information executive's interface in the PCI register; According to the local bus interface logic that is stored in the structural information executive's interface in the local register; A logic converter, this logic converter is rebuild the pci bus interface logic according to the order of user's input.

In conjunction with the accompanying drawings to the detailed description of most preferred embodiment, it is more obvious that above-mentioned purpose of the present invention and advantage will become by following, wherein:

The block diagram of Fig. 1 shows the information handling system with PCI bridge;

The block diagram of Fig. 2 shows the structure of a conventional PCI bridge;

The flow process of Fig. 3 has been described a processing that is used for the conventional PCI bridge of initialization;

The block diagram of Fig. 4 shows the structure of PCI bridge of the present invention;

The block diagram of Fig. 5 shows the structure of logic converter shown in Figure 4; With

The flow process of Fig. 6 has been described the process of initialization PCI bridge shown in Figure 4.

Fig. 4 shows that PCI bridge 400 of the present invention comprises PCI register 410, local register 420, pci bus interface logic 430, local bus interface logic 440 and logic converter 450.

PCI register 410 is initialised according to the reset signal from pci bus, and the structural information of pci bus is stored.Local register 420 is initialised according to the reset signal from pci bus, and structural information on the local bus is stored.PCI and local bus interface logic 430 and 440 are respectively according to the structural information executive's interface that is stored on PCI and local register 410 and 420.Logic converter 450 is rebuild the pci bus interface logic according to user's order.

PCI bridge 400 with such structure is initialised, then with the PCI on Fig. 1 and

local bus

110 and 100 interfaces.Here, initialization means that the structural information of PCI and local bus is stored in respectively on PCI and local register 410 and 420.

When PCI bridge 400 was initialised, PCI register 410 stored the structural information of pci bus, and local register 420 stores the structural information of local bus, for example timing of local bus, highway width, waiting status etc.The pci bus interface logic 430 that is made of on described structural information basis each state logic circuit, is used for and will be sent to local bus interface logic 440 such as signals such as address or data as slave unit with respect to pci bus 110 or PCI external unit 111.The local bus interface logic 440 that has received such signal with respect to local bus 100 or the external unit 101,102 and 103 that is connected to local bus 100 as main device, and executive's interface.Simultaneously, when pressing the reverse direction executive's interface of above-mentioned interface direction, PCI and local bus interface logic 430 and 440 are carried out reverse operatings.

In the process of PCI bridge executive's interface, when the pci bus standard was upgraded or produces foozle, the state logic circuit of the pci bus interface logic 430 of executive's interface operation was rebuild by logic converter 450.

The sketch of Fig. 5 shows the inner structure of logic converter 450.Logic converter 450 according to Fig. 5 comprises the order reader 500 that is used for the access input command; Be used for access command is transformed to the code translator 510 of the code of explaining (interpreted); The state recording device 520 that is used for the output state signalization; This state signalization is used for rebuilding according to the code of being explained the state logic circuit of pci bus interface logic 430 inside.

The reconstruction of the state logic circuit of pci bus interface logic 430 inside of finishing by logic converter 450 is carried out in initialization procedure, and it is shown in the process flow diagram of Fig. 6.According to Fig. 6, when power supply is switched on, export reset signals to PCI bridge 400 in this pci bus 110 of step 600.After receiving reset signal from the reseting signal line of pci bus 110, PCI bridge 400 carries out initialization.According to this initialization, PCI bridge 400 checks in step 610 whether the user has imported order.If the user is input command not, for example under the state of command channel, PCI register 410 reads and stores on the pci bus standard from the structural information as the series connection EEPROM (ROM (read-only memory) of electric erasable and programmable program) of external memory storage in step 630.And in step 630, local register 420 reads and is stored on the local bus structural information from serial EEPROM.So PCI and

local bus

110 and 100 are set in step 640.Yet when step 610 was determined order from the user, PCI bridge 400 read input command and writes identical order so that rebuild pci bus interface logic 430 on pci bus interface logic 430 in step 620.Such reconstruction is finished by logic converter 450.That is to say that when order was imported into logic converter 450, it was by 500 accesses of order reader, decoded then device 510 converts the code of having deciphered to.Export a state signalization to pci bus interface logic 430 from the code of code translator 510 outputs by means of state recording device 520, in pci bus interface logic 430, rebuild state logic circuit whereby.After the reason, PCI register 410 reads and stores the structural information from series connection EEPROM on the pci bus standard herein.In step 630, local register 420 reads and stores the structural information from series connection EEPROM on local bus, and sets PCI and

local bus

110 and 100 in step 640.Then, if signal is imported from pci bus, then utilize the new logic that changes to carry out described interface operation.

The user has stored predetermined command in being connected to the series connection EEPROM of PCI bridge 400 after, stored order can be by logic converter 450 accesses.

Now, do a comparison to using according to PCI bridge of the present invention with to the access that the PLX9050 that uses as the PLX technology company of conventional P CI bridge carries out to expansion ROM (accord with PCI standard).Here, expansion ROM is the storer that is used to store not the program of being supported by BIOS ROM.

According to the PCI standard, pci bus 110 set in the expansion ROM register section of the PCI register by particular data being written to PCI bridge 120.No matter when expansion ROM is by access, and whether pci bus 110 all reads particular data from the PCI register and be set so that check this expansion ROM.At this moment, if PCI bridge 120 on expansion ROM region allocation to 256 byte, then predetermined value is read from pci bus 110.When pci bus 110 confirmed that described expansion ROM is set, a least significant bit (LSB) value that is set was written to the PCI register once more so that activate described expansion ROM.

Yet because PLX 9050 is arranged to address decoding activation position with the least significant bit (LSB) of expansion ROM register, if least significant bit (LSB) is not to be configured to 1, it just can not be operated.Therefore, if pci bus 110 is set to the expansion ROM zone of PCI register among the PLX 9050 according to the PCI standard, because least significant bit (LSB) is not to be configured to 1, so PLX 9050 inoperation.In this case, read and be used to confirm data that whether expansion ROM is set up to become one to have least significant bit (LSB) be 0 value by pci bus 110, so that pci bus 110 determines that PLX9050 do not have expansion ROM.Therefore, the function that is connected to the expansion ROM of PLX9050 can not be utilized.

Yet if the bridge of PCI of the present invention 400 is used, the user can use logic converter 450 input commands and change interface logic.Therefore, the problems referred to above can be solved.

In conjunction with the specific embodiment shown in the figure, the present invention is set forth, but specific embodiment is an example.Obviously, a plurality of modifieds and other equivalent embodiment can be made on basis of the present invention by those skilled in the art, and therefore, actual techniques protection domain of the present invention must be determined by claim of the present invention.

Therefore as mentioned above, the present invention can change state logic circuit by fill order, and is easy to adapt to the variation of pci bus standard or adapts to pci bus without any the manufacturing mistake under the correction situation of BIOS system.

Claims

1. the peripheral parts interconnected PCI bridge of interface between PCI and local bus is used at the external unit that is connected to pci bus and is connected between the system equipment of local bus a communicator that communicates is provided, and this PCI bridge comprises:

A PCI register is initialised and then the structural information of described pci bus is stored according to this PCI register of reset signal from described pci bus;

A local register is according to should this locality register from the reset signal of described pci bus being initialised and then structural information on the described local bus being stored;

The pci bus interface logic is according to the structural information executive's interface that is stored in described PCI register;

The local bus interface logic is according to the structural information executive's interface that is stored in described local register; With

A logic converter is used for according to rebuilding described pci bus interface logic from user's input command.

2. PCI bridge according to claim 1, wherein, described pci bus interface logic is included in the state logic circuit of both direction executive's interface operation.

3. PCI bridge according to claim 2, wherein, described logic converter is handled from described user's order and by producing a state signalization according to each described state logic circuit in the described pci bus interface logic and is rebuild described state logic circuit.

4. PCI bridge according to claim 3, wherein, described logic converter comprises:

An order reader is used for the order of access user input;

A code translator is used for the code that the data decoding from described order reader output is become to have deciphered;

A state recording device is exported described state signalization according to the code of having deciphered of described code translator output.

5. PCI bridge according to claim 1, wherein, described logic converter uses and rebuilds described pci bus interface logic from the order of external memory storage.

6. PCI bridge according to claim 5, wherein, described external memory storage is the EEPROM of a serial.