CN1205656C - Dielectric structure between metal layers - Google Patents
Dielectric structure between metal layers Download PDFInfo
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- CN1205656C CN1205656C CN 02127646 CN02127646A CN1205656C CN 1205656 C CN1205656 C CN 1205656C CN 02127646 CN02127646 CN 02127646 CN 02127646 A CN02127646 A CN 02127646A CN 1205656 C CN1205656 C CN 1205656C
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- metal layers
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Abstract
The present invention relates to a dielectric structure between metal layers, which is formed on the surface of a semiconductor substrate. The surface of the semiconductor substrate comprises a plurality of metal layers, a dielectric layer between the metal layers, a metal covering layer which covers the surface of the semiconductor substrate to preset height and an oxide covering layer having high compensation stress for covering the surface of the dielectric layer between the metal layers, wherein the total of the compression stress of the dielectric layer between the metal layers and the oxide covering layer needs being close to the tension stress of the metal layers so as to prevent the problem that the difference of the stress of the metal layers and the stress of the dielectric layer is oversize, which causes cracking phenomena. The oxide covering layer is formed by a high density pulp-source radio frequency (HDP-SRF) method, which can greatly enhance the compression stress of the oxide covering layer so as to solve common cracking defects and bubble problems. In addition, the inner part of the oxide covering layer can have more dangling bonds which are sufficient for trapping diffused fluorine ions.
Description
Technical field
The invention relates to a kind of oxide cap of dielectric structure between metal layers, be particularly to a kind of oxide cap of the chemical gaseous phase depositing process made with high-density electric slurry-source radio frequency (HDP-SRF), the stretching stress that can solve metal level is excessive and cause oxide cap to produce the problem of rift defect.
Technical background
In ultra-large type integrated circuit ultra-large-scale Integration (ULSI) processing procedure, multi-metal intra-connection structure is that many plain conductors are made in the different layers, is used for the circuit performance of lift elements and the functional complexity of circuit.In early days at metal interlevel dielectric medium (inter-metaldielectric, IMD) development, concentrate on the improvement of problems such as clearance filled and planarization, and along with high density plasma enhanced chemical vapor deposition (high density plasma CVD, HDPCVD) all kinds of method of improvement and cmp (CMP) is suggested, the problems referred to above are overcome gradually, and therefore current development focuses on the dielectric coefficient that how to reduce the IMD layer, to promote the integral operation speed of circuit.
Greater than for the semiconductor element of 0.4 μ m, the RC time delay of circuit is determined that by FEOL it includes driving electric capacity and the load resistance (load resistance) of CMOS for size.But along with component size is contracted to below the 0.35 μ m, the RC time delay of FEOL can reduce thereupon, and the RC time delay that the back segment processing procedure is caused can increase thereupon.In order to improve this problem, a kind of mode is to replace the resistance value that traditional aluminum steel reduces metal level with copper cash, and another kind of mode is to use the dielectric medium of low-k to make the IMD layer, and it can effectively reduce capacitance.In the cmos circuit processing procedure below 0.35 μ m, the dielectric material that has been integrated the low-k of use is fluorine doped silica (fluorinatedSiO at present
2, FSG), its overall dielectric constant is about 3.5, but nationality is filled up slot between the metal wire below 0.35 micron by HDPCVD or PECVD processing procedure.But the stability of the fluorine ion in the FSG is not good, therefore can deposit the monoxide cap rock on the fsg layer surface, to prevent the problem that resistance uprises and lead corrodes of the connector that the fluorine ion diffusion is caused.
See also Fig. 1, it shows the generalized section of general IMD structure.After FEOL completes, include not display element and circuit in the semiconductor silicon base 10, and be coated with a dielectric layer 12.And in back-end process, definition forms a plurality of the first metal layer 14I on the surface of dielectric layer 12 earlier, and its material can adopt AlCu, can be as the ground floor internal connecting line.On the whole surface of dielectric layer 12 and the first metal layer 14I, evenly cover an oxide (silicon-rich oxide who is rich in silicon then, SRO) layer 16, utilize the HDPCVD method to deposit a HDP-FSG layer 18 subsequently, can fill up the space between the first metal layer 14I.With work, utilize the PECVD method to deposit a PE-FSG layer 20, can compensate the projection on HDP-FSG layer 18 surface and the out-of-flatness of depression.At last, by the CMP method with PE-FSG layer 20 flattening surface until reaching the required thickness of IMD structure, utilize the PECVD processing procedure to go up deposition monoxide cap rocks 22 in PE-FSG layer 20 surface again, the IMD structure just roughly completes.Follow-uply can on the flat surfaces of IMD structure, make a plurality of second metal level 14II, with as second layer internal connecting line.
Yet in above-mentioned IMD structure, metal level 14 has high stretching stress (tensile stress), reaches approximately+3～5E9dyne/cm
2, and the compression stress of HDP-FSG layer 18 only reaches 8E8dyne/cm
2, the compression stress of PE-FSG layer 20 only reaches-1.5E9dyne/cm
2, the compression stress of oxide cap 22 only reaches-7E8dyne/cm
2Hence one can see that, the total compression stress that piles up oxide structure in the IMD structure is much smaller than the stretching stress of metal level 14, therefore be very easy to produce crack (crack) problem in oxide cap 22, especially near closely spaced metal level 14, the easy more generation crack phenomenon of each above-mentioned oxide layer (16,18,20,22).And, along with semiconductor silicon substrate 10 lip-deep IMD structures are piled up the number increase, internal connecting line pile up the number of plies when also increasing thereupon, the accumulated value of the stretching stress that all metal levels 14 are produced, will be much larger than the compression stress accumulated value of all oxide layers (16,18,20,22), and the clean stress that so slowly successively increases, can cause serious oxide layer crack problem at last.
In view of this, in order to improve the rift defect of oxide layer, known a kind of method is to adopt with SiH
4Make oxide cap 22 for the PECVD processing procedure of reacting gas, it can make the compression stress of oxide cap 22 be increased to-1.83E9dyne/cm
2, but still can't improve rift defect.Another kind method is that to adopt TEOS be that the PECVD processing procedure of reacting gas is made oxide cap 22, and it can make the compression stress of oxide cap 22 be increased to-2.87E9dyne/cm
2, it can improve crack phenomenon, but can be because of fluorine diffusion phenomena gassing (bubble) problem of dielectric layer 12.
Summary of the invention
The objective of the invention is to propose a kind of oxide cap of dielectric structure between metal layers, can make the compression stress total value of oxide cap and dielectric layer between metal layers be equivalent to the stretching stress value of metal level, to solve common rift defect and air bubble problem.
The present invention is a kind of dielectric structure between metal layers, it is characterized in that including:
A plurality of metal levels are that definition is formed on the semiconductor substrate surface; One dielectric layer between metal layers covers this metal level and the surface at this semiconductor-based end predetermined altitude; And, cover the surface of this dielectric layer between metal layers by the monoxide cap rock that high-density electric slurry-source radio frequency processing procedure forms.
Described dielectric structure between metal layers, wherein this metal level is made of the AlCu material.
Described dielectric structure between metal layers, wherein this dielectric layer between metal layers includes:
The one first fluorine doped silica (HDP-FSG) layer that is formed by the high density plasma enhanced chemical vapor deposition method covers this metal level and the surface at this semiconductor-based end predetermined altitude; And
The one second fluorine doped silica (PE-FSG) that is formed by electricity slurry reinforcement formula chemical gaseous phase depositing process layer covers this this first fluorine doped silica layer to a predetermined altitude.
Described dielectric structure between metal layers, wherein the compression stress of this oxide cap can reach-4E9--3E9dyne/cm
2
Described dielectric structure between metal layers, other includes one and is rich in Si oxide (SRO) layer, covers the surface at these a plurality of metal levels and this semiconductor-based end.
Described dielectric structure between metal layers, wherein the inside of this oxide cap has many suspension keys (dangling bond), be enough to hold back the fluorine ion of diffusion, and can make this oxide cap have high compression stress, be enough to prevent rift defect and air bubble problem.
The present invention also provides a kind of manufacture method of dielectric structure between metal layers, comprises the following steps:
Definition forms a plurality of metal levels on the semiconductor substrate surface; Form a metal intermetallic dielectric layer and cover this metal level and the surface at this semiconductor-based end predetermined altitude; And, cover the surface of this dielectric layer between metal layers by the monoxide cap rock that high-density electric slurry-source radio frequency processing procedure forms.
The step that forms this metal intermetallic dielectric layer comprises: one first fluorine doped silica layer by the high density plasma enhanced chemical vapor deposition method forms covers this metal level and the surface at this semiconductor-based end predetermined altitude; And, cover this first fluorine doped silica layer to a predetermined altitude by the one second fluorine doped silica layer that electricity slurry reinforcement formula chemical gaseous phase depositing process forms.
The manufacture method that this oxide covers is to carry out this high-density electric slurry-source radio frequency processing procedure in a high density plasma enhanced chemical vapor deposition equipment, and its power supply only adopts the source r-f generator.
The power of the source r-f generator of this high-density electric slurry-source radio frequency is 1300-3100W.
The gas source SiH of this high-density electric slurry-source radio frequency
4Flow be 82-15sccm.
The gas source O of this high-density electric slurry-source radio frequency
2Flow be 150-27sccm.
The compression stress of this oxide cap can reach-4E9--3E9dyne/cm
2
The manufacture method of described dielectric structure between metal layers more comprises and forms one and be rich in silicon oxide layer and cover the surface at these a plurality of metal levels and this semiconductor-based end.
The inside of this oxide cap has more suspension key, and foot has been held back the fluorine ion of diffusion, and can make this oxide cap have high compression stress, and foot has prevented problems such as rift defect and bubble.
The present invention uses high-density electric slurry-source radio frequency (HDP-SRF) method to form oxide cap, with respect to a feature of former various oxide cap, can significantly improve the compression stress of oxide cap, to solve common rift defect and air bubble problem.
The present invention uses high-density electric slurry-source radio frequency (HDP-SRF) method to form oxide cap, another feature with respect to former various oxide cap, can make oxide cap inside have more suspension key (dangling bond), be enough to hold back the fluorine ion of diffusion.
Description of drawings
Fig. 1 is the generalized section of general IMD structure;
Fig. 2 is the generalized section of IMD structure of the present invention;
Fig. 3 is the schematic diagram of the employed HDPCVD equipment of HDP-SRF processing procedure of the present invention.
Symbol description
Semiconductor silicon substrate 10;
Dielectric layer 12;
The first metal layer 14I;
SRO layer 16;
HDP-FSG layer 18;
PE-FSG layer 20;
Oxide cap 22;
The second metal level 14II;
The technology of the present invention:
Semiconductor silicon substrate 30;
Dielectric layer 32;
The first metal layer 34I;
SRO layer 36;
HDP-FSG layer 38;
PE-FSG layer 40;
Embodiment
See also Fig. 2, it shows the generalized section of IMD structure of the present invention.After FEOL completes, include not display element and circuit in the semiconductor silicon base 30, and be coated with a dielectric layer 32.And in back-end process, forming a plurality of the first metal layer 34I prior to definition on the surface of dielectric layer 32, its material can adopt AlCu, can be as the ground floor internal connecting line.Then, oxide (the silicon-rich oxide of silicon is rich in even covering one on the whole surface of dielectric layer 32 and the first metal layer 34I, SRO) layer 36 utilizes the HDPCVD method to deposit a HDP-FSG layer 38 subsequently, can fill up the space between the first metal layer 34I.And then, utilize the PECVD method to deposit a PE-FSG layer 40, can compensate the projection on HDP-FSG layer 38 surface and the out-of-flatness of depression, and can provide the IMD structure required thickness.The follow-up CMP processing procedure that utilizes is with the flattening surface of PE-FSG layer 40.At last, carry out high-density electric slurry-source radio frequency (HDP-SRF) processing procedure in a HDPCVD equipment, go up deposition one in PE-FSG layer 40 surface and have the oxide cap 42 of high compression stress, the IMD structure just roughly completes.Follow-uply can on the flat surfaces of IMD structure, make a plurality of second metal level 34II, with as the 2nd layer of internal connecting line.
See also Fig. 3, it shows the schematic diagram of the employed HDPCVD equipment of HDP-SRF processing procedure of the present invention.One HDPCVD equipment 50 includes a reaction cavity 52, a gas delivery system 54, a gas extraction system 56, a processing procedure control system 58, a bias voltage and penetrates screen (bias radio frequency, BRF) (source radio frequency, SRF) generator 62 for a generator 60 and a source radio frequency.When carrying out the HDP-SRF processing procedure, close bias voltage and penetrate screen generator 60, only open use source r-f generator 62, in the process conditions of preferred embodiment be: the power of source r-f generator 62 is 1300-3100w, the flow of gas source SiH4 is 82-15sccm, gas source O
2Flow be 150-27sccm.Learn through experimental result, as the gas source SiH of HDP-SRF processing procedure
4Flow when being 76-86sccm, the compression stress of oxide cap 42 can reach-4E9--3E9dyne/cm
2, can make oxide cap 42 inside have more suspension key (dangling bond), be enough to hold back the fluorine ion of diffusion, and can make oxide cap 42 have high compression stress, be enough to prevent problems such as rift defect and bubble.
The above only is the preferable embodiment of the present invention, and so it is not in order to qualification the present invention, and any people who is familiar with this skill is in the technical scope that the present invention discloses, and the variation that can expect easily or replacement all should be encompassed within the protection of the present invention.Therefore protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (15)
1. dielectric structure between metal layers is characterized in that including:
A plurality of metal levels, definition is formed on the semiconductor substrate surface; One dielectric layer between metal layers covers this metal level and the surface at this semiconductor-based end predetermined altitude; And, cover the surface of this dielectric layer between metal layers by the monoxide cap rock that high-density electric slurry-source radio frequency processing procedure forms.
2. dielectric structure between metal layers as claimed in claim 1, wherein this metal level is made of the AlCu material.
3. dielectric structure between metal layers as claimed in claim 1, wherein this dielectric layer between metal layers includes:
The one first fluorine doped silica layer that is formed by the high density plasma enhanced chemical vapor deposition method covers this metal level and the surface at this semiconductor-based end predetermined altitude; And
The one second fluorine doped silica layer that is formed by electricity slurry reinforcement formula chemical gaseous phase depositing process covers this first fluorine doped silica layer to a predetermined altitude.
4. dielectric structure between metal layers as claimed in claim 1, wherein the compression stress of this oxide cap can reach-4E9--3E9dyne/cm
2
5. dielectric structure between metal layers as claimed in claim 1, other includes one and is rich in silicon oxide layer, covers the surface at these a plurality of metal levels and this semiconductor-based end.
6. dielectric structure between metal layers as claimed in claim 1, wherein the inside of this oxide cap has many suspension keys, be enough to hold back the fluorine ion of diffusion, and can make this oxide cap have high compression stress, be enough to prevent rift defect and air bubble problem.
7. the manufacture method of a dielectric structure between metal layers comprises the following steps:
Definition forms a plurality of metal levels on the semiconductor substrate surface;
Form a metal intermetallic dielectric layer and cover this metal level and the surface at this semiconductor-based end predetermined altitude; And
By the monoxide cap rock that high-density electric slurry-source radio frequency processing procedure forms, cover the surface of this dielectric layer between metal layers.
8. the manufacture method of dielectric structure between metal layers as claimed in claim 7, the step that wherein forms this metal intermetallic dielectric layer comprises:
One first fluorine doped silica layer by the high density plasma enhanced chemical vapor deposition method forms covers this metal level and the surface at this semiconductor-based end predetermined altitude; And
One second fluorine doped silica layer by electricity slurry reinforcement formula chemical gaseous phase depositing process forms covers this first fluorine doped silica layer to a predetermined altitude.
9. the manufacture method of dielectric structure between metal layers as claimed in claim 7, wherein the manufacture method of this oxide covering is to carry out this high-density electric slurry-source radio frequency processing procedure in a high density plasma enhanced chemical vapor deposition equipment, and its power supply only adopts the source r-f generator.
10. the manufacture method of dielectric structure between metal layers as claimed in claim 9, wherein the power of the source r-f generator of this high-density electric slurry-source radio frequency is 1300-3100W.
11. the manufacture method of dielectric structure between metal layers as claimed in claim 9, wherein the gas source SiH of this high-density electric slurry-source radio frequency
4Flow be 82-15sccm.
12. the manufacture method of dielectric structure between metal layers as claimed in claim 9, wherein the gas source O of this high-density electric slurry-source radio frequency
2Flow be 150-27sccm.
13. the manufacture method of dielectric structure between metal layers as claimed in claim 7, wherein the compression stress of this oxide cap can reach-4E9--3E9dyne/cm
2
14. the manufacture method of dielectric structure between metal layers as claimed in claim 7 more comprises and forms one and be rich in silicon oxide layer and cover the surface at these a plurality of metal levels and this semiconductor-based end.
15. the manufacture method of dielectric structure between metal layers as claimed in claim 7, wherein the inside of this oxide cap has more suspension key, foot has been held back the fluorine ion of diffusion, and can make this oxide cap have high compression stress, and foot has prevented rift defect and air bubble problem.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02127646 CN1205656C (en) | 2002-08-06 | 2002-08-06 | Dielectric structure between metal layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02127646 CN1205656C (en) | 2002-08-06 | 2002-08-06 | Dielectric structure between metal layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1474438A CN1474438A (en) | 2004-02-11 |
| CN1205656C true CN1205656C (en) | 2005-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02127646 Expired - Lifetime CN1205656C (en) | 2002-08-06 | 2002-08-06 | Dielectric structure between metal layers |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7221039B2 (en) * | 2004-06-24 | 2007-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thin film transistor (TFT) device structure employing silicon rich silicon oxide passivation layer |
| CN102815663B (en) * | 2011-06-08 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
| CN107346743B (en) * | 2016-05-06 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacturing method |
-
2002
- 2002-08-06 CN CN 02127646 patent/CN1205656C/en not_active Expired - Lifetime
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| CN1474438A (en) | 2004-02-11 |
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Granted publication date: 20050608 |