CN1205587C - Charge-coupled device image detection device and method for accelerating detection of images - Google Patents

Abstract

A method for accelerating image detection and a CCD image detection device using the method enable the CCD image detection device to detect images again without removing residual charge packets, thereby accelerating the processing speed.

Description

Charge-coupled device image detection device and method for accelerating detection of images

technical field

The invention relates to a CCD image detection device and a method for accelerating detection of images thereof.

Background technique

Since a charge-coupled device (Charge-Coupled Device, referred to as CCD) can be used to produce a very high-density shift register or sequential memory, the CCD is widely used in image processing systems and digital signal processing systems. For example, in electronic devices such as scanners, digital cameras, fax machines, photocopiers, etc., CCD image detection devices must be used.

As far as traditional scanners or scanners using CIS (Contact Image Sensor) are concerned, the image detection processing part may use a CCD image detection device. FIG. 1 is a schematic diagram schematically showing the internal structure of a CCD image detection device. A general CCD image detection device includes at least one row of image sensing units (P ₁ -P _n ) for detecting images and generating charge packets corresponding to the intensity of light; a CCD analog shift register 10, There are a plurality of temporary storage units (SH ₁ ˜SH _2n ) for receiving and storing the above-mentioned induced charge packets in parallel; and an output amplifier (OP) for converting the charge into a corresponding voltage level V _im ; wherein, The CCD analog shift register 20 is controlled by the clock pulse signals Φ ₁ and Φ ₂ to sequentially output the charge stored in each register unit to the output amplifier (OP).

Fig. 2 (a)～(f) is to show in the CCD analog shift register shown in Fig. 1, the transfer situation schematic diagram of registering charge packet, and the waveform of clock pulse signal Φ ₁ , Φ ₂ ; Wherein, above-mentioned clock pulse signal Φ ₁ and Φ ₂ are respectively coupled to the shift control electrodes G _2a-1 and G _2a (1≤a≤n).

The structure of the CCD register is shown in Figure 2(a). For the sake of simplicity in the illustration, only five register units (SH ₁ ~SH ₅ ) and their corresponding five shift control electrodes (G ₁ ~G ₅ ). In addition, it is assumed that the threshold voltage (Threshold voltage) is zero.

When t=t ₁ , Φ ₁ = 0 and Φ ₂ = V, so there is no potential barrier under the electrodes G ₁ , G ₃ and G ₅ , but a ladder-shaped potential is formed under the electrodes G ₂ and G ₄ Barrier (stepbarrier), as shown in Figure 2(b). Assume that a charge representing a logic 1 is stored under electrodes _G2 and _G4 (shown in dashed lines).

When t=t ₂ , Φ ₁ =Φ ₂ =V/2, at this time the profile of the potential barrier distribution under each electrode (G ₁ -G ₅ ) has the same shape, as shown in Fig. 2(c). Arrows on the contour plots indicate that as time increases from t ₁ to t ₂ and t ₃ , the potential barrier under the odd electrodes (G ₁ , G ₃ , G ₅ ) increases and that under the even electrodes (G ₂ , G ₄ ) increases. The barrier falls.

At t = t ₃ , a potential profile as shown in Fig. 2(d) appears. Therefore, the charges present under the _G2 and _G4 electrodes are transferred under the locations of the _G1 and _G3 electrodes, respectively.

Finally, when t=t ₄ , Φ ₁ =V and Φ ₂ =0, the result is the potential energy distribution profile shown in Fig. 2(e). During the period from t ₁ to t ₄ , the charge moves one electrode to the right; similarly, the charge moves to the right by one electrode during the period from t ₅ to t ₆ and from t ₇ to t ₈ .

At present, the resolution specifications of scanners are mostly 600dpi (dot/inch) or higher; in terms of 600dpi resolution, taking scanning A4 size documents (21cm wide, 29.7cm long) as an example, the CCD image used by the scanner In the detection device, at least about 7016 (29.7/2.54×600) image sensing units and 14032 (7016×2) register units are required to receive and store image induced charges in parallel.

As far as the CCD detection devices currently provided by manufacturers are concerned, the specifications of each standard product generally include more than 10,000 image sensing units. Taking the standard CCD detection device with 12,800 image sensing units as an example (that is, with a total of 25,600 storage units from SH ₁ to SH ₂₅₆₀₀ ), if it is applied to an A4-size scanner with a resolution of 600dpi, only the storage units The induction charge packets received and stored by SH ₁ ~ SH ₁₄₀₃₂ really correspond to the scanned image, while the other storage units SH ₁₄₀₃₃ ~ SH ₂₅₆₀₀ will never correspond to any induction image signal, only a little due to light leakage or other factors. The resulting residual charge packets are present in each scan sensing, however there is no real corresponding scan image for these residual charges.

According to the traditional method described in Figure 2(a)~(e), the charges in the register units are sequentially output in series and converted into corresponding voltages; when the charges of the register units SH ₁ to SH ₁₄₀₃₂ are output; the register unit The residual charge packets in SH ₁₄₀₃₃ -SH ₂₅₆₀₀ are also shifted to the output terminal (ie, the output amplifier OP) by 14032 register units respectively, and stored in the original positions of SH ₁ -SH ₁₁₅₆₈ register units. For the remaining charges transferred to the register cells SH ₁ -SH ₁₁₅₆₈ , additional time must be spent. The 11568 residual charge packets are serially output one by one in advance. Otherwise, when the next group of images is scanned, the above 11568 residual charges will be respectively accumulated on the image induction charges newly received by the register units SH ₁ -SH ₁₁₅₆₈ , resulting in distortion of the scanned image.

After each image scan, the residual charge packets in the storage units SH ₁₄₀₃₃ ~ SH ₂₅₆₀₀ have absolutely no effect on the processing of the scanned image, but in order to avoid distortion of the scanned image, additional time must be used to process the 11568 residual charge packets output, which wastes processing time and reduces the processing speed of the scanner. To reduce the time to process residual charge packets. The currently used solution is to increase the frequency of the signals Φ ₁ and Φ ₂ when moving 11568 residual charge packets out of the CCD analog shift register, so as to speed up the removal of the residual charge packets. However, when removing the charges of the register units SH ₁ ~ SH ₁₄₀₃₂ , the signals Φ ₁ and Φ ₂ operate at normal frequency; when removing the residual charge packets, the signals Φ ₁ and Φ ₂ must be switched to a high frequency, which will cause Difficulties in control and increased complexity of the circuit also increase the relative cost, and the processing time that can actually be reduced is not much. Therefore, if a method and mechanism can be proposed, the CCD analog shift register does not need to move out the above-mentioned residual charge packets one by one, and the problem of distortion of the scanned image can not be generated, which can not only speed up the time of image detection ( That is to speed up the processing time of the scanner), and also reduce the complexity of the circuit.

Contents of the invention

In view of this, an object of the present invention is to provide a method for speeding up image detection, so that the CCD image detection device can detect the image again without removing the residual charge packets to speed up the processing speed.

According to one aspect of the present invention, a CCD image detection device is provided, including: a plurality of image sensing units (P ₁ ~ P _n ), which are used to respectively sense light and generate charge packets compared with light intensity; CCD shift registers, including : a plurality of storage units: the first storage unit (SH ₁ ) to the 2nth storage unit (SH _2n ), used to store the charge packet, wherein the first storage unit (SH ₁ ) to the 2j-2th storage unit ( SH _{2j-2 )} , j<n), actually corresponding to a storage unit _of an image to be detected; ) of the first electrode (G ₁ ) to the 2nth electrode (G _2n ) of a plurality of displacement control electrodes; the first electrode (G ₁ ), the third electrode (G ₃ ), the fifth electrode of the displacement control electrode Electrode (G ₅ )...The 2j-5th electrode (G _2j-5 ), the 2j-3th electrode (G _2j-3 ) are both coupled to the first clock pulse signal; the second electrode (G ₂ ), the fourth electrode (G ₄ ), the sixth electrode (G ₆ ) ... the 2j-4th electrode (G _2j-4 ), the 2j-2th electrode (G _2j-2 ) are all coupled to the second clock pulse signal ; Controlled by the first and second clock pulse signals, the charge packets in the first register unit (SH ₁ ) to the 2j-2th register unit (SH _2j-2 ) are sequentially distributed by the In the above CCD shift register; wherein, the 2j-2th electrode (G _2j-2 ) and the 2jth electrode (G _2j ) control electrode in the plurality of shift control electrodes are respectively coupled to the first potential, and the second Potential, so that the 2j-2th register unit (SH _2j-2 ) and the 2jth register unit (SH _2j ) among the plurality of register units constitute a barrier unit, so that the 2j+1th register unit (SH _2j+1 ) to the 2nth storage unit (SH _2n ) will not be moved into the first storage unit (SH ₁ ) to the 2j-2th storage unit (SH _2j-2 ).

According to another aspect of the present invention, there is provided a kind of accelerated detection image method for the CCD image detection device described in claim 1; comprising: 2j-1 electrodes (G _{2j- 1} ), the 2jth electrode (G _2j ) control electrode is respectively coupled to the first potential and the second potential, so that the 2j-1th registering unit (SH _2j-1 ) and the 2jth registering unit among the plurality of registering units (SH _2j ) constitutes a barrier unit; the first electrode (G ₁ ), the third electrode (G ₃ ), the fifth electrode (G ₅ )...the 2j-5th electrode (G _2j-5 ), the 2j-3th electrode (G _2j-3 ) are both coupled to the first clock pulse signal; the second electrode (G ₂ ), the fourth electrode (G ₄ ), the sixth electrode ( G ₆ )...the 2j-4th electrode (G _2j-4 ) and the 2j-2th electrode (G _2j-2 ) are both coupled to the second clock pulse signal; the plurality of image sensing units (P ₁ -P _n ) respectively sense images and generate charge packets compared with light intensity; store the charge packets in the plurality of register units: the first register unit (SH ₁ ) to the 2nth register unit (SH _2n ); 1. Under the control of the second clock pulse signal, the charge packets in the first register unit (SH ₁ ) to the 2j-2 register unit (SH _2j-2 ) are sequentially transferred from the CCD shift register wherein, the charge packets registered in the 2j+1th register unit (SH _2j+1 )～2nth register unit (SH _2n ) will not be moved into the first register unit due to the function of the blocking unit unit (SH ₁ ) to the 2j-2th storage unit (SH _2j-2 ), so it is not necessary to store the electricity stored in the 2j+ _{1-th storage unit (SH 2j+1 )} The purse is removed, and the CCD image detection device can detect the image again; then let the multiple image sensing units (P ₁ ~ P _n ) respectively sense the image and generate a charge packet compared with the light intensity, and repeat the process of The steps of storing charge packets and moving out of the CCD shift register.

The CCD image detection device to _{which the} method of the present invention is applicable includes: a plurality of image sensing units (P _{1 ˜P n} ); G _2n ) constitutes a CCD shift register; the method comprises the steps:

(a) Assuming that the register units SH ₁ to SH _2j-2 are register units that actually correspond to the scanned image, the G _2j-1 and G _2j control electrodes among the plurality of shift control electrodes can be respectively coupled to The first potential and the second potential make the SH _2j-1 and SH _2j storage units among the plurality of storage units constitute a blocking unit; wherein j<n;

(b) coupling odd-numbered electrodes G ₁ , G ₃ , G ₅ . . . G _2j-5 , G _2j-3 of the shift control electrodes to the first clock pulse signal;

(c) coupling even-numbered electrodes G ₂ , G ₄ , G ₆ . . . G _2j-4 , G _2j-2 of the displacement control electrodes to the second clock pulse signal;

(d) The plurality of image sensing units (P ₁ -P _n ) respectively sense images and generate charge packets that are compared with light intensity;

(f) storing the charge packet in the plurality of storage units (SH ₁ ˜SH _2n );

(g) Under the control of the first and second clock pulse signals, the charge packets in the register units SH ₁ to SH _2j-2 are sequentially shifted out of the CCD shift register; wherein, The residual charge packets stored in the storage units SH _2j+1 -SH _2n will not be moved into the storage units (SH ₁ -SH _2j-2 ) due to the function of the blocking unit;

(h) Let the plurality of image sensing units (P ₁ -P _n ) respectively sense images and generate charge packets corresponding to light intensity, and repeat the above steps (d)-(g) to store and remove the charge packets steps of the CCD shift register.

Based on the method for accelerating image detection, another object of the present invention is to propose a novel CCD image detection device, which has a processing speed superior to that of traditional CCD image detection devices.

The CCD image detection device of the present invention includes: a plurality of image sensing units (P ₁ -P _n ) for respectively sensing light and generating charge packets compared with light intensity; and a CCD shift register.

The above-mentioned CCD shift register includes: a plurality of register units (SH ₁ ˜SH _2n ) for registering the charge packets; and a plurality of shift control electrodes (G ₁ ˜G _2n ). G ₁ , G ₃ , G ₅ . . . G _2j-5 , G _2j-3 of the shift control electrodes are all coupled to the first clock pulse signal, and G ₂ , G ₄ , G ₆ . Both G _2j-4 and G _2j-2 are coupled to the second clock pulse signal; controlled by the first and second clock pulse signals, the electric circuits in the above-mentioned register units (SH ₁ -SH _2j-2 ) The purse is sequentially shifted out from the CCD shift register.

Wherein, the G _2j-1 and G _2j control electrodes in the plurality of shift control electrodes are respectively coupled to the first potential and the second potential, so that SH _2j-1 and SH _2j in the plurality of register units register The cells constitute barrier units, so that the charge packets stored in the register units SH _2j+1 -SH _2n will not be moved into the register units (SH ₁ -SH _2j-2 ); j<n.

The first clock signal and the second clock signal are complementary signals to each other. The voltage of the first potential is smaller than the voltage of the second potential.

Description of drawings

In order to make the above-mentioned purposes, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Fig. 1 outline shows the schematic diagram of the internal structure of CCD image detection device;

Among Fig. 2 (a)～(e) summary display Fig. 1, the schematic diagram of the charge transfer situation of CCD analog shift register of the present invention;

Fig. 2(f) is a waveform diagram showing clock pulse signals Φ ₁ and Φ ₂ ;

Fig. 3 shows the schematic diagram of the internal structure of the CCD image detection device of the present invention;

4(a)-(e) schematically show the schematic diagrams of the charge transfer of the CCD analog shift register of the present invention.

Detailed ways

Fig. 3 shows a schematic diagram of the internal structure of the CCD image detection device of the present invention. Referring to Fig. 3, the CCD image detection device of the present invention includes: a plurality of image sensing units (P ₁ ~ P _n ), which are used to respectively sense light and generate charge packets compared to the intensity of light; CCD shift register 30 includes: a register unit (SH ₁ ˜SH _2n ), used to register the charge packet; a plurality of shift control electrodes (G ₁ ˜G _2n ); and an output amplifier (OP).

_The odd-numbered electrodes _{G 1 , G 3 ,} G ₅ . G ₄ , G ₆ ...G _2j-4 , G _2j-2 are all coupled to the second clock pulse signal Φ ₂ ; the shift control electrodes G _2j+1 , G _2j+3 , ...G _2n-3 , G _{2n -1} can also be coupled to the first clock pulse signal Φ ₁ , G _2j+2 , G _2j+4 , ... G _2n-2 , G _2n of the shift control electrodes can also be coupled to the second clock pulse signal Φ ₂ . The waveforms of the first and second clock pulse signals (Φ ₁ , Φ ₂ ) are shown in Fig. 2(f).

The G _2j-1 and G _2j control electrodes among the plurality of shift control electrodes are respectively coupled to the first potential V ₁ and the second potential V ₂ , so that the SH _2j-1 and SH _2j register units form a blocking unit.

Controlled by the first and second clock pulse signals (Φ ₁ , Φ ₂ ), the charge packets in the register units (SH ₁ ~SH _2j-2 ) are sequentially transferred from the CCD shift register shifted out to the output amplifier OP. However, the charge packets stored in the storage units SH _2j+1 -SH _2n will not be moved into the above-mentioned storage units (SH ₁ -SH _2j+2 ) due to the function of the barrier unit.

Taking the resolution of 600dpi (dot/inch) as an example, the CCD image detection device used needs at least about 7016 (j-1) image sensing units, that is, 14032 register units. Therefore, when making a standard CCD detection device with 12800 (n) image sensing units, it is possible to choose to couple the displacement control electrodes G ₁₄₀₃₃ and G ₁₄₀₃₄ (G _2j-1 , G _2j ) to the first potential V ₁ (voltage 0) and the second potential V2 (positive voltage V) to form a barrier unit. In this way, the charge packets in the register units SH ₁ ~ SH ₁₄₀₃₂ can be moved out of the CCD shift register 30 under the control of the first clock pulse signal Φ ₁ and the second clock pulse signal Φ ₂ , but the residual charges in SH ₁₄₀₃₅ ~ SH ₂₅₆₀₀ are not will be moved into the storage units SH ₁ ~SH ₁₄₀₃₂ .

4( a )-( e ) schematically show the schematic diagrams of charge transfer in the CCD analog shift register of the present invention. Figures 4(a)-(e) only illustrate part of the register cells, and shift control electrodes.

The method for speeding up the image detection of the present invention allows the CCD image detection device to detect the image again without removing the residual charge packets, thereby speeding up the processing speed. Referring to Figures 3 and 4(a)-(e), the method for accelerating image detection includes the following steps.

Firstly, the control electrodes G ₁₄₀₃₃ and G ₁₄₀₃₄ (that is, G _2j-1 , G _2j ; j=7017) among the plurality of displacement control electrodes are respectively coupled to the first potential V ₁ (voltage 0) and the second potential V 1 . The potential V ₂ (positive voltage V) makes the SH ₁₄₀₃₃ , SH ₁₄₀₃₄ (that is, SH _2j-1 , SH _2j ) storage units among the plurality of storage units constitute a blocking unit.

G ₁ , G ₃ , G ₅ . . . G ₁₄₀₂₉ , G ₁₄₀₃₁ (G _2j-5 , G _2j-3 ) of the shift control electrodes are coupled to a first clock pulse signal Φ ₁ ; and, the shift G ₂ , G ₄ , G ₆ . . . G ₁₄₀₃₀₂ , G ₁₄₀₃₂ (G _2j-4 , G _2j-2 ) of the control electrodes are all coupled to the second clock pulse signal Φ ₂ ; as shown in FIG. 4( a ).

The method of the present invention is mainly applicable to the CCD image detection device with the structure shown in FIG. 3 . In this embodiment, _the shift control electrodes G ₁₄₀₃₅ , G ₁₄₀₃₇ ... ~G _{25599 may also} be selectively coupled to the first clock pulse signal Φ ₁ ; Optionally, the second clock pulse signal Φ ₂ can also be coupled.

When the CCD image detection device detects an image, the plurality of image sensing units (P ₁ -P ₁₂₈₀₀ ) respectively generate charge packets (indicated by dotted lines) that are compared with the light intensity; and store them in the coupler register unit (SH _2j ; j=1～12800), as shown in Fig. 4(b). The charge packets stored before the SH ₁₄₀₃₃ are correct image-induced charges, and the charge packets stored after the SH ₁₄₀₃₃ are residual charges.

Under the control of the first and second clock pulse signals Φ ₁ and Φ ₂ , the charge packets in the register units SH ₁ ~ SH ₁₄₀₃₂ are sequentially shifted out of the CCD shift register 30; detailed process as described below.

When t=t ₁ , Φ ₁ =0 and Φ ₂ =V, so there is no potential barrier under the odd-numbered electrodes G ₁₄₀₂₉ -G ₁₄₀₃₇ , but a ladder-shaped potential barrier is formed under the even-numbered electrodes G ₁₄₀₂₈ -G ₁₄₀₃₆ (step barrier), as shown in Figure 4(b). Assume that charges representing logic 1 are stored under the even-numbered electrodes G ₁₄₀₂₈ -G ₁₄₀₃₆ (indicated by dotted lines).

When t=t ₂ , Φ ₁ =Φ ₂ =V/2, at this time, except for electrodes G ₁₄₀₃₃ and G ₁₄₀₃₄ , the contours of the potential barrier distribution under each electrode (G ₁ ~ G ₂₅₆₀₀ ) have the same shape , as shown in Figure 4(c). Arrows on the contour plots indicate that as time increases from t ₁ to t ₂ and t ₃ , the potential barrier rises under odd electrodes (G ₁₄₀₂₉ , G ₁₄₀₃₁ ... etc.) and under even electrodes (G ₁₄₀₃₀ , G ₁₄₀₃₂ ... etc.) The potential barrier drops.

At t=t ₃ , Φ ₁ =3V/4, Φ ₂ =V/4, and the potential profile shown in Fig. 4(d) appears. Therefore, the charges existing under the G ₁₄₀₃₀ and G ₁₄₀₃₂ electrodes are transferred to under the positions of the G ₁₄₀₂₉ and G ₁₄₀₃₁ electrodes, respectively.

Finally, when t=t ₄ , Φ ₁ =V and Φ ₂ =0, the result is the potential energy distribution profile shown in Fig. 4(e). During the period from t ₁ to t ₄ , the charge moves one electrode to the right; similarly, the charge moves to the right by one electrode during the period from t ₅ to t ₆ and from t ₇ to t ₈ . According to this method, the charge packets stored before the SH ₁₄₀₃₃ will be shifted out of the CCD shift register 30 one by one; and the residual charges stored after the SH ₁₄₀₃₃ , because the potential barriers under the electrodes G ₁₄₀₃₃ and G ₁₄₀₃₄ will not follow The first and second clock pulse signals Φ ₁ and Φ ₂ change, so they will not be moved into the register unit before SH ₁₄₀₃₃ .

After all the charge packets stored before the register unit SH ₁₄₀₃₃ are completely moved out of the CCD shift register 30, the above-mentioned multiple image sensing units (P ₁ -P _n ) are then respectively induced to generate images and generate charge packets that are compared to the light intensity, And repeat the steps of registering the charge packet and moving out of the CCD shift register 30 .

Known by the method that the present invention proposes, after all the charge packets stored in the register unit SH ₁₄₀₃₃ are moved out of the CCD shift register 30, the CCD image detection device using the above-mentioned acceleration method can perform image scanning again; however, the traditional CCD image detection device, the remaining charge packets must still be moved out of the CCD shift register, so the processing efficiency of the traditional CCD image detection device is far lower than that of the CCD image detection device proposed by the present invention.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention; for example, the present invention adjusts and changes the signal waveform of the energy level barrier, and is not limited to the signal waveforms proposed in the above-mentioned embodiments. Therefore, any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the claims.

Claims (10)

1. ccd image pick-up unit comprises:

A plurality of image sensings unit (P ₁～P _n), in order to respond to light respectively and to produce the charge packet that in contrast to light intensity;

The CCD shift register comprises: a plurality of deposit units: the first deposit unit (SH ₁)～2n deposit unit (SH _2n), in order to deposit described charge packet, the first deposit unit (SH wherein ₁)～2j-2 deposit unit (SH _2j-2), j＜n is in fact corresponding to the deposit unit of an image to be detected; And correspond respectively to described a plurality of deposit unit: the first deposit unit (SH ₁)～2n deposit unit (SH _2n) the first electrode (G of a plurality of displacement control electrodes ₁)～2n electrode (G _2n); First electrode (the G of described displacement control electrode ₁), third electrode (G ₃), the 5th electrode (G ₅) ... 2j-5 electrode (G2 _J-5), 2j-3 electrode (G _2j-3) all couple first clock pulse signal; Second electrode (the G of described displacement control electrode ₂), the 4th electrode (G ₄), the 6th electrode (G ₆) ... 2j-4 electrode (G _2j-4), 2j-2 electrode (G _2j-2) all couple the second clock pulse signal; By the control of described first, second clock pulse signal, make the described first deposit unit (SH ₁)～2j-2 deposit unit (SH _2j-2) in described charge packet in order by shifting out in the described CCD shift register;

Wherein, the 2j-2 electrode (G2 in described a plurality of displacement control electrode _J-2), 2j electrode (G _2j) control electrode couples first current potential, and second current potential respectively, makes the 2j-2 deposit unit (SH in described a plurality of deposit unit _2j-2), 2j deposit unit (SH _2j) constitute blocker unit, make described 2j+1 deposit unit (SH _2j+1)～2n deposit unit (SH _2n) in the charge packet deposited can not move into the described first deposit unit (SH ₁)～2j-2 deposit unit (SH _2j-2) in.

2. device as claimed in claim 1, wherein, described first clock pulse signal and described second clock pulse signal are complementary signal each other.

3. device as claimed in claim 1, wherein, the voltage of described first current potential is less than the voltage of described second current potential.

4. device as claimed in claim 3, wherein, the voltage of described first current potential is 0, the voltage of above-mentioned second current potential is positive voltage.

5. device as claimed in claim 1, wherein, the 2j+1 electrode (G of described displacement control electrode _2j+1), 2j+3 electrode (G _2j+3) ... 2n-1 electrode (G _2n-1) couple described first clock pulse signal, the 2j+2 electrode (G of described displacement control electrode _2j+2), 2j+4 electrode (G _2j+4) ... 2n electrode (G _2n) couple described second clock pulse signal.

6. acceleration detection image method that is used for the described ccd image pick-up unit of claim 1; Comprise:

With in described a plurality of displacement control electrodes 2j-1 electrode (G _2j-1), 2j electrode (G _2j) control electrode couples first current potential, and second current potential respectively, makes the 2j-1 deposit unit (SH in described a plurality of deposit unit _2j-1), 2j deposit unit (SH _2j) the formation blocker unit;

First electrode (the G with described displacement control electrode ₁), third electrode (G ₃), the 5th electrode (G ₅) ... 2j-5 electrode (G _2j-5), 2j-3 electrode (G _2j-3) all couple first clock pulse signal;

Second electrode (the G with described displacement control electrode ₂), the 4th electrode (G ₄), the 6th electrode (G ₆) ... 2j-4 electrode (G _2j-4), 2j-2 electrode (G _2j-2) all couple the second clock pulse signal;

Make described a plurality of image sensings unit (P ₁～P _n) sensed image and produce the charge packet in contrast to light intensity respectively;

Described charge packet is deposited at described a plurality of deposit unit: the first deposit unit (SH ₁)～2n deposit unit (SH _2n);

Under the control of described first, second clock pulse signal, make the described first deposit unit (SH ₁)～2j-2 deposit unit (SH2 _J-2) in described charge packet in order by shifting out in the described CCD shift register; Wherein, described 2j+1 deposit unit (SH _2j+1)～2n deposit unit (SH _2n) in the charge packet deposited, can not move into the described first deposit unit (SH by the effect of described blocker unit ₁)～2j-2 deposit unit (SH _2j-2) in, so need not be with described 2j+1 deposit unit (SH _2j+1)～2n deposit unit (SH _2n) in the electric charge steamed stuffed bun deposited shifting out, described ccd image pick-up unit i.e. detected image once more;

Make described a plurality of image sensings unit (P again ₁～P _n) sensed image and produce and in contrast to the charge packet of light intensity respectively, and repeat the described step of charge packet being deposited and shifted out described CCD shift register.

7. method as claimed in claim 6, wherein, described first clock pulse signal and described second clock pulse signal are complementary signal each other.

8. method as claimed in claim 6, wherein, the voltage of described first current potential is less than the voltage of described second current potential.

9. method as claimed in claim 6, wherein, the voltage of described first current potential is 0, the voltage of described second current potential is positive voltage.

10. method as claimed in claim 6, wherein, further with the 2j+1 electrode (G of described displacement control electrode _2j+1), 2j+3 electrode (G _2j+3) ... 2n-1 electrode (G _2n-1) couple described first clock pulse signal, and with the 2j+2 electrode (G of described displacement control electrode _2j+2), 2j+4 electrode (G _2j+4) ... 2n electrode (G _2n) couple described second clock pulse signal.

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