CN1204864A - Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing - Google Patents
Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing Download PDFInfo
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Abstract
A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.
Description
The present invention relates to the manufacturing of semiconductor integrated circuit, more particularly, relate to the method and apparatus of etching integrated circuit stack in etching process after being etched with so that the polymer deposition layer that forms is eliminated easily.
In the manufacture process of semiconductor integrated circuit, components and parts (as transistor, capacitor and resistor) be formed at typically the semiconductor wafer made by silicon or substrate the inside or/and above.Other wafer as the silicon on GaAs or the insulator, also can be used.The metal interconnecting wires that forms by the metal layer of etching deposit on wafer is used to each device is linked together then, to form required circuit.For the ease of discussing, Figure 1A is the simple sectional view (not to scale (NTS)) of a lamination 20, represents each layer that forms in the typical semiconductor integrated circuit manufacture process.One wafer 100 is shown in the bottom of lamination 20.For brevity, wafer comprises various devices.Be formed with monoxide or interlayer dielectric layer 102 on the surface of wafer 100, it is made by silicon dioxide typically.Mix or non-doping silication glass,, also can be used for forming interlayer dielectric layer as BSG, PSG and BPSG.One bottom barrier 104 places on the interlayer dielectric layer 102, and be positioned near the metal layer 106 that the back will deposit, it is made by Ti, TiW, TiN, Ta nitride, tungsten carbide, chromium nitride, hafnium nitride, titanium carbide, hafnium carbide, molybdenum carbide or other suitable barrier material typically.Bottom barrier 104 may be a monofilm or the composite bed be made up of multilayer film.Bottom barrier (if any) rises basically and prevents that silicon atom from spreading to metal layer 106 from interlayer dielectric layer 102, thus the effect that improves reliability.
Each layer of lamination 20 understood by those skilled in the art easily, can form with multiple existing depositing operation, these depositing operations comprise: chemical vapour deposition (CVD) (CVD, Chemical Vapordeposition), plasma reinforced chemical vapour deposition (PEVCD, plasma-enhanced chemicalvapor depositon) and physical vapour deposition (PVD) (PVD, physical vapor deposition) as sputter and/or plating.Although each that illustrates layer is schematically, it must be noted that to have other other layer between upper and lower or layer.In addition, be not that all layers that illustrate all must occur, some or all layers can substitute with a plurality of different layers.For example, between barrier layer and metal layer, can deposit one or more layers, and can not slacken the function on barrier layer.
In order to generate foregoing metal interconnecting wires, utilize suitable photoetching technique to come to be photoresist layer 114 composition, follow the metal film that etching exposes to the open air.For example, this photoetching technique comprises by photo anti-corrosion agent material is exposed to be photoresist layer 114 composition in contact or stepping mask aligner and/or the x-ray instrument, with photo anti-corrosion agent material is developed to form the mask of a composition, allow following antireflecting coating, stop definite part exposure with metal layer.By this method, then can pass not the part of the following layer that is covered by photoresist mask with etchant etching.Therefore, Sheng Xia metallization material will form the consistent interconnection line of functional circuit pattern a plurality of and selection.
Figure 1B shows with traditional etch process and finishes, the interconnection line 116 that is formed by the not etching part of the lamination shown in Figure 1A 20.This etch process comprises reactive ion etching (RIE).Interconnection line 116 is that the not etching part by metal layer 106 forms.Used chemicals comprises chlorine (Cl in the reactive ion etching of lamination 20
2) and the chloride (BCl of boron
3).Other etchant chemistry goods in the reactive ion etching of lamination 20 are as HCl, HI, CH
4And/or CHCl
3, also can adopt.
In etching process, except the layer 112,110,106,104 and 102 of vertical etching interconnection line 116, the corrosion of some photoresists can take place also.As a result, the upper surface of photoresist layer 114 may become oblique.Some photo anti-corrosion agent materials that erode may be along sidewall 120 depositions of interconnection line 116, so polymer can the passivation sidewall.
Usually, the passivation of sidewall is normally necessary.For example, known that the passivation of sidewall can help to keep profile control in etching process, and prevented the etched figure of etchant undercutting (undercutting) between other figure.
Yet in the side wall passivation process, the etched material that passes on some etchant (as chlorine) and the etch layer (as the material of interlayer dielectric layer 102 or metal layer 106) can be absorbed into along on the polymer deposition layer of sidewall 102 formation.So,, comprise chlorine (Cl along being full of inorganic and organic material in the polymer deposition layer of sidewall formation
2), silicon dioxide (SiO
2), silicon (Si), carbon (Carbon), titanium (Ti), aluminium (Al) and analog.
After the etching, typically must remove the photoresist mask of covering along any polymer deposition layer on the sidewall 120.Usually, removing of photoresist is by realizing with plasma cleaning (plasma stripping) and water developing technique after etching.In plasma cleaning step, the water vapour and the oxygen that are in plasmoid can be used to remove this photoresist and polymer.Water flushing operation is used for further removing polymer and further dilutes any corrosive gas (as chlorine) that absorbs in the polymer side walls.A problem that is occurred be the inorganic material that absorbs can for remove at follow-up photoresist with the water developing technique in the polymer deposition removed on the sidewall 120 bring difficulty.In other words, successfully remove all basically photoresist mask materials that is capped although photoresist is removed with the water developing technique, existing technology can not successfully be removed the side wall deposition that is full of inorganic material fully.This just needs other operation, as, wet-chemical treatment obtains ideal results.
Figure 1B shows a guardrail 130, and it is still to remain near sidewall 120 side wall deposition materials after being removed by photoresist to form.In flushing process, guardrail 130 may be removed from sidewall 120, and redeposited on the surface of wafer.As known to those those skilled in the art, it is very unfavorable occurring guardrail 130 (being essentially a polymeric tapes that is full of inorganic material) on wafer surface.At least, these guardrails can produce undesirable impurity and cause going out noise in light limit surrender data (PLY data, photo limited yield data).The appearance of guardrail also can cause in subsequent processing steps (as, filling insulating material) or potential integrity problem occurs in the integrated circuit of being produced (IC) operating process.
According to top explanation, needed etching is that easier the cleaning by follow-up plasma of formed side wall deposition layer removed and/or etching that water flushing operation is removed when etching.
The present invention relates to a kind of method that is used for passing in the plasma processing chamber etching the selected part on the lamination in one embodiment, described lamination comprises: a metal layer; One first barrier layer, it is arranged near the described metal layer; With a photoresist layer, it is arranged on described metallization layer, and this method comprises: use high sputter composition to be etched to the small part etching and pass described first barrier layer; Be etched to the small part etching with the low sputter composition of use and pass described metal layer, the etched sputter composition of described low sputter composition is lower than the etched sputter composition of described high sputter composition.
The present invention relates to a kind of method that is used for reducing in plasma processing chamber in the process lateral wall polymer accumulation of the selected part of etching lamination in another embodiment, this lamination comprises: a bottom barrier; One metal layer, it is arranged on the bottom barrier; One top barrier, it is arranged on the metal layer; With a photoresist layer, it is arranged on the metal layer.
This method comprises uses the partially-etched at least top barrier of passing of one first constant pressure.This method comprises that also use one is higher than the partially-etched at least metal layer that passes of second constant pressure of first constant pressure.First constant pressure is that design utilizes the sputter composition etching top barrier higher than the sputter composition of second constant pressure.This method also comprises uses the low partially-etched at least bottom barrier of passing of the 3rd constant pressure of one to the second constant pressure.The 3rd constant pressure is that design utilizes the sputter composition etching higher than the sputter composition of second constant pressure to pass bottom barrier.By reading appended each figure of following detailed description and research, these and other advantage of the present invention will be more obvious.
Connection with figures with reference to following explanation, just can be understood the present invention and advantage thereof best, wherein:
Figure 1A is the sectional view of a lamination, shows each layer that forms in the typical ic manufacturing process;
Figure 1B is the sectional view of the interconnection line that forms in the lamination shown in Figure 1A, comprising some fences, removes and/or during the water flushing, these fences still are kept at original position at photoresist;
Fig. 2 A is the sketch that is suitable for implementing the etch reactor of etching technique of the present invention;
Fig. 2 B is the flow chart of multistep etch process according to an embodiment of the invention;
Fig. 3 is the sectional view that utilizes etching technique etching of the present invention lamination afterwards.
In the following description, in order to understand the present invention better, many concrete details are provided.Yet, clearly do not need some or all these detail can realize the present invention to the people who is familiar with this technology yet.In some occasion, for fear of unnecessary numerous and diverse explanation, some processing steps that are widely known by the people are not introduced in detail.
According to one embodiment of present invention, the invention provides one and improvedly be used for the technology that whole lamination is passed in etching, it uses high sputter composition to be etched to the small part etching and passes the barrier layer.The etching of high sputter composition has advantageously increased the sputter of photoresist layer.The sputter meeting of the photoresist layer of this increase causes other carbon occurring in etch reactor, and is absorbed in the side wall deposition layer.
By increasing the carbon content of side wall deposition layer, the side wall deposition layer becomes more solvable, therefore follow-up photoresist remove and/or water flushing operation process in easier removing.The physical sputtering of this increase has also reduced the physical size of side wall deposition layer, because when more photoresist is sputtered away (for example, when the attenuation of photoresist figure and/or when tilting more, reduce the height 120 among Figure 1B), reduce the sidewall height of etched lamination.
In one embodiment, can with the bias voltage of increase lamination, thereby realize the etching of high sputter composition by reducing the pressure in the etching chamber.Along with operation pressure reduces, the mean free path in the plasma chamber increases, so that be more prone to discharge plasma chamber by the barrier material of sputter, so, reduce them and be adsorbed to degree in the side wall deposition layer.Along with the minimizing that inorganic material absorbs, the side wall deposition layer may be more solvable, and follow-up photoresist remove and/or the water rinsing step in, easier removing.
According to another embodiment of the present invention, the present invention also provides a low sputter composition etching, is used to be etched to the small part metal layer.Because in most of laminations, metal layer is thicker than top barrier usually substantially, like this, helps using low sputter composition etching to come etching to pass whole metal layer, to reduce the photoresist corrosion.If be used for the high sputter composition etching on etching entire top barrier layer, long metallization etching process can cause excessive photoresist to be sputtered away, so, reduced the critical dimension of formed interconnection line.As known to those those skilled in the art, this least wishes to take place, because it can make interconnection line may be subjected to current induced and/or thermoinducible damage in operating process.
In addition, in another embodiment, this method also comprises the etching of high sputter composition, is used for etching and wears the lower curtate barrier layer.Use high sputter that most of photo anti-corrosion agent material is sputtered away, so, the carbon component in the side wall deposition layer increased.If the etching of high sputter composition realizes by reducing etching pressure, just have more low sputtering layer material and drained, so, reduced the content that is absorbed into inorganic matter in the lateral wall polymer.Follow-up photoresist remove and/or water flushing operation in, high and few easier being removed of guardrail of inorganic material that absorb of phosphorus content.
Although etch process of the present invention can be carried out with any suitable etching technique, be to adopt reactive ion etching (RIE) in one embodiment.RIE is to use an inductive couple plasma reactor, is called TCP
TM9600 SE plasma reactors are operated.This plasma reactor can obtain from the Fremont Lam Research Corp. of California, USA.Discuss for convenience, Fig. 2 A shows TCP
TMThe sketch of 9600SE plasma reactor is comprising a wafer 270.With reference to figure 2A, a reactor 250 comprises a plasma treatment chamber 252.On chamber 252, arranged that one produces isoionic source 256, it can make the coil form shown in Fig. 2 A.Coil 256 comes energize by radio frequency (RF) generator 258 by a matching network (not shown) typically.In chamber 252, shower head 254 is arranged, it preferably includes a plurality of holes, and the RF that is used between shower head 254 and wafer 270 induces ion plasma to discharge gaseous source materials (as etchant source gas).
The mouth that gaseous source materials also can form in the wall of chamber 252 discharges.When etching aluminium or a kind of aluminium alloy, the etchant source chemicals comprises for example Cl
2And BCl
3Also can use other chlorine based etchant chemicals.Comprise CH in the example
4, HI, HBr, HCl and CHCl
3, they can use together with any inertia and/or non-active gas.
Wafer 270 is introduced in etching for convenience in chamber 252, place on the chuck 262, and this chuck plays a part one second electrode, preferably provides bias voltage by a radio freqnency generator 264 (also can typically by a matching network).Wafer comprises a plurality of integrated circuits formed thereon.Integrated circuit comprises logical device, as PLA, FPGA and ASIC, or memory device, as random access memory (RAMs, random access memories), dynamic random access memory (DRAMs), Synchronous Dynamic Random Access Memory (SDRAMs) or read-only memory (ROMs).Wafer is cut into pieces when finishing, and each integrated circuit is divided into single chip.After the RF power connection, form product by etchant source gas, with wafer 270 reactions, and the plasma contact layer is passed in etching.The byproduct that may be volatilized falls is discharged through an outlet 266.
Fig. 2 B shows multistep metal etching process 300 according to an embodiment of the invention.In order to simplify discussion, technology 300 is carried out on the lamination shown in Figure 1A, although it must be appreciated that technology of the present invention can carry out on any similar lamination in the manufacture process of IC.For example, it can be carried out on the lamination that top barrier (two top barrier shown in replacement Figure 1A) are only arranged.
In step 302, use high sputter composition to be etched to the small part etching and pass top barrier.Because this first high sputter composition etching is to be used for " penetrating " barrier layer, preferably be called break-through-etch here.In the example of Figure 1A, top barrier comprises first and second top barrier 108 and 110.If the antireflecting coating shown in Figure 1B 112 is organic substances, at first use gas such as N
2, Ar, O
2, CHF
3, CF
4, CH
3F, CO, CO
2, C
4F
8And/or other suitable chemicals to penetrate this antireflecting coating be very useful.
The physical sputtering that increases break-through-etch becomes branch to cause relatively large photo anti-corrosion agent material to be sputtered away.As shown previously, this can reduce the height of polymer guardrail, and for example, it has reduced Figure 1B mid point 124, so reduced the height of guardrail 130.As a result, follow-up photoresist remove and/or the water rinsing step in, the polymeric material of removing is less.
The more important thing is that the increase of photoresist sputter can increase the density of photo anti-corrosion agent material in the reative cell.Therefore, the photoresist of most of sputter is absorbed in the pattern side wall.As known to, the carbon content height of photoresist.So the increase of photo anti-corrosion agent material absorption or absorption has also increased the carbon content of polymer deposition layer in the sidewall.As known to the people who is familiar with this technology, to remove in the step process at follow-up photoresist, the polymer guardrail that carbon content is high is easier to remove.
In one embodiment, high sputter composition break-through-etch is to realize with the bias voltage that increases on the wafer by the pressure that reduces in the plasma processing chamber.Reduce constant pressure and also can obtain an other significant advantage, just reduced the amount that is absorbed into inorganic material in the polymer side walls to obtain the etching of high sputter composition.This is the concentration that meeting increases the mean free path of its inside and/or reduces indoor particle in the break-through-etch process that reduces because of constant pressure.Therefore, the etched barrier material that occurs in the less chamber is absorbed in the polymer side walls.As known to those are familiar with the people of this technology, the minimizing of inorganic material absorption can make the polymer guardrail more solvable, and make the polymer guardrail follow-up photoresist remove and/or the water rinsing step in easier being eliminated.
Yet, it must be noted that to set and realize the etching of high sputter composition by the increase substrate bias power.Increasing bias voltage (or end) power setting is the mechanism that changes the bias voltage of substrate (with etched sputter composition), and it does not rely on foregoing change operation pressure.Therefore, the entire effect to the bias voltage of substrate (with etched sputter composition) depends on one (if using two mechanism in a processing step simultaneously) main in these two mechanism.
In addition, can reduce top (or source) power setting and increase the sputter composition, keep isoionic stability although also will reduce the substrate biasing power setting sometimes.This is another independent mechanism, and it can be used for changing the substrate bias voltage of (with etched sputter composition).In these embodiments, the etched advantage of high sputter composition just reduces the height of polymer guardrail and increases their carbon content, is still advantageously keeping.
If still keep the etching of high sputter composition, come etching to pass whole lamination, just, pass metal layer, etched high sputter becomes branch's excessive erosion protectiveness photoresist mask.When this situation occurring, can influence the critical dimension of interconnection line conversely.Therefore, be preferably in excessive photoresist and be corroded, so that change critical dimension, make it to surpass before the specification error, finish high sputter composition break-through-etch.In one embodiment, by before etching is passed fully, stop the etching of high sputter composition at metal layer.Best, when barrier layer during, finish high sputter composition break-through-etch basically by complete etching.The etching that also must be pointed out metal layer 106 among Figure 1B does not need high sputter etching composition.
For the remainder of lamination is passed in etching, according to one embodiment of present invention, also provide a low sputter composition master etching step here.In this regard, it is exactly with respect to break-through-etch that low sputter composition etching is understood simply, and its sputter composition is lower.Main etching step is shown in the step 304 among Fig. 2 B.
In one embodiment, use low sputter composition etching to come the partially-etched at least metal layer (as, the metal layer 106 among Figure 1A) of wearing.In etching step 304, chemical reaction is main etching mechanism.Because chemical reaction more has alternative than physical sputtering, to compare with the corrosion rate of the photoresist of high sputter composition break-through-etch, the photoresist corrosion rate of photoresist layer 114 has reduced.The minimizing of photoresist corrosion can help to guarantee that enough protectiveness photoresists are retained on the wafer surface, with the critical dimension of protection etched figure (at this moment, just interconnection line).
In one embodiment, can realize low sputter composition etching by increasing operation pressure (with respect to the operation pressure in the break-through-etch process).In decoupling or high-density plasma, the increase of operation pressure typically is converted into the minimizing that photoresist consumes.This can the assurance finished etching with limited photoresist.In addition, in order to keep the desirable profile of interconnection line by realization ion orientation, can increase top power and substrate biasing power setting.
Can continue low sputter composition etching before passing in that lamination is etched always.Yet, in one embodiment, also provide another high sputter composition etching to come etching to pass whole bottom barrier here.In context, it is exactly that its sputter composition is higher with respect to main etched sputter composition that the etching of high sputter composition is understood simply.Can use the used constructed high sputter composition etching that realizes in the break-through-etch step.The etching of high sputter composition has also increased the carbon content of lateral wall polymer deposition and/or has reduced the content of the inorganic material that is absorbed in the lateral wall polymer deposition.This extra high sputter composition etching is shown in step 306 among Fig. 2 B, wherein, uses a high sputter composition etching to come the partially-etched at least bottom barrier of wearing.Sometimes, after lamination is etched with fully, can continue to use the etching of this high sputter composition to obtain etching.
In addition, high sputter composition etching step 306 has advantageously reduced the height of the polymer side walls that generated so that it follow-up photoresist remove and/or the water rinsing step in easier removing.Because the increase of carbon content (if use low operation pressure to obtain the etching of high sputter composition, can reduce the content of inorganic material), the polymer side walls that is generated is more solvable.
Fig. 3 shows and utilizes etching technique of the present invention that lamination shown in Figure 1A 20 is etched into interconnection line 216.Compare with the interconnection line 116 before shown in Figure 1B.Owing to used the etching of high sputter composition, so, the height of sidewall reduced.In other words, compare with the height 120 among Figure 1B, the height 220 among Fig. 3 has reduced.Because carbon content height and/or inorganic material content are low, guardrail 230 is more solvable, in follow-up photoresist removing and/or water developing technique, and easier removing.Following table 1 shows and is suitable at a TCP
TMCarry out the roughly technological parameter of high sputter composition break-through-etch in the 9600SE plasma reactor.In this table, show a roughly suitable scope; The one roughly preferred scope of preferred range and roughly.In each table of back, etching is that the wafer to a 82-300mm carries out.Clearly can change the scope that illustrates to the people who is familiar with this technology and carry out described etching at other etching chamber and/or to other wafer size.
Table 1
| Break-through-etch | ||||||||
| Pressure (mT) | Top power (W) | End power (W) | ??Cl 2(sccm) | HCl | ??N 2(sccm) | Heback ??(T) | Temperature ℃ | |
| Approximate range | ??2-10 | ?75-250 | ??125-250 | ?30-200 | ?10-50 | ??0-25 | ??4-14 | ?20-70 |
| Preferable range roughly | ??5-10 | 120-175 | ??150-225 | ?50-100 | ?15-30 | ??5-20 | ??6-11 | ?30-60 |
| More preferably scope roughly | ??5-7 | 130-160 | ??160-180 | ?90-130 | ?15-25 | ?10-20 | ??8-10 | ?40-50 |
Following table 2 shows and is suitable at TCP
TMCarry out the roughly technological parameter of low sputter composition master etching step in the 9600SE plasma reactor.In this table, show an OK range roughly; One preferable range and more preferably scope roughly roughly.In table 2, increased operation pressure and reduced bias voltage (with etched sputter composition).Although for the bias voltage that is adopted in the table 1 (or end power) was set, the entire effect that shown bias voltage (or end) power has increased substrate bias (with etched sputter composition) had reduced.This fact has been emphasized the separate feature of these two mechanism (substrate bias power is set and operation pressure) of substrate bias (with etched sputter composition).
Table 2
| Main etching | ||||||||
| Pressure (mT) | Top power (W) | End power (W) | ??Cl 2(sccm) | HCl | ??N 2(sccm) | Heback ??(T) | Temperature ℃ | |
| Approximate range | 12-20 | 125-300 | 150-325 | 30-200 | ??10-50 | ??0-25 | ??4-14 | ?20-70 |
| Preferable range roughly | 12-16 | 150-225 | 175-250 | 50-130 | ??15-30 | ??5-20 | ??6-11 | ?30-60 |
| More preferably scope roughly | 12-14 | 185-210 | 190-225 | 90-120 | ??15-25 | ?10-20 | ??8-10 | ?40-50 |
Following table 3 shows at TCP
TMCarry out high sputter composition etching step (be used for the etching bottom barrier and/or be used for etching) in the 9600SE plasma reactor.In this table, show an OK range roughly; One preferable range and more preferably scope roughly roughly.In table 3, reduced operation pressure.To increase bias voltage (with etched sputter composition).Although set with respect to the bias voltage that is adopted in the table 1 (or end power), bias voltage shown in the table (or end) power has reduced, and the entire effect of substrate bias (with etched sputter composition) has been increased.This fact has been emphasized once more to the separate feature of substrate bias these two mechanism of (with etched sputter composition) (substrate bias power is set and operation pressure).
Table 3
| Cross etching | ||||||||
| Pressure (mT) | Top power (W) | End power (W) | ??Cl 2(sccm) | HCl | ??N 2(sccm) | Heback ??(T) | Temperature ℃ | |
| Approximate range | 2-10 | ?75-250 | 125-250 | ?30-200 | ?10-50 | ??0-25 | ??4-14 | ?20-70 |
| Preferable range roughly | 5-10 | 120-175 | 150-225 | ?50-100 | ?15-30 | ??5-20 | ??6-11 | ?30-60 |
| More preferably scope roughly | 5-7 | 130-160 | 160-180 | ??50-85 | ?15-25 | ??10-20 | ??8-10 | ?40-50 |
So far, utilized several exemplary embodiments to introduce the present invention, in category of the present invention, various substituting can also have been arranged, displacement and equivalent.For example, although main reference DRAMS has introduced sidewall accumulation minimizing technology of the present invention here, understand to make things convenient for follow-up discussion and to be convenient to, what must know is that the present invention also not only is confined to this.Wish that the sidewall provided piles up the manufacturing (microprocessor, logic device, memory device and analog) that the minimizing technology need also can be used to any semiconductor device of etching metal layer.It must be noted that method of the present invention and device also have the mode of multiple enforcement.
Below claims be intended to include that in spirit of the present invention and category all substitute, displacement and equivalent.
Claims (21)
1. method that is used for passing the selected part on the lamination in the plasma processing chamber etching, described lamination comprises: a metal layer; One first barrier layer, it is arranged near the described metal layer; With a photoresist layer, it is arranged on described metallization layer, and this method comprises:
Use the etching of high sputter composition, partially-etchedly at least pass described first barrier layer; With
Use low sputter composition etching, partially-etchedly at least pass described metal layer, the etched sputter composition of described low sputter composition is lower than the etched sputter composition of described high sputter composition.
2. the etching of the method for claim 1, wherein using the etching of described high sputter composition to be carried out is to realize than the low etching pressure of the used pressure of low sputter composition etching by adopting.
3. one first bias voltage of the method for claim 1, wherein described substrate in described high sputter composition etching process is higher than one second bias voltage of described substrate in described low sputter composition etching process.
4. the method for claim 1, wherein described metal layer comprises aluminium.
5. the method for claim 1, wherein described first metal layer comprises titanium.
6. the method for claim 1, wherein adopt the chemicals that comprises chlorine in one of the etching of described high sputter composition and the etching of low sputter composition.
7. the method for claim 1 also comprises:
Use another high sputter composition to be etched to the small part etching and pass the bottom barrier that is different from described first barrier layer, described first barrier layer places on the described metal layer, described bottom barrier places under the described metal layer, the sputter composition height that the etched sputter composition of described another high sputter composition is adopted than the etching of described low sputter composition.
8. method as claimed in claim 7, wherein, described metal layer comprises Al-Cu.
9. etching of the method for claim 1, wherein described high sputter composition and the etching of low sputter composition one of at least are to adopt reactive ion etching.
10. the method for claim 1, wherein described lamination is used for the dynamic random access memory manufacturing.
11. one kind is used for passing the method that reduces lateral wall polymer foundation on the lamination in the selected process partly in the plasma processing chamber etching, described lamination comprises: a metal layer; One first barrier layer, it is arranged near the described metal layer; With a photoresist layer, it is arranged on the described metal layer, and this method comprises:
Use that one first constant pressure is partially-etched at least to pass described first barrier layer;
Use that second constant pressure higher than described first constant pressure is partially-etched at least to pass described metal layer, wherein, described first constant pressure is that design utilizes a sputter higher than the used sputter composition of described second constant pressure described first barrier layer of etching that becomes to assign to.
12. method as claimed in claim 11, wherein, described lamination is used for the dynamic random access memory manufacturing.
13. method as claimed in claim 11 also comprises:
Use three constant pressure at least partially-etched the pass bottom barrier that be different from described first barrier layer lower than described second constant pressure, described first barrier layer places on the described metal layer, described bottom barrier places under the described metal layer, wherein, described second constant pressure is that design utilizes one than the high sputter of the used sputter composition of the described second constant pressure described bottom barrier of etching that becomes to assign to.
14. method as claimed in claim 13, wherein, at least one comprises Ti in the middle of described first barrier layer and the described bottom barrier, and described metal layer comprises aluminium.
15. method as claimed in claim 14, wherein, described lamination is used for the dynamic random access memory manufacturing.
16. method as claimed in claim 14, wherein, chloride chemicals is adopted in described partially-etched at least etching of passing described metal layer.
17. method as claimed in claim 16, wherein, described partially-etched at least etching of passing described metal layer comprises reactive ion etching.
18. method as claimed in claim 13, wherein, described first constant pressure is between 2 milli torrs and 10 milli torrs.
19. method as claimed in claim 18, wherein, described second constant pressure is between 12 milli torrs and 20 milli torrs.
20. one kind is used for passing the method that reduces lateral wall polymer foundation on the lamination in the selected process partly in the plasma processing chamber etching, described lamination comprises: a metal layer; One first barrier layer, it is arranged near the described metal layer; With a photoresist layer, it is arranged on the described metal layer, and this method comprises:
Use that one first constant pressure is partially-etched at least to pass described first barrier layer;
Use that second constant pressure higher than described first constant pressure is partially-etched at least to pass described metal layer, wherein, described first constant pressure is that design utilizes a sputter higher than the used sputter composition of described second constant pressure described first barrier layer of etching that becomes to assign to;
Use that one three constant pressure lower than described second constant pressure is partially-etched at least to pass described bottom barrier, wherein, described the 3rd constant pressure is that design utilizes one to come the described bottom barrier of etching than the high sputter composition of the used sputter composition of described the 3rd constant pressure.
21. method as claimed in claim 20, wherein, described lamination is used for the dynamic random access memory manufacturing.
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|---|---|---|---|
| CN 98114980 CN1204864A (en) | 1997-06-20 | 1998-06-18 | Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing |
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|---|---|---|---|
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| CN 98114980 CN1204864A (en) | 1997-06-20 | 1998-06-18 | Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8393073B2 (en) | 2005-01-14 | 2013-03-12 | HGST Netherlands B.V. | Method to control mask profile for read sensor definition |
| CN109148264A (en) * | 2018-08-08 | 2019-01-04 | 上海华力微电子有限公司 | A method of reducing residual polyalcohol based on etching machine bench prevents aluminium from corroding |
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1998
- 1998-06-18 CN CN 98114980 patent/CN1204864A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8393073B2 (en) | 2005-01-14 | 2013-03-12 | HGST Netherlands B.V. | Method to control mask profile for read sensor definition |
| CN109148264A (en) * | 2018-08-08 | 2019-01-04 | 上海华力微电子有限公司 | A method of reducing residual polyalcohol based on etching machine bench prevents aluminium from corroding |
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