CN1204688C - Input/output circuit capable of allowing variable voltage - Google Patents
Input/output circuit capable of allowing variable voltage Download PDFInfo
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- CN1204688C CN1204688C CN 01143732 CN01143732A CN1204688C CN 1204688 C CN1204688 C CN 1204688C CN 01143732 CN01143732 CN 01143732 CN 01143732 A CN01143732 A CN 01143732A CN 1204688 C CN1204688 C CN 1204688C
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- coupled
- voltage
- electrode
- pmos
- nmos pass
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Abstract
The present invention relates to an input/output circuit allowing variable voltage, which has the advantage that leakage currents can not be generated, and the input/output circuit has high reliability. The circuit is mainly characterized in that the circuit has a clamp circuit for restraining the electric potential of N-Well of M1. If power supply voltage V#-<CC> is higher than or is equal to voltage V#-<I/O> on the end of the Input/output circuit, the electric potential of N-Well of M1 is restrained to the power supply voltage V#-<CC>. If the power supply voltage V#-<CC> is less than the voltage V#-<I/O> on the end of the Input/output circuit, the electric potential of N-Well of M1 is restrained to the voltage V#-<I/O> on the end of the Input/output circuit.
Description
Technical field
The present invention relates to a kind of input/output circuitry of energy allowing variable voltage, particularly a kind of input/output circuitry that can not produce the energy allowing variable voltage of leakage current.
Background technology
Because the result of the continuous minimization of advanced ic manufacturing technology for keeping the stable electronic circuit operating characteristic reliably of integrated circuit, must constantly reduce the supply voltage value in the one chip (supplyvoltage).So not only power consumption reduces, and circuit speed also thereby improve.Certainly some type products is subject to existing manufacturing technology and still need works in the high voltage scope, thus, can cause on the same printed circuit board (PCB) (Printed Circuit Board), the shared identical data/address bus of different integrated circuits (Data Bus), but use different supply voltage values.If data/address bus voltage is produced by the integrated circuit of high power supply voltage and is excessive with the integrated circuit magnitude of voltage difference of low supply voltage, can cause the bus data voltage distortion, and make the integrated circuit power consumption excessive, thereby can't normally bring into play function or operation.
Figure 1 shows that a kind of input/output circuitry of known single voltage source, it comprises PMOS transistor M1, M3, M5 and nmos pass transistor M2, M4, M6.Gate coupled to the one input control signal PU of M3, M4 wherein; The gate coupled of M5, M6 is to another input control signal PD; Drain coupled to one output circuit of M2 (output circuit); Its drain electrode of M1 is coupled to this output circuit by electrode, and the source electrode of M1 then is coupled to supply voltage V by electrode
CCThe source electrode of M3, M5 also is coupled to supply voltage V
CCThe source-coupled of M2, M4, M6 is to earthed voltage V
SSThe drain coupled of M3, M4 is to the grid of M1; The drain coupled of M5, M6 is to the grid of M2.
Below be divided into two kinds of situations the problem of leakage current in the known input/output circuitry shown in Figure 1 be discussed:
(1) as the voltage V of input/output circuitry end (Input/Output circuit)
I/OThe voltage of logic high state (logic high) be lower than supply voltage V
CC(V for example
I/O=3V, V
CC=5V) and M1, when M2 is not on-state, the voltage of the N-Well of M1 is V
CCBecause the voltage of I/O end is lower than the voltage of the N-Well of M1, so do not have forward diode leakage current (forward diode leakage current) existence between the drain electrode of M1 and the N-Well.
(2) as the voltage V of input/output circuitry end
I/OThe voltage of logic high state (logic high) be higher than supply voltage V
CC(V for example
I/O=5V, V
CC=3V), and M1, when M2 is not on-state, the voltage of the N-Well of M1 is V
CCThis will make has the forward diode leakage current to exist between the drain electrode of M1 and the N-Well, as shown in Figure 2.This leakage phenomenon can seriously influence the normal running of M1.
In other words, as the voltage V of input/output circuitry end shown in Figure 1
I/OThe voltage of logic high state (logichigh) be higher than supply voltage V
CCThe time, the problem of leakage current is unavoidable.Leakage current can further cause heat radiation difficulty, and is more obvious when especially huge and data voltage and supply voltage difference are big when the data/address bus number.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of input/output circuitry that can not produce the energy allowing variable voltage of leakage current.
Another object of the present invention is to provide a kind of high-reliability can allowing variable voltage input/output circuitry.
For achieving the above object, the input/output circuitry of a kind of energy allowing variable voltage of the present invention comprises: a supply voltage; One earthed voltage; One the one PMOS transistor, its drain electrode is coupled to this supply voltage by electrode, and its source electrode then is coupled to an output circuit by electrode; One the 2nd PMOS transistor, its source electrode is coupled to the transistorized N-Well of a PMOS by electrode, and its drain electrode then is coupled to the transistorized grid of a PMOS by electrode, and transistorized gate coupled to an input control circuit of the 2nd PMOS; One the 3rd PMOS transistor, its source-coupled are to this supply voltage, and its gate coupled is to another input control circuit; One first nmos pass transistor, its drain coupled are to this output circuit, and its source-coupled is to this earthed voltage, and its gate coupled is to the 3rd PMOS transistor drain; One second nmos pass transistor, its drain coupled are to the transistorized grid of a PMOS, and its source-coupled is to this earthed voltage, and the transistorized grid of its gate coupled to the two PMOS; One the 3rd nmos pass transistor, its drain coupled are to the grid of this first nmos pass transistor, and its source-coupled is to this earthed voltage, and the transistorized grid of its gate coupled to the three PMOS; And a clamp circuit, have: one the 4th PMOS transistor, its gate coupled are to the transistorized N-Well of a PMOS, and its drain electrode is coupled to this supply voltage by electrode, and its source electrode then is coupled to the transistorized N-Well of a PMOS by electrode; And one the 5th PMOS transistor, its gate coupled is to the transistorized N-Well of a PMOS, and the 5th its source electrode of PMOS transistor is coupled to the transistorized N-Well of a PMOS by electrode, and its drain electrode then is coupled to this output circuit by electrode.
The input/output circuitry of this energy allowing variable voltage, more comprise: one first protective circuit, it is in order to the current potential of the drain electrode that limits this first nmos pass transistor, make that potential difference can not cause this first nmos pass transistor voltage collapse between the source electrode of this first nmos pass transistor and the drain electrode, and can reduce the passageway shuts off leakage current of this first nmos pass transistor again; Wherein this first protective circuit comprises: one the 4th nmos pass transistor, its drain coupled are to this output circuit, and its source-coupled is to the drain electrode of this first nmos pass transistor; One the 6th PMOS transistor, its source-coupled are to supply voltage, and its gate coupled is to earthed voltage, and its drain coupled is to the grid of the 4th nmos pass transistor; And one second protective circuit; it is in order to the current potential of the drain electrode that limits this second nmos pass transistor; make this second nmos pass transistor source electrode and the drain electrode between potential difference can not cause this second nmos pass transistor voltage collapse; and can reduce the passageway shuts off leakage current of second nmos pass transistor again; this second protective circuit comprises: one the 5th nmos pass transistor; its drain coupled is to the transistorized grid of a PMOS; its gate coupled is to this supply voltage, and its source-coupled is to the drain electrode of this second nmos pass transistor.
Design of I by energy allowing variable voltage provided by the present invention, can guarantee bus data voltage not can because of with the excessive and distortion of integrated circuit magnitude of voltage difference, therefore and power consumption is excessive overcome integrated circuit simultaneously, cause the problem that normally to bring into play function or operation.
Description of drawings
Fig. 1 is the circuit diagram of known input/output circuitry;
Fig. 2 is the transistorized structure chart of PMOS;
Fig. 3 is the circuit diagram of first preferred embodiment of input/output circuitry that can allowing variable voltage of the present invention;
Fig. 4 is the circuit diagram of second preferred embodiment of input/output circuitry that can allowing variable voltage of the present invention.
Embodiment
As shown in Figure 3, first preferred embodiment of the input/output circuitry of energy allowing variable voltage of the present invention comprises: supply voltage V
CC, earthed voltage V
SS, a PMOS transistor M1, the 2nd PMOS transistor M3, the 3rd PMOS transistor M5, the 4th PMOS transistor M7, the 5th PMOS transistor M8, the first nmos pass transistor M2, the second nmos pass transistor M4, the 3rd nmos pass transistor M6.
Wherein, M7 and M8 constitute the current potential of a clamp circuit (clamping circuit) in order to the N-Well of strangulation M1; If supply voltage V
CCBe greater than or equal to the voltage V of input/output circuitry end
I/O, then the current potential of the N-Well of M1 by strangulation to supply voltage V
CCIf supply voltage V
CCBe lower than the voltage V of input/output circuitry end
I/O, then the current potential of the N-Well of M1 is by the voltage V of strangulation to the input/output circuitry end
I/O
M1 drain electrode wherein is coupled to output circuit by electrode, and the source electrode of M1 then is coupled to supply voltage V by electrode
CCThe drain coupled of M2 is to output circuit, and the source-coupled of M2 is to earthed voltage V
SSM3 source electrode wherein is coupled to the N-Well of M1 by electrode; The drain electrode of M3 then is coupled to the grid of M1 by electrode, the gate coupled of M3 is to input control signal PU; The drain coupled of M4 is to the grid of M1, and the source-coupled of M4 is to earthed voltage V
SS, the gate coupled of M4 is to input control signal PU; The source-coupled of M5 is to supply voltage V
CC, the drain coupled of M5 is to the grid of M2, and the gate coupled of M5 is to input control signal PD; The drain coupled of M6 is to the grid of M2, and the source-coupled of M6 is to earthed voltage V
SS, the gate coupled of M6 is to input control signal PD; M7 drain electrode wherein is coupled to supply voltage V by electrode
CC, the source electrode of M7 then is coupled to the N-Well of M1 by electrode, and the gate coupled of M7 is to the N-Well of M1; M8 drain electrode wherein is coupled to output circuit by electrode, and the source electrode of M8 then is coupled to the N-Well of M1 by electrode, and the gate coupled of M8 is to the N-Well of M1.
Below be divided into two kinds of situations and discuss whether there is leakage current in the input/output circuitry of the present invention shown in Figure 3:
(1) as the voltage V of input/output circuitry end
I/OThe voltage of logic high state be lower than supply voltage V
CC(V for example
I/O=3V, V
CC=5V), and M1, when M2 is not on-state because the effect of clamp circuit M7, M8, the voltage of node N1 is VCC.In this case, the voltage of the N-Well of M1 by strangulation to V
CC, the voltage of the drain electrode of M1 is V
I/O=3V does not exist so do not have the forward diode leakage current between the N-Well of M1 and the drain electrode P+.In addition, the source voltage of M3 also by strangulation to V
CC, M3 is a conducting state, the voltage of node N3 thereby quilt are drawn high to V
CC, in other words, the grid voltage of M1 is V
CC, the source voltage of M1 is V
CC, the drain voltage of M1 is V
I/OSo the passageway shuts off leakage current of M1 (ChannelCut-Off Leakage Current) can neglect.
(2) as the voltage V of input/output circuitry end
I/OThe voltage of logic high state be higher than supply voltage V
CC(V for example
I/O=5V, V
CC=3V), and M1, when M2 is not on-state because the effect of clamp circuit M7, M8, the voltage of node N1 is V
I/O, the voltage of the N-Well of M1 by strangulation to V
I/O, the voltage of the drain electrode of M1 also is V
I/OBecause the voltage of the N-Well of M1 is not less than the source electrode of M1 and the voltage of drain electrode, so do not have the existence of forward diode leakage current between the N-Well of M1 and the drain electrode.In addition, the source voltage of M3 also by strangulation to V
I/O, M3 is a conducting state, the voltage of node N3 thereby quilt are drawn high to V
I/O, in other words, the grid voltage of M1 is V
I/O, the source voltage of M1 is V
CC, the drain voltage of M1 is V
I/OSo the passageway shuts off leakage current of M1 can neglect.
According to above analysis, in the input/output circuitry of the present invention shown in Figure 3, voltage V no matter
I/OThe voltage of logic high state (logic high) be higher or lower than supply voltage V
CC, the problem of leakage current all can not take place.
The present invention is except effectively solving the problem of leakage current by clamp circuit, and can be further destroyed to prevent circuit element by protective circuit (protection circuit), and mat and a kind of input/output circuitry of high-reliability is provided is described as follows:
As shown in Figure 4; second preferred embodiment of the input/output circuitry of energy allowing variable voltage of the present invention is compared with first preferred embodiment; two holding circuits have been increased; first protective circuit is made of nmos pass transistor M9 and PMOS transistor M10; the current potential of drain electrode in order to restriction M2 makes the source electrode of M2 and the potential difference of drain electrode can not cause M2 voltage collapse (Voltage AvalancheBreakdown) or cause hot carrier (Hot Carrier) integrity problem.Second protective circuit is made of nmos pass transistor Mll, and it makes the source electrode of M4 and the potential difference of drain electrode can not cause the M4 voltage collapse or cause hot carrier integrity problem in order to the current potential of the drain electrode of restriction M4.
The specific embodiment that is proposed in invention description is only in order to be easy to illustrate technology contents of the present invention, and be not with narrow sense of the present invention be limited to this embodiment, so, can make many variations according to disclosed technology contents and implement in the situation that does not exceed spirit of the present invention and following claim.
Claims (2)
1. the input/output circuitry of an energy allowing variable voltage comprises:
One supply voltage;
One earthed voltage;
One the one PMOS transistor, its drain electrode is coupled to this supply voltage by electrode, and its source electrode then is coupled to an output circuit by electrode;
One the 2nd PMOS transistor, its source electrode is coupled to the transistorized N-Well of a PMOS by electrode, and its drain electrode then is coupled to the transistorized grid of a PMOS by electrode, and transistorized gate coupled to an input control circuit of the 2nd PMOS;
One the 3rd PMOS transistor, its source-coupled are to this supply voltage, and its gate coupled is to another input control circuit;
One first nmos pass transistor, its drain coupled are to this output circuit, and its source-coupled is to this earthed voltage, and its gate coupled is to the 3rd PMOS transistor drain;
One second nmos pass transistor, its drain coupled are to the transistorized grid of a PMOS, and its source-coupled is to this earthed voltage, and the transistorized grid of its gate coupled to the two PMOS;
One the 3rd nmos pass transistor, its drain coupled are to the grid of this first nmos pass transistor, and its source-coupled is to this earthed voltage, and the transistorized grid of its gate coupled to the three PMOS; And
One clamp circuit has:
One the 4th PMOS transistor, its gate coupled are to the transistorized N-Well of a PMOS, and its drain electrode is coupled to this supply voltage by electrode, and its source electrode then is coupled to the transistorized N-Well of a PMOS by electrode; And
One the 5th PMOS transistor, its gate coupled are to the transistorized N-Well of a PMOS, and the 5th its source electrode of PMOS transistor is coupled to the transistorized N-Well of a PMOS by electrode, and its drain electrode then is coupled to this output circuit by electrode.
2. the input/output circuitry of energy allowing variable voltage as claimed in claim 1 more comprises:
One first protective circuit, it is in order to the current potential of the drain electrode that limits this first nmos pass transistor, make that potential difference can not cause this first nmos pass transistor voltage collapse between the source electrode of this first nmos pass transistor and the drain electrode, and can reduce the passageway shuts off leakage current of this first nmos pass transistor again; Wherein this first protective circuit comprises:
One the 4th nmos pass transistor, its drain coupled are to this output circuit, and its source-coupled is to the drain electrode of this first nmos pass transistor;
One the 6th PMOS transistor, its source-coupled are to supply voltage, and its gate coupled is to earthed voltage, and its drain coupled is to the grid of the 4th nmos pass transistor; And
One second protective circuit; it is in order to the current potential of the drain electrode that limits this second nmos pass transistor; make that potential difference can not cause this second nmos pass transistor voltage collapse between the source electrode of this second nmos pass transistor and the drain electrode, and can reduce the passageway shuts off leakage current of second nmos pass transistor again
This second protective circuit comprises:
One the 5th nmos pass transistor, its drain coupled are to the transistorized grid of a PMOS, and its gate coupled is to this supply voltage, and its source-coupled is to the drain electrode of this second nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01143732 CN1204688C (en) | 2001-12-19 | 2001-12-19 | Input/output circuit capable of allowing variable voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01143732 CN1204688C (en) | 2001-12-19 | 2001-12-19 | Input/output circuit capable of allowing variable voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1427546A CN1427546A (en) | 2003-07-02 |
| CN1204688C true CN1204688C (en) | 2005-06-01 |
Family
ID=4677235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01143732 Expired - Fee Related CN1204688C (en) | 2001-12-19 | 2001-12-19 | Input/output circuit capable of allowing variable voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1204688C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7986171B2 (en) * | 2008-10-21 | 2011-07-26 | Himax Technologies Limited | Mixed-voltage I/O buffer |
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2001
- 2001-12-19 CN CN 01143732 patent/CN1204688C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1427546A (en) | 2003-07-02 |
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