CN1195224A - Bias circuit for FET amplifier - Google Patents

Abstract

A first PNP transistor Q2 is provided between the drain and gate of a source grounded field-effect transistor(FET)Q1 for automatically maintaining the inter-drain and source voltage and drain currents of the FETQ1 to be constant against the fluctuation of a DC parameter in the DC bias circuit of the FETQ1. The bias circuit including a second PNP transistor Q3 is connected with the base of this Q2. The Q2 and Q3 have equivalent characteristics so that the fluctuation of the drain voltage and the drain currents due to the temperature fluctuation of the inter-emitter and base voltage of the Q2 can be compensated, and the drain currents can be prevented from largely fluctuating.

Description

The bias circuit that is used for field effect transistor (FET) amplifier

The present invention relates to be used for the bias circuit of field-effect transistor (FET), and to relate in particular to the drain current in order to the maintaining field effect transistor that is used for the field-effect transistor microwave amplifier be the bias circuit of steady state value.

For example, in the flat 3-11682 of Japanese Patent Application Publication, disclose a kind of this type of and be used for the conventional bias circuit of field effect transistor (FET) amplifier.Even the conventional bias circuit that is disclosed is used to when making the dc parameter of field-effect transistor change for a certain reason also the drain-source voltage of maintaining field effect transistor automatically, and therefore makes its drain current all be in steady state value.Fig. 7 is the disclosed circuit diagram that is used for the conventional bias circuit of field effect transistor (FET) amplifier.Be used for the ground connection source electrode type field-effect transistor Q shown in Fig. 7 ₁Direct-flow biasing circuit in, FETQ ₁Gate electrode pass through resistance R ₂Link to each other with negative supply VGG and drain electrode wherein passes through resistance R ₁VDD links to each other with positive supply.PNP bipolar transistor Q ₂Collector electrode be positioned at FETQ ₁Gate electrode and resistance R ₂Between knot link to each other and PNP bipolar transistor Q ₂Emitter be positioned at FETQ ₁Drain electrode and resistance R ₁Between knot link to each other.In addition, the base electrode of PNP bipolar transistor passes through resistance R ₆Link to each other with positive supply VDD and pass through resistance R ₇Ground connection.This bias circuit is characterised in that its work is used to compensate the FETQ that the variation owing to the dc parameter of FET causes ₁Drain current and the variation of the drain-source voltage that therefore causes.

In addition, according to above-mentioned circuit structure, can be automatically drain-source voltage and the drain current of FET be maintained each steady state value place.

Describe the aforesaid operations of the bias circuit shown in Fig. 7 below in detail.Bias circuit is by FETQ ₁, PNP bipolar transistor Q ₂, and resistance R ₁, R ₂, R ₆, and R ₇Form.Resistance R ₁Value be chosen such that promptly when predetermined drain current flow through FET, drain-source voltage became predetermined value and resistance R ₆And R ₇Determined to be provided to PNP bipolar transistor Q ₂The reference voltage of base stage.Determined reference voltage should be lower than drain-source voltage, makes its difference corresponding with base stage-emitter voltage.Resistance R ₂Value select like this, promptly as PNP bipolar transistor Q ₂Collector current when flowing through, be provided for FETQ with the corresponding voltage of the variation of collector current ₁Gate electrode.

Suppose FETQ for a certain reason ₁Dc parameter change and drain current also correspondingly is reduced, pass through resistance R ₁Voltage drop also reduce and therefore make FETQ owing to the reduction of drain current ₁Drain-source voltage raise.Then, the base stage-emitter voltage of PNP bipolar transistor is raised, base current be raised and therefore collector current also raise.Because pass through resistance R because the rising of collector current makes ₂Voltage drop bigger, therefore be provided for FETQ ₁The voltage of grid also be that gate source voltage is lowered.Therefore, drain current is raised and drain current and drain-source voltage are maintained constant thus.

In above-mentioned routine techniques, PNP transistor Q ₂Emitter-to-base voltage change with variation of temperature, therefore, FETQ ₁Drain voltage corresponding with the variation of temperature value with the changing value of emitter-to-base voltage.Drain current depends on drain voltage and is provided for resistance R ₁Forward supply voltage VDD between difference.Therefore, when drain voltage being set near the positive source of forward voltage VDD, be added in resistance R ₁The voltage decreases at two ends and drain voltage change become greatly the influence that drain current changes.Its result, drain current can change intensely.Therefore, work as FETQ ₁Drain voltage when being set near positive voltage VDD, for example be set under the lower situation at positive voltage VDD, can not keep constant drain current.

An object of the present invention is to provide a kind of bias circuit of FET amplifier, even the drain voltage of FET is set near the voltage of positive voltage of amplifier so, also can be by it to prevent because the changing of essence of the drain current of the FET of the amplifier that variations in temperature causes.

According to the present invention, the bias circuit of earthing power supply type FET amplifier is characterised in that the first transistor is connected between the drain electrode and gate electrode of FET; And transistor seconds is linked to each other with drain resistance and the first transistor of FET.

In addition, the base stage of transistor seconds directly links to each other with emitter.

Bias circuit according to the present invention is characterized in that the emitter-to-base voltage characteristic of the first transistor, and the emitter-to-base voltage characteristic with transistor seconds is identical basically.

In addition, when FET is the N channel junction first and second transistors be the PNP transistor when working as FET and being the P channel junction first and second transistors be NPN transistor.

In addition, bias circuit of the present invention is characterised in that the device that also comprises the base voltage that is used to regulate the first transistor.

In bias circuit according to the present invention, also be PNP transistor Q ₂Provide in the bias circuit part in the bias circuit of base potential, a PNP transistor Q is set in addition ₃, its have a base stage and a collector electrode that directly links to each other with base stage and with PNP transistor Q ₂Has same type.As PNP transistor Q ₂Emitter-to-base voltage vary with temperature and when changing PNP transistor Q ₃Emitter-to-base voltage similarly with PNP transistor Q ₂Emitter-to-base voltage variation and change, thereby the base potential of PNP transistor Q2 also changes.Therefore, TETQ ₁Even drain voltage become constant basically and when drain voltage is set near positive voltage VDD of FET amplifier drain current also maintain steady state value.

Fig. 1 is the circuit diagram of bias circuit of the FET amplifier of first embodiment according to the invention;

Fig. 2 is the schematic diagram of voltage one temperature characterisitic that the various piece of the bias circuit shown in Fig. 1 is shown;

Fig. 3 is the schematic diagram of drain current-temperature characterisitic that the FET of the bias circuit among Fig. 1 is shown;

Fig. 4 is the schematic diagram that concerns according between the temperature of the rate of change of the drain current of FET compared with prior art of the present invention and FET and drain voltage;

Fig. 5 is the circuit diagram according to the bias circuit that is used for FET of second embodiment of the invention;

Fig. 6 is the circuit diagram according to the bias circuit that is used for FET of third embodiment of the invention; And

Fig. 7 is the conventional circuit diagram that is used for the bias circuit of FET amplifier.

Below with reference to accompanying drawing most preferred embodiment of the present invention is described.

Fig. 1 is the circuit diagram according to the bias circuit of the FET amplifier of first embodiment of the invention.In Fig. 1, ground connection source electrode type FETQ ₁Direct-flow biasing circuit comprise a PNP transistor Q2 and a PNP transistor Q ₃, transistor Q wherein ₂Have one and FETQ ₁The emitter that links to each other of drain electrode with and pass through resistance R ₁VDD links to each other with positive supply, and PNP transistor Q ₂Have one and FETQ ₁The collector electrode that links to each other of grid and its pass through resistance R ₂VGG links to each other with negative supply, in addition PNP transistor Q wherein ₃Have an emitter that links to each other with positive supply VDD, base stage and a collector electrode that directly links to each other, and base stage and collector electrode pass through resistance R with base stage ₃With PNP transistor Q ₂Base stage link to each other and pass through resistance R ₄Link to each other with ground.

Describe the operation of the bias circuit shown in Fig. 1 in detail below with reference to Fig. 2.

In Fig. 2, VE ₂Expression PNP transistor Q ₂Emitter electromotive force, VB ₂Expression base potential, VEB ₂Expression emitter-to-base voltage, △ VEB ₂Variation, the VEB of the emitter-to-base voltage that the expression temperature causes ₃Expression PNP transistor Q ₃Emitter-to-base voltage, △ VEB ₃The P transistor Q that the expression temperature causes ₃The variation of emitter-to-base voltage and the magnitude of voltage that VDD represents positive supply VDD.In order to simplify mathematical operation, PNP transistor Q ₁And Q ₃Base current be assumed to be little to ignoring.

The value of resistance R 1 is to determine like this, when predetermined drain current ID flows through, and FETQ ₁Drain voltage VD become predetermined value according to following equation (1) $\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}1=\frac{\mathrm{VDD}-\mathrm{VD}}{\mathrm{ID}}---\left(1\right)$

When under near the situation voltage VDD that drain voltage VD is set in positive supply, resistance R ₁Value be set in the scope from several ohm to hundreds of ohm.

PNP transistor Q ₂Collector current IC ₂Flow through resistance R ₂And will offer FETQ according to following equation (2) with the corresponding voltage of the variation of collector current IC2 ₁Grid: $\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}2=\frac{\mathrm{VGG}-\mathrm{<figure-callout\; id="4"\; label="V"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">V</figure-callout>}4}{\mathrm{IC}2}---\left(2\right)$

Because collector current IC ₂At FETQ ₁Drain current ID must be set enough for a short time, so the value of resistance R 2 just should be selected in the scope from several kilohms to hundreds of kilo-ohm.Resistance R ₃And R ₄Determined PNP transistor Q ₂Base potential VB ₂And base potential VB ₂Numerical value just than FETQ ₁The magnitude of voltage of the low emitter-base stage of drain voltage VD value.In the case, PNP transistor Q ₃Collector current be set to and be substantially equal to PNP transistor Q ₂Collector current IC ₂Resistance R ₃Number range be to several kilohms and resistance R from hundreds of ohm ₄Number range from several kilohms to the hundreds of kilohm.By using voltage VDD and the PNP transistor Q with positive supply ₃Emitter-to-base voltage (VEB ₃+ △ VEB ₃) between poor corresponding position resistance R ₃And R ₄After carrying out dividing potential drop, obtain PNP transistor Q ₂Base potential VB ₂, and represent with following equation (3): $\mathrm{<figure-callout\; id="2"\; label="VB"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">VB</figure-callout>}2=\frac{R4}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}4}\&times;\{\mathrm{VDD}-(\mathrm{VEB}3+\mathrm{\&Delta;VEB}3)\}---\left(3\right)$

Use the curve VB among Fig. 2 in the case ₂Expression PNP transistor Q ₂The change that produces with variation of temperature of base potential.

FETQ ₁Drain voltage VD be PNP transistor Q ₂Base potential VB ₂With PNP transistor Q ₂Emitter-to-base voltage (VEB ₂+ △ VEB ₂) and and represent with following formula (4):

VD=VB ₂+ (VEB ₂+ △ VEB ₂) ... (4), can obtain following formula (5) from formula (3) and (4): $\mathrm{VD}=\frac{R4}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}4}\&CenterDot;\mathrm{VDD}+\{\mathrm{VEB}2+\mathrm{\&Delta;VEB}2-\frac{R4}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}4}\&CenterDot;(\mathrm{VEB}3+\mathrm{\&Delta;VEB}3)\}---\left(5\right)$ In order to understand formula (5), at hypothesis PNP transistor Q ₂And Q ₃Basically being similar product and having under the much the same situation that can cause the temperature that emitter-to-base voltage changes, also is VEB ₂ VEB ₃And △ VEB ₂ △ VEB ₃, formula (5) also can be reduced to the formula (6) of back.In the case, among Fig. 2 VEB has been shown ₂+ △ VEB ₂And VEB ₃+ △ VEB ₃ $\mathrm{VD}=\frac{R4}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+R4}\&CenterDot;\mathrm{VDD}+\frac{R3}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}4}\&CenterDot;(\mathrm{VEB}2+\mathrm{\&Delta;VEB}2)---\left(6\right)$ Be clear that very that from formula (6) because first of the right of formula (6) is big more a lot of than second, therefore drain voltage VD is roughly constant under the situation of not considering variations in temperature.

Curve VD among Fig. 2 shows this situation.

By using formula (6) to △ VEB ₂Differential can obtain following equation, it has represented to cause PNP transistor Q ₂The temperature that changes of emitter-to-base voltage to the influence of drain voltage VD. $\frac{\mathrm{\&Delta;VD}}{\mathrm{\&Delta;VEB}2}=\frac{R3}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+R4}---\left(7\right)$

On the other hand, according to the bias circuit of prior art, by 7 couples of resistance (R of following resistance R ₆+ R ₇) can provide the transistorized base potential VB ' of PNP with ratio: $V{B}^{\&prime;}=\frac{R7}{R6+R7}\&CenterDot;\mathrm{VDD}---\left(8\right)$

Because FETQ ₁Drain voltage VD ' be base potential VB ₂' and emitter-to-base voltage (VEB ₂+ △ VEB ₂) and, can represent by following equation (9): $V{D}^{\&prime;}=\frac{R7}{R6+R7}\&CenterDot;\mathrm{VDD}+(\mathrm{VEB}2+\mathrm{\&Delta;VEB}2)---\left(9\right)$ By equation (9) to △ VEB ₂Differential, can obtain following equation: $\frac{\mathrm{\&Delta;V}{D}^{\&prime;}}{\mathrm{\&Delta;<figure-callout\; id="2"\; label="VEB"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">VEB</figure-callout>}2}=1---\left(10\right)$

Equation (7) and equation (10) are compared, clearly, in bias circuit according to the present invention, compare, cause PNP transistor Q with situation of the prior art ₂The temperature that changes of emitter-to-base voltage to FETQ ₁The influence of drain voltage be limited to R ₃/ (R ₃+ R ₄).

In addition. can obtain to flow through FETQ by following equation (11) ₁Drain current ID: $\mathrm{ID}=\frac{\mathrm{VDD}-\mathrm{VD}}{R1}---\left(11\right)$ By equation (6) and (11), can obtain following equation: $\mathrm{ID}=\frac{1}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}1}\&CenterDot;\frac{R3}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}4}\&CenterDot;\{\mathrm{VDD}-(\mathrm{VEB}2+\mathrm{\&Delta;VEB}2)\}---\left(12\right)$

By obtaining following equation with equation (12) to △ VEB2 differential, it has represented to cause PNP transistor Q ₂The temperature of variation of emitter-to-base voltage to the influence of drain current: $\frac{\mathrm{\&Delta;ID}}{\mathrm{\&Delta;<figure-callout\; id="2"\; label="VEB"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">VEB</figure-callout>}2}=\frac{-1}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}1}\&CenterDot;\frac{R3}{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}3+R4}---\left(13\right)$ Similarly, the drain current ID that flows through the prior art bias circuit becomes as follows: $I{D}^{\&prime;}=\frac{\mathrm{VDD}-V{D}^{\&prime;}}{R1}---\left(14\right)$ Combination by equation (9) and (14) can obtain following equation: $\mathrm{ID}=\frac{1}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">R</figure-callout>}1}\&CenterDot;\{\frac{R6}{R6+R7}\&CenterDot;\mathrm{VDD}-(\mathrm{VEB}2+\mathrm{\&Delta;VEB}2)\}---\left(15\right)$

By using equation (15) to △ VEB ₂Carrying out differential can obtain following equation it has represented to cause PNP transistor Q ₂The temperature of variation of emitter-to-base voltage to the influence of drain current: $\frac{\mathrm{\&Delta;I}{D}^{\&prime;}}{\mathrm{\&Delta;<figure-callout\; id="2"\; label="VEB"\; filenames="A9810032000142.png"\; state="\{\{state\}\}">VEB</figure-callout>}2}=\frac{-1}{R1}---\left(16\right)$

By comparing with equation (13) and equation (16), be clear that very much, at the bias circuit that is used for FET according to the present invention, compare with the situation in the prior art bias circuit, cause temperature that the emitter-to-base voltage of PNP transistor Q2 changes to FETQ ₁The influence of drain current be limited to R ₃/ (R ₃+ R ₄).

Though, in order to simplify description, PNP transistor Q ₂And Q ₃Be described as and had essentially identical base stage-emitter voltage characteristic and the identical temperature that causes base stage-emitter voltage to change, but in fact be difficult to obtain transistor with identical characteristics.

Yet, when having selected similar transistor, the very little and fully variation of limit drain current of the difference between them.When coming with comprising two PNP transistor Q simultaneously ₂And Q ₃The PNP transistor integrated circuit time, the PNP transistor that is obtained just might have identical in fact characteristic.

Now, with reference to the accompanying drawings most preferred embodiment of the present invention is described in detail.With reference to figure 1, use as amplifying FETQ ₁GaAsFET amplify the signal of frequency with micron wave length scope.GaAsFETQ ₁Have with as PNP transistor Q ₂The drain electrode that links to each other of the transistorized emitter of silicon PNP and by as resistance R ₁Chip-resistance link to each other with positive supply VDD, and have and as PNP transistor Q ₂The grid that links to each other of the transistorized collector electrode of silicon PNP in addition also by as resistance R ₂Chip-resistance link to each other with negative supply VGG.As with silicon PNP transistor Q ₂Similar PNP transistor Q ₃Silicon PNP transistor have emitter, base stage and the collector electrode that links to each other with base stage that links to each other with positive supply VDD, and by as resistance R ₃Chip-resistance and silicon PNP transistor Q ₂Base stage link to each other and by as resistance R ₄Chip-resistance link to each other with ground.

Below with reference to Fig. 3 the work of this embodiment is described in detail, suppose positive voltage VDD=+3.3V, VEB2=VEB3=+0.7V, △ VEB2=△ VEB3=+0.1V (at-25 ℃), △ VEB2=△ VEB3=OV (+25 ℃), △ VEB2=△ VEB3=-0.1V (+75 ℃) (temperature characterisitic of the emitter-to-base voltage of bipolar transistor be considered to usually-2mv/ ℃), negative supply voltage VGG=-3V, R1=30 Ω, R2=24K Ω, R3=3K Ω, R4=23K Ω, R6=10K Ω, and R7=23K Ω.

Can obtain PNP transistor Q by equation (3) ₂Base voltage VB ₂, also promptly in the time of-25 ℃, VB ₂=2.212V; In the time of+25 ℃, be 2.3V; In the time of+75 ℃, be 2.388V.

Can obtain FETQ by equation (4) ₁Drain voltage VD, also promptly in the time of-25 ℃ VD=3.012V, be 3.0V at+25 ℃, at+75 ℃ for 2.988V.

Can obtain FETQ by equation (11) ₁Drain current ID, also promptly in the time of-25 ℃ ID=9.6mA, at+25 ℃ of ID=10mA, at+75 ℃ of ID=10.4mA.

These all are shown among Fig. 3.

Drain current is ± 4% at the rate of change of room temperature.

On the other hand, according to equation (8), under the situation of not considering temperature, the PNP transistor Q of prior art bias circuit ₂Base stage VB2 ' be 2.3V.

According to equation (9), FETQ ₁Drain voltage VD '-25 ℃ be 3.1V ,+25 ℃ for 3.0V, at+75 ℃ for 2.9V.

According to equation (14), drain current ID ' is 6.667mA at-25 ℃, is 13.333mA at+25 ℃ for 10mA reaches at+75 ℃.

These are shown among Fig. 3.

Therefore, the rate of change of the drain current of prior art bias circuit at room temperature is ± 33.3%.

By foregoing description, can clearly be seen that the temperature variant rate of change of drain current according to the present invention.Substantial improvement has been arranged.

Fig. 4 shows the drain current rate of change characteristic of bias circuit of the present invention and prior art bias circuit.Also be that Fig. 4 has represented, when positive voltage VDD be+when drain voltage VD changes during 3.3V, the result of calculation of drain current rate of change at room temperature.

According to bias circuit of the present invention, the rate of change of drain current is constant to have nothing to do with the drain voltage VD that sets for about 4%, yet according to the bias circuit of prior art, rate of change rises with the rising of drain voltage.

Below with reference to Fig. 5 second embodiment of the present invention is described.The difference of first embodiment shown in second embodiment and Fig. 1 is the fixed resistance R of first embodiment ₄By variable resistor R ₅Substitute.As mentioned above, even as transistor Q ₂And Q ₃For with transistorlike the time, in fact also can not make them have identical emitter-to-base voltage characteristic.In the case, FETQ ₁Drain voltage can with set point exist deviation and thus drain current can have deviation with set point.Yet, by using variable resistor R ₅Substitute fixed resistance, can regulate drain voltage and regulate drain current thus.

Though 6 in minimum embodiment of the present invention, FETQ ₁For N channel junction transistor positive voltage is VDD, and the present invention is not limited to these.

Fig. 6 shows and uses P channel depletion type FETQ ₁Bias circuit.In Fig. 6, negative supply voltage is VDD and positive voltage is VGG.In the bias circuit in Fig. 6, transistor Q ₂And Q ₃Be NPN transistor.For the bias circuit shown in Fig. 6, can obtain identical characteristic by the bias circuit shown in Fig. 1 or Fig. 5.

As mentioned above, the invention is characterized in by the 2nd PNP transistor being added to the transistorized bias voltage of PNP part and can compensate the change in voltage of the transistorized emitter-base stage of a PNP that causes by temperature.

Its result is even work as FETQ ₁Drain voltage also can limit because the variation of the drain current that variation of temperature caused when being set near positive voltage.

Claims (11)

1, a kind of bias circuit that is used to have the field effect transistor (FET) amplifier of a field-effect transistor, it is characterized in that, source terminal with a drain electrode end that links to each other with first power supply, a gate terminal that links to each other with second source and a ground connection, it is characterized in that comprising:

Be connected the described drain electrode end of described field-effect transistor and the first transistor between the described gate terminal; And

Be connected the transistor seconds between the base terminal of described first power supply and described the first transistor.

2, bias circuit according to claim 1 is characterized in that wherein said first and second transistors have essentially identical emitter one base voltage characteristic.

3, bias circuit according to claim 1 is characterized in that described first and second transistors are set in the chip.

4, bias circuit according to claim 1 is characterized in that described the first transistor is by base resistance ground connection.

5, bias circuit according to claim 1 is characterized in that described transistor seconds has a base stage and an emitter that directly links to each other with described base stage.

6, bias circuit according to claim 1, it is characterized in that wherein said field-effect transistor is a N channel junction transistor, described first and second transistors are the PNP transistor, and described first power supply is that positive direct-current power supply and described second source are negative DC power supply.

7, bias circuit according to claim 1, it is characterized in that wherein said field-effect transistor is the p channel depletion mode transistor, described first and second transistors are NPN transistor, and described first power supply is the positive direct-current power supply for the negative described second source of DC power supply.

8, bias circuit according to claim 4 is characterized in that described base resistance is a variable resistor.

9, bias circuit according to claim 1 is characterized in that wherein said field effect transistor (FET) amplifier is the high-frequency amplifier of micron waveband.

10, a kind of bias circuit that is used to have the field effect transistor (FET) amplifier of field-effect transistor has the source terminal of a drain electrode end that links to each other with the positive direct-current power supply, the gate terminal that links to each other with negative DC power supply and a ground connection, it is characterized in that, wherein comprises:

Be connected the described drain electrode end of described field-effect transistor and the PNP transistor between the described gate terminal;

Be connected the described drain electrode end of described field-effect transistor and first resistance between the described positive direct-current power supply;

Be connected the described gate terminal of described field-effect transistor and second resistance between the described negative DC power supply;

Be connected described positive direct-current power supply and have a base stage and an emitter that directly links to each other with described base stage with the 2nd PNP transistor between the transistorized base terminal of a described PNP, the transistorized emitter-to-base voltage characteristic of wherein said first and second PNP is basic identical.

11, a kind of bias circuit that is used to have the field effect transistor (FET) amplifier of field-effect transistor has the source terminal of a drain electrode end that links to each other with negative DC power supply, the gate terminal that links to each other with the positive direct-current power supply and a ground connection, it is characterized in that, wherein comprises:

Be connected the described drain electrode end of described field-effect transistor and first NPN transistor between the described gate terminal;

Be connected the drain electrode end of described field-effect transistor and first resistance between the described negative DC power supply;

Be connected the described gate terminal of described field-effect transistor and second resistance between the described positive direct-current power supply;

The 2nd PNP transistor is connected between described positive direct-current power supply and the transistorized base terminal of a described PNP, it has a base stage and an emitter that directly links to each other with described base stage, and the transistorized emitter-to-base voltage characteristic of wherein said first and second PNP is basic identical.

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