CN1190254A - Mode detecting device and method - Google Patents
Mode detecting device and method Download PDFInfo
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- CN1190254A CN1190254A CN97100705A CN97100705A CN1190254A CN 1190254 A CN1190254 A CN 1190254A CN 97100705 A CN97100705 A CN 97100705A CN 97100705 A CN97100705 A CN 97100705A CN 1190254 A CN1190254 A CN 1190254A
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Abstract
The test mode detecting device is used for IC's and it may cooperate with a test device producing the first recombination signal. The said test mode detecting device includes a signal recombining circuit, which has a special signal input end and recombines the special input signal to produce the first and the second recombined output signals; and a discrimination circuit, which receives the first and the second recombined signals to distinguish whether the said IC is made to enter the said test mode.
Description
The present invention relates to a kind of checkout gear and method, refer to a kind of checkout gear and method especially about test pattern.
The quality quality of integrated circuit in batch production process, usually need the test in the mat batch production process to be distinguished, so, in order in the test program of batch production process, to improve the accuracy of measured data and to improve test speed, can in integrated circuit, comprise the several portions measurement circuit, when testing, confirm the purpose of product quality to realize producing in batches.
Yet, for avoiding integrated circuit when being in normal mode of operation, to be strayed in the survey formula pattern, cause measurement circuit to have influence on the operate as normal of side circuit, the circuit designer has adopted all resolution integrated circuits to be in the method for normal mode of operation and test pattern, so that integrated circuit can be guaranteed the unlikely operate as normal that influences integrated circuit of measurement circuit under the situation that batch process is subsequently tested; But, because of the known mode of distinguishing normal mode of operation and test pattern respectively has its defective, purpose of the present invention promptly is to provide a kind of more stable and apparatus and method of distinguishing normal mode of operation and test pattern that reliability is higher, to overcome the defective of known method.
In known method, the method for the most common enforcement test pattern detection mode is that one of increase or many test pin (test pin) are switched normal mode of operation and test pattern, even in order to distinguish the certain test modes in the multiple test pattern; For example, one test pin is fixed in high potential (/ electronegative potential) state at ordinary times, in case when forcing this test pin to be converted to be in electronegative potential (/ high potential) state from the outside, even integrated circuit is switched in the test pattern by normal mode of operation, integrated circuit begins its internal signal is derived by measurement circuit, and allows directly to control this internal signal by the outside; Like this, external test facility just can utilize this characteristic to be positioned at the corresponding internal signal and the input control signal of IC interior with measurement.
The advantage of aforementioned known method is to divide quite clearly between normal mode of operation and the test pattern, so, can not produce the accident that is strayed into test pattern from normal mode of operation, yet, its defective is to plan that unnecessary pin is with the usefulness as switching, so the integrated circuit for inner wrapping usually forms puzzlement, its reason is that the pin on the inner wrapping integrated circuit often respectively has purposes, and real difficulty is vacated the usefulness of unnecessary specific pin for test; Moreover, because the user can only impose the signal of fixed potential at this specific pin place for test usefulness, just can enter test pattern and internal information is derived, maintain secrecy so be difficult to accomplish circuit.
For improving the defective that aforementioned need additionally are provided with test pin, known other method desires to make integrated circuit to enter the action of normal mode of operation or test pattern for adopting serial (or parallel) signal from a certain specific pin place input specific combination with differentiation; The advantage of this method is need not increase pin and can reaches and distinguish normal mode of operation or test pattern, yet, its shortcoming is to design serial (or parallel) signal that produces which kind of specific combination, make it when integrated circuit is in normal mode of operation, can not produced, otherwise be in the integrated circuit of normal running originally, its operate as normal signal promptly may miss integrated circuit to switch in the test pattern because of identical with the specific combination signal, instead causes misoperation; In other words, because thousand strange hundred kinds of the operate as normal signals of integrated circuit are difficult to guarantee can not take place and the identical thing of this specific combination signal, so known employing is very unreliable from the practice of a certain specific pin place input specific combination signal.
In addition, also have the detection of utilization oscillator whether to vibrate, to distinguish that integrated circuit is in normal mode of operation or is in the known method of test pattern, yet this method is also the same from the known method of a certain specific pin place input specific combination signal with aforementioned employing, and the situation that all is difficult to equally avoid being strayed into test pattern takes place.
Main purpose of the present invention promptly is to provide a kind of checkout gear and method that makes integrated circuit avoid being strayed into the test pattern of test pattern.
Another object of the present invention promptly is to provide a kind of checkout gear and method with test pattern of high security.
Another purpose of the present invention promptly is to provide a kind of checkout gear and method that is issued to the test pattern of measuring integrated circuit in the situation that does not increase test pin.
The present invention relates to a kind of checkout gear of test pattern, can be applicable to an integrated circuit, and this device can be in order to cooperate the testing apparatus of a generation first recombination signal, the checkout gear of this test pattern can comprise: signal reorganization circuit, it has a signal specific input, this signal reorganization circuit is recombinated this signal specific then in order to import a signal specific, and produces the output of one second recombination signal; And a judging circuit, in order to import this first and second recombination signal, whether make this integrated circuit enter test pattern to differentiate.
For achieving the above object, wherein this integrated circuit also can comprise an enabling signal input, and described signal reorganization circuit and this judging circuit all are electrically connected on this enabling signal input, and this enabling signal input is in order to import an enabling signal.
Wherein this enabling signal input can be (reset) signal input part that resets, and this enabling signal then can be a reset signal.
For achieving the above object, wherein said signal reorganization circuit and described judging circuit all can be in one corresponding to described enabling signal and enable (enable) state and produce one and enable to move, and when this enabling signal is in a forbidden energy (disable) state, stop to enable the action of this signal reorganization circuit and this judging circuit.
For achieving the above object, wherein this enabled state can be a high potential state.
For achieving the above object, wherein this enabled state can be a low-potential state.
For achieving the above object, wherein this testing apparatus can be an integrated circuit testing equipment, in order to bulk properties and the quality of measuring this integrated circuit.
For achieving the above object, wherein in this testing apparatus, can comprise another signal reorganization circuit, it has another signal specific input, and this another signal reorganization circuit can be imported another signal specific from this another signal specific input end, and this first recombination signal output of generation of being recombinated.
For achieving the above object, wherein this another signal reorganization circuit also can comprise another and postpone coding circuit, in order to all or part of signal in this another signal specific is cut apart, recombinated, to obtain this first recombination signal.
For achieving the above object, wherein this another signal reorganization circuit can comprise: one first trigger, in order to importing this another signal specific, and with this another signal specific as its clock pulse signal; One second trigger is electrically connected on this first trigger, in order to the output signal of this first trigger as its clock pulse signal; And one the 3rd trigger, be electrically connected on this second trigger, in order to the output signal of this second trigger as its clock pulse signal.
For achieving the above object, wherein this first, second and the 3rd trigger all can be a toggle flip-flop, and this first, second and the output signal of the 3rd trigger in order to as this first recombination signal.
For achieving the above object, wherein this first recombination signal can be the recombination signal of a parallel form.
For achieving the above object, wherein this signal reorganization circuit also can comprise one and postpone coding circuit, in order to all or part of signal in this signal specific is cut apart, recombinated, to obtain this second recombination signal.
For achieving the above object, wherein this signal reorganization circuit can comprise: one the 4th trigger, in order to importing this signal specific, and with this signal specific as its clock pulse signal; One the 5th trigger is electrically connected on the 4th trigger, in order to the output signal of the 4th trigger as its clock pulse signal; And one the 6th trigger, be electrically connected on the 5th trigger, in order to the output signal of the 5th trigger as its clock pulse signal, and the output signal of the 4th, the 5th and the 6th trigger is in order to as this second recombination signal.
For achieving the above object, wherein the 4th, the 5th and the 6th trigger all can be a toggle flip-flop.
For achieving the above object, wherein this second recombination signal can be the recombination signal of a serial form.
For achieving the above object, wherein this second recombination signal can be the recombination signal of a parallel form.
For achieving the above object, wherein this judging circuit system can be a comparator.
For achieving the above object, wherein when this comparator when relatively this first and second recombination signal is identical, can produce a test mode signal, be located at a measurement circuit of this IC interior and enter in this test pattern with driving, otherwise this integrated circuit will be kept and is in the normal mode of operation.
For achieving the above object, wherein the checkout gear of this test pattern can be located at the inside of this integrated circuit.
For achieving the above object, wherein the checkout gear of this test pattern also can comprise: a signal generating circuit, in order to produce this another signal specific and this signal specific, produce this first and second recombination signal respectively for another signal reorganization circuit and this signal reorganization circuit.
For achieving the above object, wherein this signal generating circuit can comprise: a signal generator, in order to produce primary signal output; One state generator is electrically connected on this signal generator, in order to this primary signal is transferred to status signal output; And a signal coder, be electrically connected on this state generator, in order to this status signal is encoded, to produce the output of this another signal specific or this signal specific.
For achieving the above object, wherein this another signal specific or this signal specific can be the signal specific of a serial form.
For achieving the above object, wherein this another signal specific or this signal specific can be the signal specific of a parallel form.
For achieving the above object, wherein this signal generating circuit can be electrically connected on this enabling signal input, and produce one when being in this enabled state and enable action, and when being in this disabled state, this enabling signal stops to enable the action of this signal generating circuit corresponding to this enabling signal.
For achieving the above object, wherein this another signal specific can be identical signal specific with this signal specific.
For achieving the above object, wherein this signal generating circuit can be located in this IC interior, and the checkout gear of this test pattern also can comprise: multiplex's device, with so that an operate as normal signal of this signal specific and this integrated circuit can shared this integrated circuit an output connecting pin end.
For achieving the above object, wherein this multiplex's device can be one or two pairs one multiplexer, the selection signal end of this multiplexer enables to select signal in order to the multiplex (MUX) corresponding to this signal generating circuit place input certainly, exporting this signal specific or this operate as normal signal to this output connecting pin end, being this test pattern or this normal mode of operation corresponding to the residing mode of operation of this integrated circuit.
For achieving the above object, wherein this operate as normal signal can be the system oscillation output signal of system oscillator in this integrated circuit, and this output connecting pin end then can be the output connecting pin end of this system oscillator.
The present invention relates to a kind of detection method of test pattern, can be applicable in the integrated circuit, and this method can be in order to cooperate the testing apparatus of a generation first recombination signal, this method can comprise the following step: a) input one signal specific, make this integrated circuit be cut apart, recombinate, and produce one second recombination signal corresponding to this signal specific; B) import this first recombination signal to this integrated circuit; And c) this first and second recombination signal is compared, whether make this integrated circuit enter this test pattern to differentiate.
For achieving the above object, wherein also can comprise step before: d) enabling signal is offered this integrated circuit in this step (a).
For achieving the above object, wherein be in one when enabling (enable) state, implement this step (a) to this step (c), and when this enabling signal is in a forbidden energy (disable) state, stop to implement this step (a) to this step (c) in this enabling signal.
For achieving the above object, wherein this enabled state can be a high potential state.
For achieving the above object, wherein this enabled state system can be a low-potential state.
For achieving the above object, wherein this enabling signal can be (reset) signal that resets.
For achieving the above object, wherein this testing apparatus can be an integrated circuit testing equipment, in order to bulk properties and the quality of measuring this integrated circuit.
For achieving the above object, wherein this testing apparatus can be imported another signal specific, is cut apart then, recombinates, to produce this first recombination signal output.
For achieving the above object, wherein this first recombination signal can be the recombination signal of a serial form.
For achieving the above object, wherein this first recombination signal can be the recombination signal of a parallel form.
For achieving the above object, wherein described second recombination signal in step (a) can be the recombination signal of a serial form.
For achieving the above object, wherein described second recombination signal in step (a) can be the recombination signal of a parallel form.
For achieving the above object, when wherein more described first and second recombination signal of differentiation is identical in this step (c), can produce a test mode signal, be located at a measurement circuit of this IC interior and enter in this test pattern with driving, otherwise this integrated circuit will be kept and is in the normal mode of operation.
For achieving the above object, wherein this another signal specific or this signal specific can be the signal specific of a serial form.
For achieving the above object, wherein this another signal specific or this signal specific can be the signal specific of a parallel form.
For achieving the above object, wherein this another signal specific can be identical signal specific with this signal specific.
For achieving the above object, wherein also can comprise step afterwards: e) enable to select signal, make this integrated circuit export an operate as normal signal part, transfer this signal specific of output to from it corresponding to this enabling signal and a multiplex (MUX) in step (a); And f) imports this signal specific to this testing apparatus, to produce this first recombination signal.
By following accompanying drawing and detailed description, can more deep understanding be arranged to the present invention.
Fig. 1: be the checkout gear block schematic diagram of the test pattern of first preferred embodiment of the present invention;
Fig. 2 (a) and (b): be the illustrated inside figure of this signal reorganization circuit in the present invention's first preferred embodiment and this another signal reorganization circuit;
Fig. 2 (c): be the waveform example figure of this signal reorganization circuit in the present invention's first preferred embodiment;
Fig. 3: be the checkout gear block schematic diagram of the test pattern of second preferred embodiment of the present invention;
Fig. 4: be the illustrated inside figure of this signal generating circuit in the present invention's second preferred embodiment;
Fig. 5: be the checkout gear block schematic diagram of the test pattern of the 3rd preferred embodiment of the present invention;
Fig. 6: be the detection method schematic flow sheet of the test pattern of one first preferred embodiment of the present invention;
Fig. 7: be the detection method schematic flow sheet of the test pattern of one second preferred embodiment of the present invention.
See also Fig. 1, be the checkout gear block schematic diagram of the test pattern of first preferred embodiment of the present invention, the described device of Fig. 1 comprises: an integrated circuit 10 and a testing apparatus 11; Wherein, comprise in this integrated circuit 10: the checkout gear 101 and the measurement circuit 102 that are test pattern; The checkout gear 101 of this test pattern then comprises: a signal reorganization circuit 1011 and a judging circuit 1012 (preferably, this judging circuit 1012 can be a comparator) with a signal specific input P11; In addition, this integrated circuit 10 also can comprise an enabling signal input P12, uses the usefulness for input one enabling signal S15; Wherein this enabling signal input P12 can be (reset) signal input part that resets, and this enabling signal S15 then can be a reset signal; In this testing apparatus 11, also can comprise signal reorganization circuit 111 with another signal specific input P13.
The preferably, this testing apparatus 11 can be an integrated circuit testing equipment, in order to bulk properties and the quality that measures this integrated circuit 10.
Further specify the operation principle of device shown in Figure 1 now.
At first, for guaranteeing that this integrated circuit can not enter test pattern arbitrarily, can design and make this enabling signal S15 be in one really when enabling (enabe) state, could drive the circuit in the checkout gear 101 of this test pattern, whether enter in the test pattern with decision; In other words, because this signal reorganization circuit 1011 all is electrically connected on this enabling signal input P12 with this judging circuit 1012, so this signal reorganization circuit 1011 and this judging circuit 1012 all can be in this enabled state and produce one and enable action corresponding to this enabling signal S15; Certainly, when being in a forbidden energy (disable) state, then will stop to enable the action of this signal reorganization circuit 1011 and this judging circuit 1012, that is, can guarantee that this integrated circuit 10 is unlikely this moment to enter test pattern arbitrarily and produce misoperation as this enabling signal S15.
Moreover, this signal reorganization circuit 1011 can be from this signal specific input P11 place input one signal specific S11, and be in enabled state in response to this enabling signal S15, thereby produce one and enable action, then this signal specific S11 is recombinated, or filter out part (or all) signal of this signal specific S11, export in this judging circuit 1012 to produce one second recombination signal S12; On the other hand, this another signal reorganization circuit 111 can be imported another signal specific S13 from this another signal specific input P13 place, producing one first recombination signal S14, and is exported in this judging circuit 1012; Afterwards, this judging circuit 1012 is in enabled state in response to this enabling signal S15, thereby produce one and enable action, and differentiate relatively this first and second recombination signal S14, when S12 is identical, can produce test mode signal S16 output, and drive this measurement circuit 102 be located at these integrated circuit 10 inside and enter in this test pattern, otherwise, when different or this enabling signal S15 gets back to this disabled state as signal, this integrated circuit 10 will be kept and be in the normal mode of operation, to reach the original normal circuit function of this integrated circuit 10.
The preferably, the described first or second recombination signal S14, the S12 of serial (or parallel) form can be accepted and relatively be to this judging circuit 1012; Certainly, this judging circuit 1012 also can be selected the one or more comparison signals among the more described first or second recombination signal S14, the S12 arbitrarily individually.
Certainly, no matter signal reorganization circuit 1011 or another signal reorganization circuit 111, its purpose all is in order to strengthen the function of keeping secret of integrated circuit, promptly, have only this testing apparatus 11 adopted be located at these integrated circuit 10 inside in the identical signal reorganization circuit of checkout gear 10 of test pattern, just can organize out identical comparison signal; Certainly, increase the method for confidentiality about another kind, then be to adopt complementary idea, be about to signal reorganization circuit 1011 and be designed to a complementary circuit with another signal reorganization circuit 111, correspondingly signal specific S11 and another signal specific S13 then are a complementary signal, at this moment, handle respectively after another signal specific S13 and the signal specific S11 by another signal reorganization circuit 111 and signal reorganization circuit 1011, just can obtain first and second recombination signal S14 of identical unanimity, S12, so that the checkout gear 10 of this test pattern can produce this test mode signal S16 correct opportunity, and then drive this measurement circuit 102 and enter in this test pattern.
In addition; if described integrated circuit 10 differences; the signal reorganization circuit 1011 of then being located at checkout gear 10 inside of this test pattern in these integrated circuit 10 inside obviously can change or adjust to some extent; thus; another signal reorganization circuit 111 of these testing apparatus 11 inside obviously also need carry out corresponding variation or adjustment; and this change or adjust the work of another signal reorganization circuit 111; it for the designer very easy thing; yet for the plagiarism person; then must be (for example through all complicated processes; implement reduction engineering process etc.) can understand, therefore, for the protection of integrated circuit when more further guarantee can be provided.
And then, about described another signal reorganization circuit 111 and described signal reorganization circuit 1011, one straightforward procedure, can be respectively with correspondingly another signal specific S13 and signal specific S11 directly are sent in the judging circuit 1012, or when somewhat complex design, after the some bit signals of screening are postponed, encode arbitrarily, be resent in the judging circuit 1012; In addition, another signal reorganization circuit 111 and signal reorganization circuit 1011 can be accepted another signal specific S13 and the signal specific S11 of serial (or parallel) form respectively, simultaneously, another signal reorganization circuit 111 and signal reorganization circuit 1011 also can be output as first and second recombination signal S14, the S12 of serial (or parallel) form respectively.
As for the internal circuit exemplary plot (with serial signal be reassembled as parallel signal be example) of described another signal reorganization circuit 111 with signal reorganization circuit 1011, then can consult Fig. 2 (a) and (b) those shown respectively, wherein, another signal reorganization circuit 111 shown in Fig. 2 (a) can comprise: one first trigger FF1, in order to importing another signal specific S13, and with this another signal specific S13 for making its clock pulse signal; One second trigger FF2 is electrically connected on this first trigger FF1, and this second trigger FF2 is in order to the output signal O with this first trigger FF1
0As its clock pulse signal; And one the 3rd trigger FF3, being electrically connected on this second trigger FF2, the 3rd trigger FF3 is in order to the output signal Q with this second trigger FF2
1As its clock pulse signal, the output signal of the 3rd trigger FF3 then is Q
2Certainly, the signal (Q after described another signal specific S13 is recombinated
0, Q
1, Q
2), promptly use as the first recombination signal S14 in order to output, afterwards, the normal signal input pin by this integrated circuit 10 had promptly possessed originally just can be inputed to this first recombination signal S14 in this integrated circuit 10 easily.Described first, second, third trigger FF1, FF2, FF3 enable to move the control that all is subjected to a trigger enable signal SE, and this trigger enable signal SE then can come from the inside of this testing apparatus 11.
In like manner, in the reorganization of the described signal shown in Fig. 2 (b) circuit 1011 also can with trigger (being the one the 4th, the 5th, the 6th trigger FF4, FF5, the FF6) electrical connection that have identical function in another signal reorganization circuit 111 shown in Fig. 2 (a), and its signal (Q after this signal specific S11 can being recombinated
3, Q
4, Q
5), use as the described second recombination signal S12 in order to output; The action that enables as for the 4th, the 5th, the 6th trigger FF4, FF5, FF6 then all will be subjected to the control of this enabling signal S15.
Certainly, at this first～the 6th trigger FF1～FF6 shown in Fig. 2 (a) and (b), all can be a toggle flip-flop, and this arbitrary toggle flip-flop can comprise: a signal input part T, a clock pulse input CK, a signal input part Q and a trigger Enable Pin E.
For example, if if this signal specific S11 is (11001010) serial signal as shown in Fig. 2 (c), then as the waveform of trigger FF4～FF6 output signal of this second recombination signal S12, be as indicating parallel signal shown in (Q3, Q4, Q5) among Fig. 2 (c), so the result obviously can provide the integrated circuit testing function that has more confidentiality than known technology.
Because test shown in Figure 1 only takies one (promptly in order to import the usefulness of this signal specific S11) with pin, so the present invention needn't increase under the situation of known ic pin number, provide a kind of checkout gear that makes integrated circuit avoid being strayed into the test pattern of test pattern and tool high security and high-reliability, to reach the target of measuring integrated circuit smoothly.
Another preferred embodiment about the checkout gear of test pattern of the present invention, see also Fig. 3, it is the checkout gear block schematic diagram of the test pattern of the present invention's second preferred embodiment, among Fig. 3, comprise a testing apparatus 21, one measurement circuit 202, signal reorganization circuit 2011 with a signal specific input P21, one judging circuit, 2012 (preferablies, this judging circuit 2012 can be a comparator), one enabling signal input P22 and a signal reorganization circuit 211 and an enabling signal S25 with another signal specific input P23, its function all can be equal to the testing apparatus 11 shown in Fig. 1, measurement circuit 102, signal reorganization circuit 1011 with signal specific input P11, judging circuit 1012 (preferablies, this judging circuit 1012 can be a comparator), another signal reorganization circuit 111 and this enabling signal S15 of this another signal specific input of enabling signal input P12 and tool P13 are promptly no longer given unnecessary details at this.
The checkout gear 201 of the test pattern shown in Fig. 3 is with checkout gear 101 difference between the two of the test pattern shown in Fig. 1, the checkout gear 201 of described test pattern also can comprise the signal generation device 2013 of being located at this integrated circuit outside, be used for being in this enabled state in response to this enabling signal S25, produce output another a signal specific S23 and a signal specific S21, can correspondingly produce output for another signal reorganization circuit 211 respectively with signal reorganization circuit 2011 and have identical first and second recombination signal S24, S22, thus, this judging circuit 2012 be in this enabled state corresponding to this enabling signal S25 and produce one enable the action, and differentiate relatively this first and second recombination signal S24, when S22 is identical, can produce test mode signal S26 output, and drive this test circuit 202 be located at these integrated circuit 20 inside and enter in this test pattern, otherwise, when different or this enabling signal S25 gets back to this disabled state as signal, this integrated circuit 20 will be kept and be in the normal mode of operation, to reach the original normal circuit function of this integrated circuit 20.
Wherein, about the internal circuit preferred embodiment of this signal generation device 2013, then can consult shown in Figure 4ly, among Fig. 4, this signal generation device 2013 can comprise a signal generator 20131, a state and produce a circuit 20132 and a signal encoding circuit 20133; Wherein, this signal generator 20131 is in order to produce primary signal S27 output; This state generator 20132 is in order to transfer this primary signal S27 to one status signal S28 output; This signal coder 20133 is then in order to be encoded this status signal S28, to produce this another signal specific S23 or this signal specific S21 output; Certainly, this another signal specific S23 can be identical signal specific with this signal specific S21.
Another preferred embodiment about the checkout gear of test pattern of the present invention, see also Fig. 5, checkout gear block schematic diagram for the test pattern of the present invention's the 3rd preferred embodiment, among Fig. 5, comprise a testing apparatus 31, one measurement circuit 302, signal reorganization circuit 3011 with a signal specific input P31, one judging circuit, 3012 (preferablies, this judging circuit 3012 can be a comparator), one enabling signal input P34, signal reorganization circuit 311 and a signal generation device 3013 and an enabling signal S35 with another signal specific input P33, its function all can be equal to this testing apparatus 21 shown in Fig. 3, this measurement circuit 202, signal reorganization circuit 2011 with this signal specific input P21, this judging circuit 2012 (preferablies, this judging circuit 2012 can be a comparator), this enabling signal input P22, have another signal reorganization circuit 211 and this signal generation device 2013 and this enabling signal S25 person of this another signal specific input P23, promptly no longer given unnecessary details at this.
The checkout gear 301 of the test pattern shown in Fig. 5 is with checkout gear 201 difference between the two of this test pattern shown in Fig. 3, the checkout gear 301 of the test pattern described in Fig. 5 is that the signal generation device 2013 that will be located at this integrated circuit outside among Fig. 3 is arranged at this signal generation device 3013 in these integrated circuit 30 inside instead, and, by increasing multiplex's device 3014 (preferablies, can be a multiplexer), so that a signal specific S31 who is produced by this signal generation device 3013 can use integrated circuit output pin end P32 jointly with an operate as normal signal S34 of this integrated circuit 30, thus, when the pin number that can save this integrated circuit 30 more.
Furtherly, this multiplex's device 3014 can be one or two pairs one multiplexer, the selection signal end S of this multiplexer 3014 then enables to select signal S33 in order to the multiplex (MUX) in response to this signal generating circuit 3013 places input certainly, exporting this signal specific S31 or this operate as normal signal S34 to this output connecting pin end P32, with to should integrated circuit 30 residing mode of operations being this test pattern or this normal mode of operation; Certainly, if be output as this signal specific S31 at this output connecting pin end P32 place, this signal specific S31 should provide this another signal reorganization circuit 3113 to produce one first recombination signal S35 and to be input in this judging circuit 3012, simultaneously, this signal reorganization circuit 3011 promptly produces one second recombination signal S32 in response to this signal specific S31, therefore, this judging circuit 3012 produces one and enables action in response to this enabling signal S36 is in this enabled state, and differentiate relatively this first and second recombination signal S35, when S32 is identical, can produce test mode signal S37 output, and drive the measurement circuit 302 be located at these integrated circuit 30 inside and enter test pattern, otherwise, when different or this enabling signal S36 gets back to disabled state as signal, this signal generating circuit 3013 will stop to export or changing the state that this multiplex (MUX) enables to select signal S33, so that this multiplexer 3014 switches back the pattern that can export this operate as normal signal S34 at this output connecting pin end P32 place, that is, this integrated circuit 30 will be kept and be in the normal mode of operation, to reach the original normal circuit function of this integrated circuit 30.
Another preferred version is, this operate as normal signal S34 can be the system oscillation output signal of system oscillator in this integrated circuit 30, and this output connecting pin end P32 then can be the output connecting pin end of this system oscillator.
Certainly, about the schematic flow sheet of the detection method of test pattern of the present invention, then can consult the 6th and 7, Fig. 6 and 7 is respectively the detection method schematic flow sheet of of the present invention one first and second preferred embodiment test pattern; Wherein, about the discrepancy of Fig. 6 and Fig. 7, can be by the operation principle of Fig. 1 and Fig. 5 (or Fig. 3 and Fig. 5) circuit shown in both one clearly understand, promptly no longer given unnecessary details at this.
In sum, utilize the present invention, can be under the condition that does not increase excessive cost, significantly and effectively improve the defective of known method waste IC bond number, low confidentiality and low reliability, so the present invention one has the work of industrial value.
Claims (10)
1. the checkout gear of a test pattern can be applicable to an integrated circuit, and this device can be in order to cooperate the testing apparatus of a generation first recombination signal, and the checkout gear of this test pattern can comprise:
One signal reorganization circuit, it has a signal specific input, and this signal reorganization circuit is in order to import a signal specific and this signal specific is recombinated, to produce the output of one second recombination signal; And
One judging circuit, whether it makes this integrated circuit enter this test pattern in order to import this first and second recombination signal to differentiate.
2. according to the device of claim 1, wherein this integrated circuit also can comprise an enabling signal input, described signal reorganization circuit and described judging circuit all are electrically connected on described enabling signal input, and the usefulness of this enabling signal input for input one enabling signal; Wherein this enabling signal input can be (reset) signal input part that resets, and this enabling signal then can be a reset signal; In addition, described signal reorganization circuit all can produce consistent can the action in response to this enabling signal is in an activation (enable) state with described judging circuit, and when this enabling signal is in a forbidden energy (disable) state, stop the action of described signal reorganization circuit of activation and described judging circuit, wherein this enabled status can be a high potential state or a low-potential state.
3. according to the device of claim 1, wherein this testing apparatus can be an integrated circuit testing equipment, its bulk properties and quality in order to measure this integrated circuit, can comprise another signal reorganization circuit, it has another signal specific input, this another signal reorganization circuit can be imported another signal specific from this another signal specific input end, and this first recombination signal output of generation of being recombinated; And this another signal reorganization circuit also can comprise another delay coding circuit, and it is in order to be cut apart all or part of signal in this another signal specific, recombinate, to obtain this first recombination signal; And this another signal reorganization circuit can comprise:
One first trigger, it is in order to importing this another signal specific, and with the usefulness of this another signal specific as its clock pulse signal;
One second trigger is electrically connected this first trigger, and this second trigger is in order to the output signal of this first trigger usefulness as its clock pulse signal; And
One the 3rd trigger is electrically connected on this second trigger, and the 3rd trigger is in order to the output signal of this second trigger usefulness as its clock pulse signal; Wherein this first, second and the 3rd trigger can be a toggle flip-flop, and this first, second and the output signal of the 3rd trigger in order to usefulness as this first recombination signal.
4. according to the device of claim 1, wherein this first recombination signal can be the recombination signal of a tandem form, or the recombination signal of a form arranged side by side; And wherein this signal reorganization circuit also can comprise a delay coding circuit, and it is in order to be cut apart all or part of signal in this signal specific, recombinate, to obtain this second recombination signal; And wherein this signal reorganization circuit can comprise:
One the 4th trigger, it is in order to importing this signal specific, and with the usefulness of this signal specific as its clock pulse signal;
One the 5th trigger is electrically connected on the 4th trigger, and the 5th trigger is in order to the output signal of the 4th trigger usefulness as its clock pulse signal; And
One the 6th trigger, be electrically connected on the 5th trigger, the 6th trigger is in order to the output signal of the 5th trigger usefulness as its clock pulse signal, and the output signal of the 4th, the 5th and the 6th trigger is in order to the usefulness as this second recombination signal; Wherein the 4th, the 5th and the 6th trigger can be a toggle flip-flop.
5. according to the device of claim 1, wherein this second recombination signal can be the recombination signal of a tandem form, or the recombination signal of a form arranged side by side, and described judging circuit can be a comparator, this comparator is when relatively this first and second recombination signal is identical, can produce a test mode signal, be located at a measurement circuit of this IC interior and enter in this test pattern with driving, otherwise this integrated circuit will be kept in the normal mode of operation; And the checkout gear of this test pattern can be located at the inside of this integrated circuit.
6. according to the device of claim 1, wherein the checkout gear of this test pattern also can comprise a signal generating circuit, it is in order to produce this another signal specific and this signal specific, produce this first and second recombination signal respectively for another signal reorganization circuit and this signal reorganization circuit, this signal generating circuit can comprise:
One signal generator, it is in order to produce primary signal output;
One state generator is electrically connected on described signal generator, and this state generator is in order to transfer this primary signal to the output of one status signal; And
One signal coder is electrically connected on described state generator, and this signal coder is in order to be encoded this status signal, to produce the output of this another signal specific or this signal specific; And this another signal specific or this signal specific can be the signal specific of a tandem form or the signal specific of a form arranged side by side; And this signal generating circuit can be electrically connected on this enabling signal input, produces consistent can the action when being in this enabled status in response to this enabling signal, and stop the action of this signal generating circuit of activation when this enabling signal is in this disabled state; This another signal specific can be identical signal specific with this signal specific; This signal generating circuit can be located in this IC interior, and the checkout gear of this test pattern also can comprise multiplex's device, its with so that the operate as normal signal of this signal specific and this integrated circuit can shared this integrated circuit an output connecting pin end, this multiplex's device can be one or two pairs one multiplexer, the selection signal end of this multiplexer is in order to select signal in response to multiplex's activation of this signal generating circuit place input certainly, to export this signal specific or this operate as normal signal to this output connecting pin end, with to should the residing mode of operation of integrated circuit being this test pattern or this normal mode of operation, and this operate as normal signal can be the system oscillation output signal of system oscillator in this integrated circuit, and this output connecting pin end then can be the output connecting pin end of this system oscillator.
7. the detection method of a test pattern, it can be applicable in the integrated circuit, and this method can be in order to cooperate a testing apparatus that produces first recombination signal, and this method can comprise the following step:
A) input one signal specific makes this integrated circuit be cut apart, recombinate in response to this signal specific, and produces one second recombination signal;
B) import this first recombination signal to this integrated circuit; And
C) this first and second recombination signal is carried out the differentiation action, whether make this integrated circuit enter this test pattern to differentiate.
8. according to the method for claim 7, wherein the preceding step (d) that also can comprise in this step (a) provides an enabling signal to this integrated circuit, wherein when this enabling signal is in an activation (enable) state, this step of Fang Zhihang (a) is to this step (c), and when this enabling signal is in a forbidden energy (disble) state, stop to carry out this step (a) to this step (c); And this enabled status can be a high potential state or a low-potential state, and this enabling signal can be (reset) signal that resets.
9. according to the method for claim 7, wherein this testing apparatus can be an integrated circuit testing equipment, its bulk properties and quality in order to measure this integrated circuit; And this testing apparatus can be imported another signal specific, and cut apart, recombinated, to produce this first recombination signal output, wherein this first recombination signal can be the recombination signal of a tandem form or the recombination signal of a form arranged side by side, and this second recombination signal in this step (a) can be the recombination signal of a tandem form or the recombination signal of a form arranged side by side; Differentiate when relatively this first and second recombination signal is identical in this step (c) again, can produce a test mode signal, be located at a measurement circuit of this IC interior and enter in this test pattern with driving, otherwise this integrated circuit will be kept and is in the normal mode of operation; In addition, this another signal specific or this signal specific can be the signal specific of a tandem form or the signal specific of a form arranged side by side.
10. according to the method for claim 9, wherein this another signal specific can be identical signal specific with this signal specific; And the back of this step (a) also can comprise step:
E) select signal in response to this enabling signal and multiplex's activation, make this integrated circuit export an operate as normal signal part, transfer this signal specific of output to from it; And
F) import this signal specific to this testing apparatus, to produce this first recombination signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97100705A CN1072399C (en) | 1997-02-04 | 1997-02-04 | Mode detecting device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97100705A CN1072399C (en) | 1997-02-04 | 1997-02-04 | Mode detecting device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1190254A true CN1190254A (en) | 1998-08-12 |
| CN1072399C CN1072399C (en) | 2001-10-03 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97100705A Expired - Fee Related CN1072399C (en) | 1997-02-04 | 1997-02-04 | Mode detecting device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1072399C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103365735A (en) * | 2012-04-09 | 2013-10-23 | 纬创资通股份有限公司 | Transmission interface and method for determining transmission signal |
| CN104134466A (en) * | 2014-07-23 | 2014-11-05 | 大唐微电子技术有限公司 | Chip and test state entering method thereof |
| CN104345266A (en) * | 2013-07-25 | 2015-02-11 | 汤铭科技股份有限公司 | Chip for realizing communication interface by using existing functional pins |
| CN106918775A (en) * | 2017-04-21 | 2017-07-04 | 成都锐成芯微科技股份有限公司 | The access method of chip test mode |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62121374A (en) * | 1985-11-20 | 1987-06-02 | Ricoh Co Ltd | Test mode starting circuit |
| JPH0799619B2 (en) * | 1989-12-28 | 1995-10-25 | 三菱電機株式会社 | Semiconductor memory device |
-
1997
- 1997-02-04 CN CN97100705A patent/CN1072399C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103365735A (en) * | 2012-04-09 | 2013-10-23 | 纬创资通股份有限公司 | Transmission interface and method for determining transmission signal |
| CN104345266A (en) * | 2013-07-25 | 2015-02-11 | 汤铭科技股份有限公司 | Chip for realizing communication interface by using existing functional pins |
| CN104345266B (en) * | 2013-07-25 | 2017-06-23 | 汤铭科技股份有限公司 | Chip for realizing communication interface by using existing functional pins |
| CN104134466A (en) * | 2014-07-23 | 2014-11-05 | 大唐微电子技术有限公司 | Chip and test state entering method thereof |
| CN104134466B (en) * | 2014-07-23 | 2017-05-10 | 大唐微电子技术有限公司 | Chip and test state entering method thereof |
| CN106918775A (en) * | 2017-04-21 | 2017-07-04 | 成都锐成芯微科技股份有限公司 | The access method of chip test mode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1072399C (en) | 2001-10-03 |
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