CN1188931A - Arithmetic stage - Google Patents

Abstract

An arithmetic stage calculates the sum AX+BY where A and B are 1-bit signals and X and Y p bit coefficients X=7 and Y=3 and the corresponding bits b1 to b5 are represented together with the corresponding logical states of A and B. It will be seen that for example column b3 together with columns A and B is the truth table of an NAND gate. Column b2 together with columns A and B is the truth table of a COINCIDENCE gate. In the example of figure 5 column b4 equals B, column b1 is logical 0 whatever the states of A and B,and column b5 is NOT A. Thus in accordance with one illustrative embodiment of the invention the arithmetic stage may be implemented by the logic circuit of figure6 where bit b5 is produced by inverting A, bit b4 is produced by coupling output b1 to input B, via a direct connection, bit b3 is produced by a NAND gate 61, bit b2 is produced by a COINCIDENCE gate 62, and bit b1 is produced by coupling output b4 to a source of logical '0' via a connection 63.

Description

Arithmetic stage

The present invention relates to be used to form each signal and each coefficient amass and arithmetic stage.This 1 signal long-pending and be in such as 1 signal processor that comprises the Ta of n level Dell-Xi Gema modulator, to calculate.Embodiments of the invention relate to this 1 signal processor.The preferred embodiments of the present invention relate to Audio Signal Processing, but the present invention is not limited to audio signal processor.

1,2 and 3 background of the present invention is described with reference to the accompanying drawings, wherein, Fig. 1 is the block scheme of known Dell's tower-Xi Gema modulator, and Fig. 2 is the block scheme of Dell's tower-Xi Gema modulator of constituting as n level filter segment, and Fig. 3 is the noise shaping characteristic.

Having known can be by leading the sampled analog signal and by the m figure place amplitude coding of sampling is become digital form with analog signal conversion being at least anti-Qwest.Therefore, if m=8, sampling just is quantified as 8 precision.In general m can be for being equal to or greater than 1 any digit.

Only there to be 1 in order being quantized into, to it is reported the analog-digital converter (ADC) that " Xi Gema-Dell's tower A/D converter " or " Dell's tower-Xi Gema A/D converter " is provided.Adopted noun " tower-Xi Gema of Dell " herein.This ADC has described in by the Craig Marven of Texas Instruments and Gillian Ewers disclosed with ISBN 0-904.047-00-8 " straightforward procedure of digital signal processing ".

See this ADC of Fig. 1,1 quantizer 3 of feeding of poor (the Dell's tower) between the integration (Xi Gema) of analog input signal and 1 output signal.Output signal comprises the position of logical value 0 and 1, and is represented as-1 and+1 actual value respectively.Integrator 3 adds up 1 output, and so wherein the value of being stored is then followed the value in simulating signal.Quantizer 3 is along with the generation of each increases accumulated value (+1) 1 or reduces (1) 1.ADC needs very high sampling to produce the output bit stream, and its accumulated value is followed in simulating signal.

Following description and " 1 " signal in the claim mean that signal is quantized into the precision such as 1 figure place that is produced by the Ta of Dell-Xi Gema ADC.

Constituting the direct Ta of the Dell-Xi Gema modulator (DSM) of handling 1 signal of n level filtering part is to be proposed in the paper of 7-10 day in October, 1993 running after fame in the 95th the AES meeting in New York " 1 bit digital of sound signal is handled " by N.M.Casey and James A.S.Angus.Fig. 2 illustrates the circuit diagram of the 3rd level (n=3) of this DSM filtering part.

See Fig. 2, DSM has the input end 4 of 1 sound signal and the output terminal 5 that produces 1 signal after handling.1 signal the position by known unshowned clock device through DSM institute clock.Exporting 1 signal is produced by 1 quantizer such as the comparer with zero threshold level.DSM has 3 grades, and every grade comprises the one 1 the multiplier a that is connected to input end 4 ₁, a ₂, a ₃, be connected to the 21 multiplier C of output terminal 5 ₁, C ₂, C ₃, totalizer 6 ₁, 6 ₂, 6 ₃With integrator 7 ₁, 7 ₂, 7 ₃

1 multiplier with 1 signal times being received with P potential coefficient A ₁, A ₂, A ₃, C ₁, C ₂, C ₃, producing P position product, these products are by totalizer 61,62,63 additions and and be added on the integrator 7.In the intergrade of totalizer 62,63, also will handle the output addition of level integrator.Level does not comprise another 1 the multiplier A4 that is connected to input end, and it makes input signal be multiplied each other by P potential coefficient A4, totalizer 64 with MAD to the output of the integrator 73 of handling level.Itself and be added on the quantizer 2.

In DSM, two complementary arithmetic device can be used to represent the P figure place of positive and negative.The input of quantizer Q can be positive, turns in output quantity+1 (logical one), or negative, turn to-1 (logical zero) in output quantity.

In the article of Casey and Angus " 1 bit processor will produce one 1 output; this output packet is contained in the sound signal of being hidden in the noise of unacceptable degree; and be badly in need of making the noise of quantification by suitably shaping ", the noise of hiding sound signal is the quantizing noise that is produced by quantizer Q.

Quantizer Q can be a totalizer, and its first input end received audio signal and second input end receive basically and the irrelevant stream of random bits (quantizing noise) of sound signal.Under the sort circuit scheme, the sound signal that receives at input end 4 is by multiplier a ₁, a ₂, a ₃, a ₄ Feed output terminal 5 and of forward by multiplier C ₁, C ₂, C ₃Feed back from output terminal 5.Therefore, coefficient A ₁To A ₄Define zero of sound signal transform transition function, and coefficient C ₁-C ₃Define the utmost point of transmission of audio signals function.

Yet noise signal is by multiplier C ₁-C ₃Come from quantizer feedback, like this, coefficient C ₁-C ₃Limit the utmost point of the transition function of noise signal.

Coefficient A ₁-A ₄And C ₁-C ₃The first-selected stability that circuit is provided in other desired characteristic.

Coefficient C ₁-C ₃As the noise shaping aspect, thereby shown in Fig. 3 solid line 31, make the quantizing noise in the vocal cores reduce to minimum.

Coefficient A ₁-A ₄And C ₁-C ₃Also be used for required Audio Signal Processing characteristic.

Coefficient A ₁-A ₄And C ₁-C ₃Selection can facilitate by following factors:

A) find out the transform H (Z) of required filtering characteristic, for example the noise shaping function; With

B) H (Z) is transformed into coefficient.

More than can be by people such as R.W.Adams at Journal of Audio EngineeringSociety, the method for describing in the article " Theory and PracticalImplementation of a Fifth Order Sigma-Delta A/D Converter " in 1991 7/8 month 39 volumes the 7/8th realizes.Can also realize by the method in the article of Angus described in the prior art description partly in the above and Casey.The coefficient of analyzing level V DSM and being used to calculate required filtering characteristic is described.

Figure 12 illustrates level V, DSM, and it has coefficient a-f and A-E, totalizer 6 and integrator 7.Each of integrator 7 all provides the delay of a unit.The output of integrator is from left to right represented by S-W.Input to DSM is a signal X (n), wherein a sampling in the clock controlled sequence of n representative sampling.Input to quantizer Q is represented by Y (n), and it also is the output signal of DSM.Analysis is based on a kind of mode of operation, supposes that promptly quantizer Q is a simple totalizer, and it is added to random noise on the signal after the processing.Therefore in analyzing, this will ignore quantizer.

Signal Y (n)=fx (n)+w (n), promptly the output signal Y (n) of sampling (n) adds the output W (n) that handles integrator 7 again for input signal X (n) multiply by coefficient f.

Identity principle is used for produce on each output signal of integrator 7 system of equations 1.

y[n]＝fx[n]+W[n]

w[n]＝w[n-1]+ex[n-1]+Ey[n-1]+v[n-1]

v[n]＝v[n-1]+dx[n-1]+Dy[n-1]+u[n-1]

u[n]＝u[n-1]+cx[n-1]+Cy[n-1]+t[n-1]

t[n]＝t[n-1]+bx[n-1]+By[n-1]+s[n-1]

S[n]=s[n-1]+ax[n-1]+Ay[n-1] these equations must system of equations 2 after passing through transforms.

y(z)＝fx(z)+W(z)

W(z)(1-z ^-1)＝z ^-1(eX(z)+EY(z)+V(z))

V(z)(1-z ^-1)＝z ^-1(dX(z)+DY(z)+U(z))

U(z)(1-z ^-1)＝z ^-1(cX(z)+CY(z)+T(z))

T(z)(1-z ^-1)＝z ^-1(bX(z)+BY(z)+S(z))

S (z) (1-z ^-1)=z ^-1(aX (z)+AY (z)) transform equation can be separated into the single function that Y (z) is X (z) (equation 3). $Y\left(z\right)=\mathrm{fX}\left(z\right)+\frac{z^{-1}}{(1-z^{-1})}\left(\mathrm{eX}\right(z)+\mathrm{EY}(z)+$ $\frac{z^{-1}}{1-z^{-1}}(\mathrm{dX}\left(z\right)+\mathrm{DY}(z)+$ $\frac{z^{-1}}{1-z^{-1}}(\mathrm{cX}\left(z\right)+\mathrm{CY}(z)+$ $\frac{z^{-1}}{1-z^{-1}}(\mathrm{bX}\left(z\right)+\mathrm{BY}(z)+$ $\frac{z^{-1}}{1-z^{-1}}(\mathrm{aX}\left(z\right)+\mathrm{AY}(z\left)\right)\left)\right)\left)\right)$ This can be expressed as equation 4 again, and the required transmission number of DSM can be expressed as the polyphone form: $\frac{Y\left(z\right)}{X\left(z\right)}$ Then equation 4 is: $\frac{Y\left(z\right)}{X\left(z\right)}=\frac{{\mathrm{\α}}_0+{\mathrm{\α}}_1{z}^{-1}+{\mathrm{\α}}_2{z}^{-2}+{\mathrm{\α}}_3{z}^{-3}+{\mathrm{\α}}_4{z}^{-4}+{\mathrm{\α}}_5{z}^{-5}}{{\mathrm{\β}}_0{+\mathrm{\β}}_1{z}^{-1}+{\mathrm{\β}}_2{z}^{-2}+{\mathrm{\β}}_3{z}^{-3}+{\mathrm{\β}}_4{z}^{-4}+{\mathrm{\β}}_5{z}^{-5}}$ $=\frac{f{(1-z^{-1})}^3+z^{-1}e{(1-z^{-1})}^4+{z^{-2}d(1-z^{-1})}^3+{z^{-3}c(1-z^{-1})}^2+z^{-1}b(1-z^{-1})+z^{-5}a}{{(1-z^{-1})}^5-z^{-1}E{(1-z^{-1})}^4-z^{-2}D{\left(1{-}^{-1}x\right)}^3-z^{-3}C{(1-z^{-1})}^2-z^{-4}B(1-z^{-1})-Z^{-5}A}$

Solving an equation 4 can be from factor alpha ₀-α ₅In draw coefficient f-a, from factor beta ₀-β ₅In draw coefficient E-A, factor alpha _nAnd β _nSelect in a known way so that required transition function to be provided.

F only is the Z in the molecule ⁰, so f=α ₀

From the molecule on the left side, deduct α subsequently ₀(1-z ^-1) ⁵, the α that obtains calculating ₀+ α ₁z ^-1+ ... α ₅Z ^-5-α ₀(1-z ^-1) ⁵

Similarly from the molecule of the right, deduct f (1-z ^-1) ⁵E is unique z subsequently ^-1, and with the on the left side molecule in the corresponding α that calculates ₁Equate.

This processing procedure repeats in the molecule all.

This processing procedure repeats in the denominator all.

At filter segment by when using 1 multiplier and avoid P position multiplication, the bit rate of bit stream along with coefficient and 1 signal long-pending and quick generation and correspondingly require to improve.

According to an aspect of the present invention, a kind of two 1 signal A and B and its coefficient X and the Y product and arithmetic stage AX+BY of being used to form is provided, should and have 4 value+X+Y, + X-Y,-X+Y and-X-Y, each value has the P position, wherein, P is at least 2, this processor comprises the device that forms truth table, be used for that the four groups of corresponding P place values with described each value of value of representative are relevant in logic with four logic states of A and B, the device of this formation truth table have the input end that is used to receive A and B and with export with described input end on the state A and the corresponding P place value in groups of B that receive.

According to a further aspect in the invention, a kind of two 1 signal A and B and its coefficient X and the Y product and arithmetic stage AX+BY of being used to form is provided, should and have 4 value+X+Y ,+X-Y ,-X+Y and-X-Y, each value has the P position, this level comprises logical circuit and a plurality of logic gate, this logical circuit has two and is used to receive A that P output is arranged respectively and the input end of B, P output terminal output and each P place value, logical circuit is realized logic function, makes four logic states of A and B relevant with four groups of P place values of representative and AX+BY.

This makes the full position totalizer that need not expensive P position multiplier and work more slowly just can produce required arithmetic function fast according to 1 signal A and B.

In order to understand the present invention better, 4 to 11 the present invention is described with reference to the accompanying drawings.

Fig. 4 is the schematic block diagram of the integrator stage of DSM;

Fig. 5 is the relevant truth table of state with 1 input signal A and B, illustrate signal A and B and each coefficient long-pending and;

Fig. 6 is the logical circuit of the truth table of realization Fig. 5;

Fig. 7 A and 7B are the logical circuit of another group truth table and this group truth table of realization, and the point of fixity algorithm is shown;

Fig. 8 illustrates total logical circuit;

Fig. 9 is the synoptic diagram that is used to store the memory storage of tracing table;

Figure 10 and 11 schematic block diagrams for the arithmetic stage that uses with variable coefficient.

See Fig. 4, shown integrator stage is corresponding with the integrator stage of the known DSM of Fig. 2 on function.Two 1 signal A and B are added on the arithmetic stage 40 from bringing out 5 such as the input end 4 of DSM and DSM defeated.Shown arithmetic stage has the one 1 multiplier a ₁, this multiplier multiply by P potential coefficient X, the 21 multiplier C with 1 signal A ₁, it multiply by P potential coefficient Y and totalizer 6 with 1 signal B, and it forms and AX+BY.

In effect, stored all possible in the arithmetic stage and value AX+BY according to illustrated embodiment of the present invention.Corrected value is to be selected by state A and B at input end.It make will produce and produce very fast.Truth table can represent that wherein X and Y fix by " connecing firmly " logical circuit (hard-wired) shown in Fig. 6 or 7B.

In addition, truth table also can be stored as by the tracing table in the suitable storer of A shown in Fig. 9 and B addressing.If coefficient is fixed, then storer can be ROM.Coefficient can be variable, but and storer can be the storer of wiring.In an embodiment, counting circuit calculates the corresponding truth table that is stored in the storer in response to the instantaneous value of variable coefficient.Subsequently by signal A and B addressing truth table.

With the AX+BY integrator 7 of feeding.This integrator also comprises totalizer 41 and unit delay device 42.

The output of unit delay device 42 feeds back to the totalizer 41 of the integration of the AX+BY that adds up.

Can be such as the P figure place with AX+BY.

Each of A and B all has the logic state 1 and 0 of representative+1 respectively and-1.Therefore be four probable values of P position with having each:

A B

+X+Y 1 1

+X-Y 1 0

-X+Y 0 1

-X-Y 0 0

According to the present invention and every of AX+BY all be the logical function of state A and B.For example, consider fixed coefficient X=7 and Y=3, and be expressed as with what 2 complement form occurred and have a b ₁-b ₅5 bit digital:

b ₅ b ₄ b ₃?b ₂ b ₁

+7＝ 0 0 1 1 1

+3＝ 0 0 0 1 1

-7＝ 1 1 0 0 1

-3＝ 1 1 1 0 1

See Fig. 5, wherein X=7 and Y=3 and corresponding position b ₁-b ₅Four possible and value AX+BY show together with corresponding logic state A and B.Will find such as hurdle b ₃Reaching hurdle A and B is the truth table of a door.Hurdle b ₂Reaching hurdle A and B is coincidence counting door (c) truth table.

In the example of Fig. 5, hurdle b ₄Equal B and hurdle b ₁No matter state A and B are logical zero.Hurdle b ₅Equal non-A.

Therefore according to embodiments of the invention, arithmetic stage 40 can be realized by the logical circuit of Fig. 6, wherein:

Position b ₄Be by exporting b ₄Produce with input end B coupling through direct connecting circuit 60;

Position b ₃Produce by Sheffer stroke gate 61;

Position b ₂Produce by coincidence counting door 62;

Position b ₁Be by exporting b ₁Be coupled to through connecting circuit 60 and produce on the source of logical zero, and

Position b ₅Serve as reasons to have and produce as the not gate of input end A.

In currently preferred embodiment of the present invention, coefficient X and Y have the non integer value that can be plus or minus.Coefficient is to realize in the complement code algorithm of point of fixity 2 with the binary point that is placed on the appropriate position.Can be stored in that maximal value in the integrator 7 of each integration stages knew in advance before this.Binary point is placed on the appropriate location that can store maximum integrator value.

See the example of the employing point of fixity non integer value of Fig. 7 A and 7B, make X=1.5 and Y=0.5.

Fig. 7 A illustrates final truth table and Fig. 7 B illustrates the logical circuit that is equal to mutually.

See Fig. 8, produce the P position by P logic gate G1-Gp and AX+BY, its fixing logic function depends on fixed value X and Y.Can prove that from Fig. 6 the door of indication can be b herein ₁In simple connecting circuit or b ₄In the source of fixed logic.

The logic gate that does not need to provide rigid line to connect realizes A and B one of four states are calculated AX+BY and the truth table that obtains.

Truth table can be stored as simply can be by the tracing table in the storer of A shown in figure P and B addressing such as ROM.

The description of front is about the fixed value of coefficient A and Y.In further embodiment of the present invention, X and Y are variable.Variable coefficient is to produce in 1 signal processor that comprises as the DSM in the application 9624671.5 of co-applications, and this signal processor is a signal mixer.

See Figure 10, variable coefficient X and Y are by coefficient generator 100 produce and the processors 101 of being fed.Processor 101 at each state computation P position of four kinds of states of 1 signal A and B and AX+BY.The P position of each state of one of four states constitutes the truth table shown in Fig. 5 or 7A.Truth table is stored in the represented storer of Figure 10 square frame 40, and is corresponding with the arithmetic stage 40 of Fig. 4.Truth table is stored as the tracing table by A and B addressing.The state that is input to A in the storer 40 and B is selected the suitable group of P position from truth table, it is as the suitable integrator of exporting and feed DSM algorithm device level with AX+BY 7.

See Figure 11, in a preferred embodiment, provide at least two storeies 401 and 402.If coefficient X and Y change, in storer 101, calculate continuous truth table and also alternately be stored in storer 401 and 402.1 signal alternately is fed in storer 401 and 402 and through the output multiplier through input multiplier 111 alternately to be exported from storer.The processor controls 403 of storer by also controlling multiplier according to A and B will with the position write truth table and from truth table, read.

Receive such as 402 storer input A and B with read and in, other storer receives new truth table.

When signal A and B addressable memory 401, recomputate truth table and be stored in subsequently in the storer 402 by A and B addressing at the following class value of X and Y.By interleaving memory 401 and 402, can calculate apace at X and Y changing value with AX and BY.

Processor 101 is used for calculating truth table and coefficient generator 100 can be realized by the programmable calculator of Figure 10 102 representatives.

Writable memory 40,401 and 402 can be programmable gate array.

Claims (11)

1. one kind is used to form two 1 signal A and B and its coefficient X and the Y product and arithmetic stage AX+BY, should and have 4 value+X+Y ,+X-Y ,-X+Y and-X-Y, each value has the P position, wherein, P is at least 2, this processor comprises the device that forms truth table, be used for that the four groups of corresponding P place values with described each value of value of representative are relevant in logic with four logic states of A and B, the device of this formation truth table have the input end that is used to receive A and B and with export with described input end on the state A and the corresponding P place value in groups of B that receive.

2. level as claimed in claim 1 is characterized in that the device that is used to form truth table comprises the memory storage of storing truth table, and by the table of signal A and B addressing.

3. as the level of claim 1 or 2, it is characterized in that coefficient X and Y so that truth table is fixed.

4. as the level of claim 1 or 2, it is characterized in that one of coefficient X and Y are so that truth table is variable at least.

5. level as claimed in claim 4 is characterized in that also comprising the device that is used for calculating truth table in response to coefficient X and Y.

6. level as claimed in claim 5, it is characterized in that it comprises that a pair of truth table forms device and is used for making truth table to be stored in the control device of one of described formation device, meanwhile by described 1 signal A and B addressing other parts with will be described and export and react as the same.

7. one kind is used to form two 1 signal A and B and its coefficient X and the Y product and arithmetic stage AX+BY, should and have 4 value+X+Y ,+X-Y ,-X+Y and-X-Y, each value has the P position, this level comprises logical circuit and a plurality of logic gate, this logical circuit has two and is used to receive A that P output is arranged respectively and the input end of B, P output terminal output and each P place value, logical circuit is realized logic function, makes four logic states of A and B relevant with four groups of P place values of representative and AX+BY.

8. arithmetic stage as claimed in claim 7 is characterized in that logical circuit comprises the P logic gate.

9. arithmetic stage that is used to form the arithmetic function of two 1 signal values, this function has four values that depend on the value of two 1 signals, each value has the P position, wherein P is at least 2, this grade comprises the device that forms truth table, logically each the four groups of P place values with four logic states of A and B and the described value of representative are relevant, and this formations device has the input end that is used to receive A and B and the output terminal that is used to export in groups the P place value corresponding with the A of described input end reception and B state.

10. one kind comprises the Ta of the Dell-Xi Gema modulator of the desired arithmetic stage of claim as described above.

11. one kind comprises the audio signal processor as the Ta of the Dell-Xi Erma modulator of claim 10.

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