CN118800769A

CN118800769A - Pixel detector

Info

Publication number: CN118800769A
Application number: CN202311159436.0A
Authority: CN
Inventors: 周鸣昊; 钟华强
Original assignee: Wuxi Jianwei Huaxin Technology Co ltd
Current assignee: Wuxi Jianwei Huaxin Technology Co ltd
Priority date: 2023-09-08
Filing date: 2023-09-08
Publication date: 2024-10-18

Abstract

The present application relates to a pixel detector. The pixel detector comprises a photosensitive pixel chip and a readout pixel chip, wherein: the local photosensitive pixel array of the photosensitive pixel chip has the same row and column number as the readout pixel array of the readout pixel chip, and the pixel size of the local photosensitive pixel array is larger than that of the readout pixel array; the photosensitive pixel chip and the readout pixel chip realize the mapping of the pixel array through a RDL rewiring layer. The method can obviously reduce the detection dead zone when a plurality of pixel detectors are spliced.

Description

Pixel detector

Technical Field

The application relates to the field of pixel detectors, in particular to a pixel detector.

Background

A pixel detector refers to a detector that is capable of measuring particle energy, position, and other characteristics. Pixel detectors are typically composed of a large number of homogeneous pixels, each capable of measuring information such as the position, energy, charge, etc. of an incident particle, while generating charge and voltage signals inside the detector. The signals are collected, amplified, converted and analyzed by circuits such as a preamplifier, a data converter and a digital processor, and finally a complete particle image or spectrogram is formed.

The pixel detector is generally composed of a photosensitive pixel chip and a readout pixel chip, and the photosensitive pixel chip and the readout pixel chip realize lattice packaging through a flip-chip bonding technology. The photosensitive pixel chip generally mainly comprises a photosensitive pixel array, a first light source, a second light source and a first light source, wherein the photosensitive pixel array is used for receiving light signals and converting the light signals into electric signals; the readout pixel chip generally mainly includes a readout pixel array, a peripheral circuit, and an IO pin, and is used for converting a voltage signal in a photosensitive pixel into a digital signal and performing signal processing. By combining the photosensitive pixels and the readout pixels, the pixel detector can convert the optical signals into digital images for image processing and analysis.

In the prior art, the photosensitive pixels and the readout pixels are in one-to-one correspondence, and the shapes and the sizes are basically equal. As shown in fig. 1, the readout pixel chip includes peripheral circuits and IO pins in addition to the readout pixel array, and there are no photosensitive pixels on the photosensitive pixel chip corresponding to the areas where the peripheral circuits and the IO pins are located. Therefore, the area where the peripheral circuits and the IO pins are located will become a detection dead zone of the pixel detector, especially when a plurality of readout pixel chips or pixel detectors are needed for stitching, the detection dead zone between the readout pixel chips or pixel detectors will affect the effective imaging area and imaging efficiency.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a pixel detector that reduces the detection dead zone when a plurality of readout pixel chips or pixel detectors are tiled.

In a first aspect, the present application provides a pixel detector, the pixel detector comprising a photosensitive pixel chip and at least one readout pixel chip, each readout pixel chip corresponding to a local photosensitive pixel array of the photosensitive pixel chip, the total number of readout pixels of all readout pixel chips being equal to the number of photosensitive pixels of the photosensitive pixel chip, wherein:

the read-out pixel array of each read-out pixel chip has the same row and column number as the corresponding local photosensitive pixel array, and the pixel size of the local photosensitive pixel array is larger than that of the read-out pixel array;

the local photosensitive pixel array and the readout pixel array realize mapping of the pixel array through an RDL rewiring layer.

In one embodiment, the pixel shapes of the local photosensitive pixel array and the readout pixel array are rectangular;

the long sides of the pixels of the local photosensitive pixel array are larger than the long sides of the pixels of the readout pixel array, and/or the wide sides of the pixels of the local photosensitive pixel array are larger than the wide sides of the pixels of the readout pixel array.

In one embodiment, the peripheral circuit area and/or the IO pin area of the readout pixel chip are disposed on a target edge side of the readout pixel array, where a size of the readout pixel array on the target edge side is smaller than a size of the local photosensitive pixel array on the target edge side.

In one embodiment, the peripheral circuit areas of the readout pixel chip are distributed and uniformly arranged on four edges of the readout pixel array area, the peripheral circuit area surrounds the readout pixel array area, the IO pin areas are distributed and uniformly arranged on four edges of the peripheral circuit area, and the IO pin areas surround the peripheral circuit area.

In one embodiment, the data interface within the peripheral circuit region employs a CMOS level based parallel interface.

In one embodiment, the bias generation circuit in the peripheral circuit region adopts a distributed bias generation mode.

In one embodiment, the bias generation circuitry within the peripheral circuitry area employs local bias generation circuitry independent of the DAC.

In one embodiment, circuit non-uniformity errors generated by bias circuit mismatch are compensated based on software calibration.

In one embodiment, a fully custom IO interface is employed within the IO pin field.

In one embodiment, a TSV process is adopted in the IO pin area to achieve vertical extraction of signals of the readout pixel chip.

With the pixel detector disclosed in this embodiment, the number of rows and columns of the readout pixel array of the readout pixel chip is the same as the number of columns and rows of the local photosensitive pixel array of the photosensitive pixel chip corresponding to the readout pixel array, and the pixel size of the photosensitive pixel is larger than the pixel size of the readout pixel; the photosensitive pixels and the readout pixels are mapped by a RDL rerouting layer. In this way, when the pixel chips or the pixel detectors are spliced, the occupied areas of the peripheral circuit area and the IO pin area can be partially offset by the area difference between the read pixel array and the corresponding local photosensitive pixel array, and compared with the traditional pixel detector, the pixel detector system which is more beneficial to realizing the low dead area ratio and the high image effective area of the pixel detector system spliced by a large area and a plurality of read pixel chips or pixel detectors. Furthermore, the peripheral circuits and IO pins of the read pixel chips are distributed around the read pixel array, so that the detection dead zone caused by the read pixel chips when a plurality of read pixel chips or pixel detectors are spliced can be further reduced.

Drawings

FIG. 1 is a schematic diagram of a pixel sensor readout pixel chip in the prior art;

FIG. 2 is a schematic diagram of a pixel detector in one embodiment;

FIG. 3 is a schematic diagram of a readout pixel chip of a pixel detector in one embodiment;

FIG. 4 is a schematic diagram of a readout pixel chip of a pixel detector in one embodiment;

FIG. 5 is a schematic diagram of a readout pixel chip of a pixel detector in one embodiment;

FIG. 6 is a schematic diagram of a readout pixel chip of a pixel detector in one embodiment;

fig. 7 is a schematic partial cross-sectional view of a pixel detector in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In the pixel detector in the prior art, the photosensitive pixels and the readout pixels are in one-to-one correspondence, and the shapes and the sizes are basically equal. As shown in fig. 1, the readout pixel chip includes a peripheral circuit area and an IO pin area in addition to the readout pixel array area, and there are no photosensitive pixels on the photosensitive pixel chip corresponding to the areas where the peripheral circuit and the IO pins are located. Therefore, the peripheral circuits and the areas where the IO pins are located will become detection dead zones of the pixel detectors, especially when a plurality of readout pixel chips or pixel detectors are required to be spliced, the detection dead zones between the readout pixel chips will affect the effective imaging area and imaging efficiency.

According to the pixel detector, the detection dead zone of a plurality of read-out pixel chips or pixel detectors during splicing can be effectively reduced, so that the imaging effective area occupation ratio can be remarkably improved. Specifically, the pixel detector may include a photosensitive pixel chip and at least one readout pixel chip, where each readout pixel chip corresponds to a local photosensitive pixel array of the photosensitive pixel chip, and a total number of readout pixels of all readout pixel chips is equal to a number of photosensitive pixels of the photosensitive pixel chip, where a number of rows and columns of the readout pixel array of each readout pixel chip is the same as a number of columns of the corresponding local photosensitive pixel array, and a pixel size of a photosensitive pixel in the local photosensitive pixel array is greater than a pixel size of a readout pixel in the readout pixel array; as shown in fig. 2, the photosensitive pixels and readout pixels may be mapped by a RDL redistribution layer.

The readout pixel chip of the pixel detector may include a readout pixel array region, a peripheral circuit region, and an IO pin region, wherein the readout pixel array region may include a readout pixel array that may be used to convert an optical signal into an electrical signal and read out the charge of each readout pixel; the peripheral circuit region may contain peripheral circuits for amplifying, filtering, processing, and converting signals from the readout pixel array, and may include, in particular, analog signal amplifiers, sampling circuits, digital converters, control logic circuits, and the like; the IO pin field may contain pins for data transfer, control signals, and power/ground connections, which may include data lines, clock lines, reset lines, enable lines, power pins, ground, and the like.

In implementation, in the pixel detector disclosed in this embodiment, the array scale of the photosensitive pixel chip needs to be guaranteed to be consistent with the array scale of the readout pixel chip, that is, the readout pixel array and the corresponding local photosensitive pixel array may have the same row and column numbers, and the pixel size of the photosensitive pixels is greater than the pixel size of the readout pixels.

RDL rewiring layers are commonly used in three-dimensional integrated circuits for connecting electronic components between different layers, which conduct signals from one layer to another through wire and interconnect technology, enabling interconnection between multiple layers. When the sizes of the photosensitive pixel and the readout pixel are not uniform, in order to achieve mapping between the photosensitive pixel and the readout pixel, a RDL redistribution layer may be used to adjust the connection relationship of signals between the two pixels. The RDL rewiring layer can enable signal transfer and conversion between the photosensitive pixels and readout pixels through rewiring and connections. In particular, the RDL rewiring layer may be routed between the local photosensitive pixel array and the readout pixel array, consisting of a series of metal lines and through vias. Through these metal lines and through vias, the RDL redistribution layer may connect the signals of the photosensitive pixels to the corresponding readout pixels to enable mapping of two different sized pixels.

In addition, in routing RDL rewiring layers, the signal transfer requirements between the photosensitive pixels and readout pixels, as well as routing rules and limitations, may be considered, such as ensuring signal correctness, minimizing signal delay, maximizing stability of signal transmission, and the like. Through reasonable design and wiring planning, the RDL rerouting layer can realize mapping and transmission of signals, and normal communication between the photosensitive pixels and the readout pixels is ensured.

In one embodiment, the pixel shapes of the photosensitive pixels and the readout pixels are rectangular; the long side of the photosensitive pixel is larger than the long side of the readout pixel and/or the wide side of the photosensitive pixel is larger than the wide side of the readout pixel.

In one embodiment, the peripheral circuit area and/or the IO pin area of the readout pixel chip are arranged on the target edge side of the readout pixel array, wherein the size of the readout pixel array on the target edge side is smaller than the size of the local photosensitive pixel array on the target edge side.

In one embodiment, as shown in fig. 3, the peripheral circuit region may be distributed uniformly on four edges of the readout pixel array region, and the peripheral circuit region surrounds the readout pixel array region.

Further, as shown in fig. 4, the IO pin areas are distributed and uniformly distributed on four edges of the peripheral circuit area, and the IO pin areas surround the peripheral circuit area.

Compared with the traditional pixel detector, the distributed type pixel detector has the advantages that the peripheral circuit area and the IO pin area are distributed, the occupied widths of the peripheral circuit area and the IO pin area can be effectively reduced, and therefore the detection dead zone caused by reading out the pixel chips when a plurality of pixel detectors are spliced can be reduced.

Specifically, referring to fig. 5, the peripheral circuit region may include a plurality of data buffer units and a plurality of bias circuits. In one case, data buffer units may be respectively provided at four sides of the readout pixel array for respectively storing data of different readout pixels in the readout pixel array. Bias circuits may be provided on either side of the array of readout pixels for providing current or voltage bias for the different readout pixels, respectively. The IO pin area can at least comprise two partitions, each partition comprises high-speed serial data output IO and/or other IO, and the two partitions can be arranged on different sides of the read-out pixel array.

In one embodiment, according to the distributed feature, the interface circuit for data summarizing of the whole readout pixel array can be adjusted to be an interface for data summarizing of the local readout pixel array, and accordingly, the data interface in the peripheral circuit area of the readout pixel chip can be a parallel interface based on CMOS level. Specifically, the peripheral circuit area is distributed on a plurality of edges of the readout pixel array area, and a traditional data interface based on a serializer can be synchronously adjusted to be a parallel interface based on a CMOS level, namely, the parallel interface based on the CMOS level is used for transmitting data according to the specification and the requirement of the readout pixel chip. In detail, the number of parallel data lines and the bandwidth of the parallel interface can be determined according to the maximum data transmission rate defined by the readout pixel chip, the number of data to be transmitted in each clock cycle can be determined according to the bit width of each data bit specified by the readout pixel chip, the data analysis and processing mode can be set according to the data format specified by the readout pixel chip, and the clock frequency and delay of the parallel interface can be designed according to the timing requirement of the data transmission specified by the readout pixel chip. The peripheral circuit area is scattered in a plurality of areas, so that a sufficient data interface can be ensured, a centralized serializer with a relatively large area is not required to be arranged, the size of the area occupied by the peripheral circuit can be greatly reduced, and a plurality of data bits can be simultaneously transmitted by adopting a parallel interface of a CMOS level, so that the data transmission rate can be effectively ensured.

It should be noted that, considering the requirement of parallel data transmission, the peripheral circuit can be optimized and adjusted to ensure that the peripheral circuit and the pins can support high-speed parallel data transmission while maintaining signal integrity and data accuracy. Firstly, a proper power filter and a proper terminal capacitor can be selected to reduce the influence of power noise and ripple on a circuit, and through reasonable ground wire planning and layout, mutual interference among signals is reduced, and shielding and isolation technologies are used to inhibit the influence of electromagnetic interference; secondly, proper signal transmission lines and impedance matching technology can be selected to ensure the quality and stability of signal transmission, or differential signal transmission can be used to improve the anti-interference capability and inhibit common mode interference; thirdly, the distribution and the time sequence control of clock signals are designed to ensure the synchronization and the correctness of the data which are simultaneously received and transmitted; fourthly, a low-power-consumption design and a heat dissipation technology are selected to control the temperature of the circuit so as to improve the stability and the reliability of the system; fifthly, the impedances of the signal source, the transmission line and the receiver are matched so as to minimize the reflection and the power loss of the signal.

In one embodiment, the bias generation circuitry within the peripheral circuitry area of the readout pixel chip employs a distributed-based bias generation approach.

Wherein the bias generation circuit is a circuit for generating a stable current or voltage bias; are commonly used in analog and radio frequency circuits of integrated circuits to ensure stability and linearity performance of the device during operation.

In a readout pixel chip of a conventional pixel detector, a bias generation circuit based on a digital-to-analog converter (DAC) is generally selected and distributed in a centralized manner, and a multi-channel DAC module is used to generate a required bias voltage or bias current. In the peripheral circuit area of the readout pixel chip disclosed in this embodiment, the centralized multi-channel DAC may be split into multiple independent DACs, that is, a distributed bias generation manner is adopted to replace the DAC-based bias generation circuit. Specifically, the bias generation circuits may be distributed in a plurality of partitions of the peripheral circuit region, that is, small bias generation circuits may be added at a plurality of places around the readout pixel array to generate a desired bias current and voltage in the vicinity, and basic elements such as a current mirror, a voltage-controlled current source, etc. may be used to provide an independent bias current and voltage for each readout pixel.

In addition, when the bias generation circuit is routed, the signal lines such as differential signal pairs or clock signals which need to be transmitted simultaneously should be kept as long as possible to reduce the difference of signal arrival time, so as to avoid causing unnecessary phase shift and symmetry misalignment: because adjacent signal wires can generate coupling phenomena, mutual interference and signal distortion are caused, cross coupling can be reduced by increasing the distance between the signal wires, using shielding layers or strata, using differential signal transmission, adopting electromagnetic shielding and other methods; meanwhile, frequent bending or back-and-forth wiring of the signal wire is avoided as much as possible, so that signal transmission delay and instability of a signal path are reduced; in order to provide enough current transmission capability and reduce the resistance of power or ground, a proper line width is selected to ensure good power supply and ground lead, and voltage drop and current noise are reduced; the multi-layer wiring mode can be adopted to plan the purposes and wiring layers of different layers so as to avoid interference and mutual influence between circuits, for example, a high-speed signal and noise sensitive area can be placed in an inner layer, and a power line and a ground line can be placed in a bottom layer; grounding strategies such as single point grounding, star grounding, or zone grounding may be employed to reduce ground potential differences, reduce loop current, and common mode noise.

In one embodiment, the bias generation circuit within the peripheral circuit region of the readout pixel chip employs a DAC independent local bias generation circuit.

In a readout pixel chip of a conventional pixel detector, a bias generation circuit based on a digital-to-analog converter (DAC) is generally selected and distributed in a centralized manner, and a multi-channel DAC module is used to generate a required bias voltage or bias current. In the peripheral circuit region of the readout pixel chip disclosed in this embodiment, the centralized multi-channel DAC may be split into multiple independent DACs, that is, a conventional digital-to-analog converter (DAC) based centralized bias generation circuit is considered to be modified into a simple local bias generation circuit, which may provide a bias for each pixel independently, without depending on the DAC. Specifically, a simple bias current source can be arranged near each readout pixel, such as a differential pair structure or a CMOS current mirror; alternatively, a simple bias voltage source may be provided, such as an amplifier circuit with a negative feedback circuit using a voltage divider circuit.

By using such a simple local bias generation circuit, each readout pixel can independently obtain the required bias without relying on a centralized digital-to-analog converter. Such a design may reduce the complexity of wiring and the need for a large area DAC, which may in turn simplify the layout and connections of the peripheral circuit regions.

In one embodiment, after a distributed bias generation mode or a local bias generation circuit independent of a DAC is selected, circuit inconsistency fixed errors generated by mismatch of bias circuits can be compensated based on software calibration.

The bias circuit mismatch refers to that in the bias circuit, due to the influence of manufacturing process variation, temperature variation, device parameter variation or other factors, key parameters of the bias circuit in different circuit units (such as pixels or sub-circuits) on the same chip are different or inconsistent, so that output difference can be generated between pixels, image quality and sensor performance can be influenced, or power consumption can be unbalanced among different pixels or circuit units, power consumption distribution of the whole chip can be influenced, and meanwhile, working performance of the chip at different temperatures can be changed, so that temperature-related instability exists.

Due to the above-described bias circuit mismatch problems in distributed or local bias generation circuits, there may be some bias or non-uniformity between the readout pixels. To solve this problem, these fixed errors can be compensated by software calibration and digital logic processing. Specifically, a series of sample data of known inputs may first be collected by a sensor and their corresponding output results recorded. The sample data covers bias mismatch conditions that may occur. A mathematical model or table may then be built from the collected sample data to describe the relationship between the known inputs and outputs. Next, the compensation value for each readout pixel can be calculated using the established mathematical model to correct for the fixed error resulting from the bias mismatch. Finally, the calculated compensation value can be applied to the actual pixel data to eliminate fixed errors and obtain a more accurate output result. Therefore, the circuit inconsistency fixed error generated by the mismatch of the bias circuit is compensated through software calibration, so that the precision and stability of the pixel sensor can be improved, and more accurate output data can be obtained.

It is noted that software calibration needs to be done during initial calibration of the readout pixel chip in use, or periodically after use to compensate for fixed errors due to bias mismatch. Furthermore, the accuracy and effectiveness of compensating for bias mismatch will depend on the accuracy of the calibration method and the performance of the compensation algorithm employed.

In one embodiment, a fully custom IO interface is employed within the IO pin area of the readout pixel chip.

In the prior art, existing, verified and packaged reusable IP blocks in an IP library are often used to build circuits when designing integrated circuits. The IP library typically contains circuit modules of different standards, such as clock modules, memory modules, communication interface modules, etc. Some IP modules may need to interact with external environments, such as communicating with external devices or systems, receiving input signals or outputting results, and so on, and thus need to use IO pins to implement connection with the outside world.

The IO pin is a circuit pin of the chip for inputting or outputting an electrical signal between the chip and the external environment. Through the IO pins, the chip may exchange and communicate data with external devices, systems, or other chips. IO pins typically include an input pin, an output pin, a power pin, a ground pin, and the like. When the integrated circuit is designed based on the IP library, IO pins can be reasonably planned and distributed according to the requirements and functions of the IP module.

In this embodiment, the IO pin area is set at a plurality of edges of the readout pixel array area, and a fully customized IO design manner may be adopted, so that the functions and characteristics of the IO circuit are customized according to the needs, so as to achieve higher flexibility and performance. The design of the IO interface circuit, the driver, the input/output pin protection circuit and the like can be particularly included to meet the electrical characteristics and the communication requirements of the chip. Meanwhile, a passivation layer windowing structure of the read pixel chip can be reserved, and a local passivation layer is provided to reduce mutual capacitance and crosstalk. Furthermore, the ESD circuit can be adjusted to the height occupied by the passivation layer windowing structure so as to meet the requirement of the chip on electrostatic discharge protection, and the position is adjusted within the specified height so as to be compatible with the passivation layer windowing structure.

In one embodiment, as shown in fig. 6, the vertical extraction of the signals of the readout pixel chip is implemented in the IO pin area of the readout pixel chip using a TSV process.

The TSV technology is a vertical interconnection technology for packaging and connecting a chip, and vertical through holes are formed by drilling holes in a silicon substrate of the chip, filling conductive materials and electroplating, and the function of the vertical through holes is to vertically lead out and connect electrical signals and power between different layers inside the chip or with the outside.

Since the conventional wire bonding approach is limited by the number of wires and the package layout, the fan-out capability of the chip signal is limited. And the TSV process can lead out signals in the vertical direction, so that the fan-out capability of chip signals is remarkably improved. In addition, the TSV process can provide a shorter and more direct signal transmission path between different layers inside the chip, reduce signal delay and loss, and improve the electrical performance and the working speed of the chip. Meanwhile, the TSV technology adopts a vertical connection channel to lead out signals, and a traditional wire bonding mode is not needed, so that the packaging volume and the packaging height can be reduced, and more compact chip design is realized. Furthermore, the TSV process can provide a more reliable internal chip interconnection mode, so that the problems of lead disconnection, fatigue and fan-out paths which are easy to occur in the traditional lead bonding are avoided, and the reliability and long-term stability of the chip can be improved.

In order to facilitate understanding, fig. 7 shows a partial cross section of a pixel detector in this embodiment, where the partial cross section includes a photosensitive pixel chip and two readout pixel chips, an RDL rewiring layer is disposed between the photosensitive pixel chip and the readout pixel chips, one side of the RDL rewiring layer is connected to the photosensitive pixel chip through a bump, the other side is connected to the readout pixel chip, specifically, a metal pad is disposed below each photosensitive pixel, a metal pad is disposed at a position, opposite to the photosensitive pixel, on an upper side of the RDL rewiring layer, the bump is connected to two metal pads, opposite from top to bottom, where an indium ball or a tin ball may be used for the bump, a metal pad is disposed above each readout pixel, a metal via may be disposed in the RDL rewiring layer, and one-to-one correspondence between the metal pad of each readout pixel and the metal pad of the RDL rewiring layer may be implemented through the metal via. The side of the readout pixel chip may be provided with a vertical via penetrating the readout pixel chip based on the TSV process to enable vertical derivation of the electrical signal.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. The pixel detector is characterized by comprising photosensitive pixel chips and at least one readout pixel chip, wherein each readout pixel chip corresponds to a local photosensitive pixel array of the photosensitive pixel chip, and the total number of readout pixels of all the readout pixel chips is equal to the number of photosensitive pixels of the photosensitive pixel chip, wherein:

The read-out pixel array of each read-out pixel chip is the same as the corresponding local photosensitive pixel array in number of rows and columns, and the pixel size of the photosensitive pixels is larger than that of the read-out pixels;

The photosensitive pixels and the readout pixels are mapped by a RDL rerouting layer.

2. The pixel detector of claim 1, wherein the pixel shapes of the photosensitive pixel and the readout pixel are rectangular;

The long side of the photosensitive pixel is larger than the long side of the pixel of the readout pixel, and/or the wide side of the photosensitive pixel is larger than the wide side of the pixel of the readout pixel.

3. The pixel detector according to claim 2, wherein the peripheral circuit area and/or the IO pin area of the readout pixel chip are disposed on a target edge side of the readout pixel array, and wherein a size of the readout pixel array on the target edge side is smaller than a size of the local photosensitive pixel array on the target edge side.

4. The pixel detector of claim 1, wherein peripheral circuit regions of the readout pixel chip are distributed and uniformly arranged on four edges of the readout pixel array region, the peripheral circuit regions surround the readout pixel array region, the IO pin regions are distributed and uniformly arranged on four edges of the peripheral circuit region, and the IO pin regions surround the peripheral circuit region.

5. The pixel detector of claim 4, wherein the data interface within the peripheral circuit region employs a CMOS level based parallel interface.

6. The pixel detector of claim 4, wherein the bias generation circuitry within the peripheral circuit region employs a distributed-based bias generation scheme.

7. The pixel detector of claim 4, wherein the bias generation circuit within the peripheral circuit region employs a DAC independent local bias generation circuit.

8. The pixel detector of claim 6 or 7, wherein the circuit non-uniformity error due to bias circuit mismatch is compensated based on software calibration.

9. The pixel detector of claim 4, wherein a fully custom IO interface is employed within the IO pin field.

10. The pixel detector of claim 4, wherein the vertical extraction of signals from the readout pixel chip is achieved in the IO pin area using a TSV process.