CN1187694A - Semiconductor memory and its making method - Google Patents
Semiconductor memory and its making method Download PDFInfo
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- CN1187694A CN1187694A CN97116175A CN97116175A CN1187694A CN 1187694 A CN1187694 A CN 1187694A CN 97116175 A CN97116175 A CN 97116175A CN 97116175 A CN97116175 A CN 97116175A CN 1187694 A CN1187694 A CN 1187694A
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Abstract
In a memory unit of DRAM, bit line contact points and memory node contact points are formed, so that no unfavorable condition occurs even if the lamination of photoengraving deflects. In the memory unit of DRAM, for the bit line contact points, an auto-alignment method is used to form contact points going through a nitride film; in the part of the memory node contact points, the contact points are formed by using the deposited nitride film which is an etching barrier layer of the bit line contact points as the side wall of the nitride film.
Description
The present invention relates to form the structure and the manufacture method of the semiconductor memory of the contact hole that device wire uses with self-aligned manner.When particularly being applied to form the structure of bit line contact point (contact) and storage node contacts point and manufacture method with self-aligned manner in the memory cell of DRAM, effect of the present invention is fine.
Fig. 9 is the figure that the structure of the contact point in the conventional semiconductor memory is shown.This Fig. 9 illustrates the cross-section structure of the memory cell part of DRAM, and the state of bit line contact point and storage node contacts point particularly is shown.
In Fig. 9, the 1st, silicon substrate, the 2nd, the element Disengagement zone, the 3rd, gate insulating film, the 4th, the part of the gate electrode that constitutes by conductivity polysilicon etc., the 5th, the part of the gate electrode that constitutes by the compound of refractory metal and silicon, the 6th, gate electrode and be transmission gate, the 7th, silicon oxide film, the 8th, oxide-film sidewall (side wall), 10a is a silicon nitride film, the 11st, and low concentration impurity diffusion region, the 12nd, high concentration impurities diffusion region, the 13rd, another high concentration impurities diffusion region, 14 and 15 is interlayer oxide films, the 16th, and the part of the bit line electrode that constitutes by conductivity polysilicon etc., the 17th, the part of the bit line electrode that the compound of refractory metal and silicon constitutes, the 18th, bit line, the 19th, bit line contact point, the 20th, storage node contacts point, the 21st, memory node.
In the contact point shown in Figure 9, thereby for example consider because photomechanical alignment offset makes storage node contacts point 20 produce the situation of skew.Figure 10 is the storage node contacts point 20 of expression this moment and the figure of the state of the contact portion of substrate 1, and Figure 11 is illustrated in to form the figure of state that storage node contacts is put the contact portion of 20 o'clock storage node contacts point 20 and substrate 1 under the situation that does not produce skew for the purpose of comparison.
Because when photomechanical alignment offset makes storage node contacts point 20 produce skew, storage node contacts point 20 is more approaching with respect to transmission gate 6, as Fig. 9 and shown in Figure 10, pruned at the storage node contacts point 20 and the sidewall 8 of the contact site office grid 6 of substrate 1.
Have again, owing to mix phosphorus impurity such as (P) usually in the conductivity polysilicon that in storage node contacts point 20, uses, when contacting with silicon substrate 1, phosphorus impurity such as (P) diffuses out from this conductivity polysilicon because of heat treatment in the technology thereafter etc., so the structure of transistorized source/leakage is changed.Therefore, as shown in figure 10, since from storage node contacts put impurity that 20 electrode materials such as grade diffuse out so, the width d1 of the low concentration impurity diffusion layer 11 under the width d2 of low concentration impurity diffusion layer 11 and the normal condition shown in Figure 11 compares and diminishes d2＜d1.At this moment, consider the unfavorable condition of degradation under the transistorized withstand voltage properties.
Even under the situation by formation high concentration impurities diffusion regions 13 such as ion injections after storage node contacts is put 20 perforates, owing to when storage node contacts is put 20 perforates, determine to form the position of high concentration impurities diffusion region 13, also produce identical unfavorable condition.That is, under above any situation, all there is the possibility that produces this unfavorable condition in the event of the superimposed precision when putting 20 perforates owing to storage node contacts.
As previously discussed, up to now for example in the memory cell of DRAM, form the bit line contact point by thin for example one deck interlayer oxide film, again by thicker for example two layer by layer between oxide-film when forming storage node contacts point, even be offset and have difficulties aspect the contact point that does not also produce unfavorable condition forming photomechanical superimposed generation that the contact point opening uses.Therefore, exist to produce contacting or the problem of the variation of transistor characteristic etc. of contact point and transmission gate.
The present invention finishes in order to solve this existing problem, the present invention relates to following structures and manufacture method: for example in the memory cell of DRAM, use so-called self aligned approach to form the bit line contact point, simultaneously will be in storage node contacts point part and the nitride film of deposit forms and use as second sidewall as the etching barrier layer of bit line contact point.
That is, semiconductor memory of the present invention is characterised in that: have a plurality of that on the first type surface of Semiconductor substrate, form, have active area and a MOS transistor of the transmission gate that covers with first dielectric film respectively; Between adjacent transmission gate, form second dielectric film that forms in order to cover above-mentioned first dielectric film and active area and connect the 1st contact point that this second dielectric film leads to above-mentioned active area, and between other adjacent transmission gate, only form second dielectric film that forms in order to cover above-mentioned first dielectric film and connect the 2nd contact point that leads to active area between this second dielectric film in the side of above-mentioned transmission gate.
In addition, semiconductor memory of the present invention is characterised in that: above-mentioned Semiconductor substrate forms with Si semiconductor, and above-mentioned the 1st dielectric film forms with silicon oxide film, moreover above-mentioned the 2nd dielectric film forms with silicon nitride film.
In addition, semiconductor memory of the present invention is characterised in that: above-mentioned the 1st contact point is the bit line contact point, and above-mentioned the 2nd contact point is the storage node contacts point.
In addition, the manufacture method of semiconductor memory of the present invention is characterised in that, comprising: form on the first type surface of Semiconductor substrate and a plurality ofly have active area respectively and with the operation of the MOS transistor of the transmission gate of first dielectric film covering; Forming the operation that forms the 2nd dielectric film on the above-mentioned Semiconductor substrate of above-mentioned a plurality of MOS transistor; Between adjacent transmission gate, form and connect the operation that above-mentioned second dielectric film leads to the 1st contact point of above-mentioned active area; Between other adjacent transmission gate, above-mentioned second dielectric film is carried out etching by anisotropic etching, only on above-mentioned the 1st dielectric film of the side of above-mentioned transmission gate, stay second dielectric film, connect the operation that forms the 2nd contact point that leads to other active areas between this second dielectric film.
In addition, the manufacture method of semiconductor memory of the present invention is characterised in that: use Si semiconductor as above-mentioned Semiconductor substrate, form silicon oxide film as above-mentioned first dielectric film, form silicon nitride film as above-mentioned the 2nd dielectric film.
In addition, the manufacture method of semiconductor memory of the present invention is characterised in that: form the bit line contact point as above-mentioned the 1st contact point, form storage node contacts point as above-mentioned the 2nd contact point.
Fig. 1 is the profile of structure of the semiconductor device of expression embodiments of the invention 1.
Fig. 2 is the profile of structure of the semiconductor device of expression embodiments of the invention 1, is the local expanded view that is used to illustrate the relation of transmission gate and contact point.
Fig. 3 is the profile of manufacture method of the semiconductor device of expression embodiments of the invention 2, and expression forms the operation of transmission gate.
Fig. 4 is the profile of manufacture method of the semiconductor device of expression embodiments of the invention 2, and expression forms the operation of the resist of bit line contact point part.
Fig. 5 is the profile of manufacture method of the semiconductor device of expression embodiments of the invention 2, and expression forms the operation of the nitride film of bit line contact point part.
Fig. 6 is the profile of manufacture method of the semiconductor device of expression embodiments of the invention 2, and expression forms the operation of bit line contact point.
Fig. 7 is the profile of manufacture method of the semiconductor device of expression embodiments of the invention 2, and expression forms the operation of bit line.
Fig. 8 is the profile of manufacture method of the semiconductor device of expression embodiments of the invention 2, and expression uses reduced opening technology to form the operation of storage node contacts point.
Fig. 9 is the profile of the structure of expression conventional semiconductor device.
Figure 10 is the profile of the structure of expression conventional semiconductor device, and the expanded view of contact point part is shown.
Figure 11 is the profile of the structure of expression conventional semiconductor device, and the expanded view of contact point part is shown.
Following with reference to the description of drawings embodiments of the invention.In each figure, identical symbol is represented identical or suitable part respectively.
Embodiment 1
Fig. 1 is the profile of structure of the semiconductor memory of expression one embodiment of the present of invention.This Fig. 1 represents the cross-section structure of the memory cell part of DRAM, and the state of bit line contact point and storage node contacts point particularly is shown.
In Fig. 1, the 1st, silicon semiconductor substrate, the 2nd, the element separating insulation film (silicon oxide film) that forms by LOCOS method etc., the 3rd, the gate insulating film that constitutes by silicon thermal oxidation film etc., the 4th, the lower membrane of the transmission gate (being gate electrode simultaneously) that constitutes by conductivity polysilicon etc., the 5th, the upper layer film of the transmission gate that constitutes by the compound that is used to make transmission gate (gate electrode) become low-resistance refractory metal and silicon, the 6th, the transmission gate (being gate electrode simultaneously) that constitutes by upper layer film 4 and lower membrane 5, the 7th, by the dielectric film (silicon oxide film) of formations such as CVD method deposit TEOS, the 8th, constitute by TEOS etc., form the dielectric film (silicon oxide film) of sidewall, the 9th, dielectric film (silicon oxide film), 10a is a silicon nitride film, 10b is the silicon nitride film sidewall, the 11st, the low concentration impurity diffusion region, the 12nd, the high concentration impurities diffusion region, the 13rd, another high concentration impurities diffusion region, 14 and 15 is interlayer dielectric (silicon oxide films), the 16th, the bit line contact point of formations such as conductivity polysilicon and be the lower membrane of bit line electrode, the 17th, the upper layer film of the bit line electrode that the compound of refractory metal and silicon etc. constitute, the 18th, the bit line that constitutes by upper layer film 16 and lower membrane 17, the 19th, bit line contact point (the 1st contact point), the 20th, storage node contacts point (the 2nd contact point), the 21st, memory node.
Wherein, dielectric film (silicon oxide film) 7, dielectric film (silicon oxide film) 8 and dielectric film (silicon oxide film) 9 are made the 1st dielectric film that as a whole formation covers transmission gate 6.In addition, silicon nitride film 10a and silicon nitride film sidewall 10b are formed in the 2nd dielectric film that forms on first dielectric film.Have, low concentration impurity diffusion region 11, high concentration impurities diffusion region 12 and 13 constitute the active area of memory cell transistor again.
Also have, here bit line contact point 19 refers in order to connect bit line 18 carries out opening to interlayer dielectric with the active area that forms on silicon substrate 1 contact hole, and storage node contacts point 20 refers to equally in order to connect memory node 21 carries out opening to interlayer dielectric with the active area that forms on silicon substrate 1 contact hole.
As shown in Figure 1, the formation of memory cell transistor comprises: gate oxidation films 3, gate electrode 6 and be located at its both sides as the active area on the silicon substrate 1 in source/drain region, i.e. low concentration impurity diffusion region 11, high-concentration diffusion region 12 or another high concentration impurities diffusion region 13.On silicon substrate 1 with a plurality of such memory cell transistors of rectangular arrangement.
In addition, form word line, form bit line with wiring layer with gate oxidation films 3 and transmission gate 6.Have the cell board that becomes opposite electrode on the top of memory node 21, the middle dielectric film of getting involved capacitor, but owing in explanation of the present invention, do not relate to this part, so in diagram with its omission.In addition, the structure about memory node 21 illustrates with cylindrical shape here, but in the present invention it is not done special qualification.
Have again, after storage node contacts point 20 is carried out opening, form high concentration impurities diffusion region 13 by implanting impurity ion.In addition, because the material of memory node 21 is the conductivity polysilicons that mixed impurity, so above-mentioned high-concentration diffusion region 13 also can be the impurity diffusion zone that itself spreads from this memory node 21.
In the semiconductor memory that constitutes like this, at first in bit line contact point 19, with the transmission gate (gate electrode) 6 of bit line contact point 19 adjacency in capping oxidation film sidewall 8 and above the oxide-film 9 of oxide-film 7 on make the nitride film 10a that is deposited to necessary thickness extend to top in advance from the side of transmission gate 6.Thereby, even bit line contact point 19 is offset,, contact with bit line 18 so can prevent transmission gate 6 because the etching of interlayer oxide film 14 terminates in nitride film 10a.
In addition, in the semiconductor memory that constitutes like this, in the storage node contacts point 20 of accumulation as the memory node 21 of the electric charge of data, along with storage node contacts point 20 near substrate 1, it is just more and more near transmission gate 6, but, can keep insulation with transmission gate 6 owing to there is the sidewall 10b that constitutes by nitride film.In addition, because memory node 21 forms on the top of bit line 18, so storage node contacts point 20 is necessary to connect interlayer oxide film 14 and 15, form deeplyer, but owing to silicon nitride film only forms as sidewall 10b, only the etching by interlayer oxide film just can form storage node contacts point 20, so that its formation becomes is easy.
Shape about the contact point of above-mentioned bit line and memory node refers again to Fig. 2 and is described in detail.Fig. 2 is the figure that illustrates after the part of transmission gate (gate electrode) 6 of the formation semiconductor memory (DRAM) of Fig. 1 and contact point is enlarged.For the sake of simplicity, the oxide-film 9 of Fig. 1 is incorporated oxide- film 7 and 8 in this Fig. 2, so with its omission.
On the diagram right side, allowance x1 in the bit line contact point part in the design of the interval x3 (size is about 0.35 micron) of adjacent transmission gate 6 and the diameter x4 (size is about 0.25 micron) of bit line contact point has only 0.05 micron, be photomechanical superimposed precision (approximately less than 0.1 micron) pact half.The possibility that therefore, must have bit line contact point and transmission gate 6 short circuits with certain probability.In order to avoid this unfavorable condition, the nitride film 10a that is used for the self-aligned contacts point of bit line contact point part is necessary to stay and extend to original thicker deposition thickness the upside of transmission gate 6.
On the other hand, in illustrated left side, in the part of storage node contacts point, the interval x5 in the design of adjacent transmission gate 6 is about 0.4 micron, forms the storage node contacts point of diameter x6 (size is about 0.3 micron) between this width.The transmission gate 6 of this moment is about 0.05 micron with the allowance x2 of the design of storage node contacts point, the part that the storage node contacts point is pruned sidewall 8, as consider photomechanical superimposed precision (approximately less than 0.1 micron), then must there be the possibility of bit line contact point and transmission gate 6 short circuits with certain probability.But in fact owing to use the reduced hatch method that storage node contacts is carried out opening, so about 0.1 micron of diameter x61 of the storage node contacts point when forming, the allowance of the design of transmission gate 6 and storage node contacts point as illustrating with x21 among Fig. 2, is about 0.15 micron.
In order not make transistorized source/drain structure that big variation is arranged, be necessary to make storage node contacts point 20 not contact with sidewall 8.At this moment, because the width of sidewall 8 is about 0.05 micron,, identical with photomechanical superimposed precision substantially so the interval x 22 of storage node contacts point 20 and sidewall 8 is about 0.1 micron.Hence one can see that, and the nitride film that is used for the self-aligned contacts point of storage node contacts point part is that the film of the sort of degree shown in the nitride film sidewall 10b that forms on the sidewall with the sidewall 8 of transmission gate 6 is just enough.
By the above as can be known, in the semiconductor memory of present embodiment, in bit line contact point one side, stay nitride film that deposit must be thicker on the oxide- film 7,8 of transmission gate 6 as it is to form contact point covering, on the other hand, put a side in storage node contacts, the nitride film 10b that stays thin sidewall shape on the oxide-film sidewall 8 that covers transmission gate 6 is to form contact point.Thus, in both contact points, form contact point not with the transmission gate contacting structure, and form the also indeclinable structure of characteristics of transistor.
In the semiconductor memory of present embodiment, memory cell neutrality line contact point at DRAM becomes the structure of having used so-called self aligned approach, in addition, as the etching barrier layer of bit line contact point and the nitride film of deposit constitutes sidewall in storage node contacts point part.
Because storage node contacts point is compared with the bit line contact point, aspect ratio during etching (degree of depth of contact hole is to the opening diameter ratio) is very big, so hysteresis (lag) because of RIE (reactive ion etching), etching gas does not reach the bottom of contact hole, is easy to generate the unfavorable condition of can not butt contact carrying out opening.As there is the film of the material different with the interlayer film in the bottom of contact hole, then etching becomes more difficult.For example consider on whole, to stay the situation of the nitride film that is used for bit line contact point opening, then stay nitride film in the bottom in storage node contacts point part, initial just to the etching of oxide-film, but at last must be under the state of high aspect ratio the nitride film of etching contact point bottom.As adopt the structure of present embodiment, because the bottom of storage node contacts point does not have nitride film, so can avoid this unfavorable condition.
From Fig. 3 to Fig. 8 is the figure that the manufacture method of the semiconductor memory an alternative embodiment of the invention is shown.
Describe as the manufacture method about present embodiment, at first with reference to Fig. 3, form element Disengagement zone 2 on silicon semiconductor substrate 1, though not shown, the ion that carries out trap, raceway groove suspension layer, channel doping layer etc. injects.Secondly, form gate oxidation films 3, film 5 of the compound of the conductivity polysilicon film 4 of formation formation gate electrode and refractory metal and silicon forms oxide-film 7 on it on it.Moreover, behind etching formation gate electrode 6, by the ion injection formation low concentration impurity diffusion region 11 of phosphorus (P) or arsenic (As) etc.
The side of gate electrode 6 formed sidewall 8 after, desirable zone in by ion inject formation high concentration impurities diffusion region 12 thereafter.This high concentration impurities diffusion region 12 not only can be injected by this ion and form, below in Shuo Ming the operation, also can be from the doping of bit line the diffusion of polysilicon 16 by impurity form.These low concentration impurity diffusion regions 11 and high concentration impurities diffusion region 12 become the active area on the first type surface of silicon substrate 1, become the source/drain region of memory cell transistor.Thereafter, the oxide-film 9 of the about 10～20nm of deposit on whole.Oxide- film 7,8 and 9 integrally constitutes the 1st dielectric film that covers transmission gate 6.Secondly, the deposit thickness is the nitride film 10 of tens nm on oxide-film 9, as the 2nd dielectric film.Oxide-film 9 play prevent because of nitride film 10 directly with active area, be the dysgenic effect that the surface of silicon substrate 1 contacts the stress that causes.
Secondly, as shown in Figure 4, only by photomechanical process resist 22 is carried out pattern etching and stay in the part of plan formation bit line contact point (the 1st contact point).Form this resist 22, make it to extend to upper surface from the side of the transmission gate 6 of the pair of transistor of clamping bit line contact point part.
Secondly, the wafer from Fig. 4 carries out anisotropic etching by reactive ion etching (RIE) to nitride film 10.Thus, as shown in Figure 5, in the bit line contact point part that covers with resist 22, the part of nitride film 10 intactly remains, and remains as the nitride film 10a that to be coated with thickness source region 12, that extend to upper surface from the side of transmission gate 6 through oxide- film 7 and 8 be tens nm.On the other hand, planning to form in the part of storage node contacts point (the 2nd contact point), only on the oxide-film sidewall (the 1st dielectric film) 8 of adjacent transmission gate 6, keep nitride film (the 2nd dielectric film) 10b of thin sidewall shape.
Secondly, as shown in Figure 6,, form the good interlayer oxide film 14 of flatness for the wafer of Fig. 5.
Thereafter, though not shown, on interlayer oxide film 14, apply resist, only the bit line contact hole of interlayer oxide film 14 is partly carried out selectable, anisotropic etching by photoetching process, form the opening that the bit line contact point is used.Secondly, by only nitride film 10a being carried out selectable anisotropic etching, form bit line contact point 19 from this opening portion.So, use so-called self aligned approach to form the bit line contact point.
Secondly, deposit conductivity polysilicon film 16 on the wafer of Fig. 6, deposit thereon is the film 17 of the compound (being designated hereinafter simply as " silicide ") of tungsten (W), titanium (Ti), cobalt refractory metals such as (Co) and silicon for example.Through operations such as photomechanical process, etchings, as shown in Figure 7 form bit line 18 thereafter.Have again, form the flatness good interlayer oxide film 15 identical thereafter with interlayer oxide film 14.
Secondly, as shown in Figure 8,, use the reduced technology that storage node contacts point 20 is carried out opening for the wafer of Fig. 7., in deposit become the conductivity polysilicon of memory node 21 before, by formation high concentration impurities districts 13 such as ion injections thereafter.
Thereafter, deposit becomes the conductivity polysilicon of memory node 21, through several technologies, forms the memory node 21 shown in Fig. 1 etc., has so just formed the structure of the semiconductor device shown in Fig. 1.
Have again, because the material of memory node 21 is the conductivity polysilicons that mixed impurity, so high concentration impurities district 13 itself spreads and the impurity diffusion zone of formation from this memory node 21.
As adopt this method; even be used to form some skew of photomechanical superimposed generation of storage node contacts point 20; put in 20 o'clock the anisotropic etching forming storage node contacts; the oxide-film sidewall 8 of transmission gate 6 be subjected to the outside nitride film sidewall 10b protection and can not be pruned, so can avoid transmission gate 6 and the such unfavorable condition of memory node 21 generation electrical shorts.In addition, by the same token, because of near the Impurity Distribution in the source/drain region the edge of transistorized transmission gate 6 can not change, so can keep the transistor characteristic of memory cell equably.
With among the embodiment 1 with reference to illustrated identical of Fig. 2, because the tolerance limit at bit line contact point 19 and the interval of gate electrode 6 is less than the photomechanical superimposed precision of bit line contact point 19, so must have the overlapping possibility of gate electrode 6 and bit line contact point 19 with certain probability.Thereby, be necessary with part adjacent gate electrodes 6 places that form the bit line contact point, oxide-film sidewall 8 and above oxide-film 7 on, make the nitride film 10a that is deposited to necessary thickness extend to top in advance from the side of gate electrode 6.So, even bit line contact point 19 is offset, but the nitride film 10a that extends to top from the side of gate electrode 6 that is etched in of interlayer oxide film 14 ends, and afterwards nitride film 10a carried out etching and opening.By this nitride film etching, the oxide-film sidewall 8 of grid and the top oxide-film 7 of gate electrode 6 can not pruned, even for example bit line contact point 19 is offset, can prevent that gate electrode 6 from contacting with bit line contact point 20 yet.
On the other hand, owing to when using the reduced hatch method that storage node contacts point 20 is carried out opening, the aperture is dwindled, so gate electrode or transmission gate 6 are roughly identical with photomechanical superimposed precision with the tolerance limit at the interval of storage node contacts point 20.Thereby the nitride film that is used for the self-aligned contacts point of storage node contacts point 20 is that the sort of degree that forms on the sidewall of the oxide-film sidewall 8 of gate electrode or transmission gate 6 is just enough.
Therefore, in the manufacture method of present embodiment, in the memory cell of DRAM, use so-called self aligned approach to form the bit line contact point, simultaneously, form as the etching barrier layer of bit line contact point and the nitride film of deposit, so that locate to become the 2nd sidewall in storage node contacts point part.Thereby deposit simultaneously and formation nitride film as the etching diaphragm of the self-aligned contacts point usefulness in the opening separately of bit line contact point and storage node contacts point, are compared with situation about forming respectively, can reduce the operation number.
Moreover, storage node contacts point is compared with the bit line contact point, and the aspect ratio during etching (degree of depth of contact hole is to the opening diameter ratio) is very big, so because of the influence of hysteresis of RIE etc., etching gas does not reach the bottom of contact hole, is easy to generate the unfavorable condition of can not butt contact carrying out opening.As there is the film of the material different with the interlayer film in the bottom of contact hole, then etching becomes more difficult.For example consider on whole, to stay the situation of the nitride film that bit line contact point opening uses, then stay nitride film in the bottom in storage node contacts point part, interlayer dielectric is carried out etching after, must be under the state of high aspect ratio etching nitride film again.
But,,,, do not need complicated technology so an etching oxidation film gets final product because the bottom of storage node contacts point does not stay nitride film by adopting manufacture method of the present invention.
Therefore, by going up different the 2nd sidewall (nitride film sidewall) of formation material character with transistorized the 1st sidewall (oxide-film sidewall) of storage node contacts point part adjacency, even produce the alignment offset of storage node contacts point 20, the first side wall that is made of oxide-film when storage node contacts point opening can not pruned, can form transistor with uniform properties, in addition, can prevent the short circuit etc. of transmission gate and memory node.
As discussed above, as adopt the present invention, at semiconductor memory, particularly in the memory cell of DRAM, use so-called self aligned approach to form the bit line contact point, simultaneously, form as the etching barrier layer of bit line contact point and the nitride film of deposit, so that locate to become the 2nd sidewall in storage node contacts point part.
Thus, in both contact points,, also can under contact point and the discontiguous situation of transmission gate, form, can form contact point for the substrate active area even superimposed skew takes place.Moreover, as adopt this manufacture method, can obtain the semiconductor memory that the characteristic of memory cell transistor does not also change.
Claims (6)
1. semiconductor memory is characterized in that:
Have a plurality of that on the first type surface of Semiconductor substrate, form, have active area and a MOS transistor of the transmission gate that covers with first dielectric film respectively;
Between adjacent transmission gate, form second dielectric film that forms in order to cover described first dielectric film and active area and connect the 1st contact point that this second dielectric film leads to described active area, and
Between other adjacent transmission gate, only form second dielectric film that forms in order to cover described first dielectric film and connect the 2nd contact point that leads to active area between this second dielectric film in the side of described transmission gate.
Described in the claim 1 semiconductor memory, it is characterized in that: described Semiconductor substrate forms with Si semiconductor, described the 1st dielectric film forms with silicon oxide film, moreover described the 2nd dielectric film forms with silicon nitride film.
Described in the claim 1 or 2 semiconductor memory, it is characterized in that: described the 1st contact point is the bit line contact point, described the 2nd contact point is the storage node contacts point.
4. the manufacture method of a semiconductor memory is characterized in that, comprising:
On the first type surface of Semiconductor substrate, form and a plurality ofly have active area respectively and with the operation of the MOS transistor of the transmission gate of first dielectric film covering;
Forming the operation that forms the 2nd dielectric film on the described Semiconductor substrate of described a plurality of MOS transistor;
Between adjacent transmission gate, form and connect the operation that described second dielectric film leads to the 1st contact point of described active area;
Between other adjacent transmission gate, described second dielectric film is carried out etching by anisotropic etching, only on described the 1st dielectric film of the side of described transmission gate, stay second dielectric film, connect the operation that forms the 2nd contact point that leads to other active areas between this second dielectric film.
Described in the claim 4 the manufacture method of semiconductor memory, it is characterized in that: use Si semiconductor as described Semiconductor substrate, form silicon oxide film, form silicon nitride film as described the 2nd dielectric film as described the 1st dielectric film.
Described in the claim 4 or 5 the manufacture method of semiconductor memory, it is characterized in that: form the bit line contact point as described the 1st contact point, form storage node contacts point as described the 2nd contact point.
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| CN97116175A CN1187694A (en) | 1997-01-09 | 1997-08-08 | Semiconductor memory and its making method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333455C (en) * | 2003-03-14 | 2007-08-22 | 海力士半导体有限公司 | Method for making semiconductor device |
| CN100407425C (en) * | 2003-01-17 | 2008-07-30 | 三星电子株式会社 | Semiconductor device and its manufacturing method |
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1997
- 1997-08-08 CN CN97116175A patent/CN1187694A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100407425C (en) * | 2003-01-17 | 2008-07-30 | 三星电子株式会社 | Semiconductor device and its manufacturing method |
| CN1333455C (en) * | 2003-03-14 | 2007-08-22 | 海力士半导体有限公司 | Method for making semiconductor device |
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