CN1186878C

CN1186878C - Universal clock generator

Info

Publication number: CN1186878C
Application number: CNB021059276A
Authority: CN
Inventors: 方文琪
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2002-04-09
Filing date: 2002-04-09
Publication date: 2005-01-26
Anticipated expiration: 2022-04-09
Also published as: CN1450721A

Abstract

The present invention relates to a universal clock generator which comprises a high-frequency clock area for generating high-frequency clock signals and a low-frequency clock area for generating low-frequency clock signals, wherein the low-frequency clock area comprises at least a delay-locked loop for amplifying the number of the pins of the high-frequency clock signals in the high-frequency clock area. When the number of pins in a high-frequency CPU clock, an SDRAM clock, an AGP clock and a PCI clock is insufficient, the delay-locked loop in the low-frequency clock area can be connected in series so as to replenish the insufficient pins.

Description

Universal clock generator

Technical field

The present invention relates to a kind of clock generator, particularly about a kind of universal clock generator that is common to various motherboard designs.

Background technology

Because in order to cooperate the chipset of various different frameworks and the different demands of PC on the market, the change that the framework of clock generator often also must be at any time.The export structure of a known clock generator 11 is by the various frequencies of this clock generator 11 outputs all elements (for example chipset 12 and DRAM module 13) to the motherboard as Figure 1-1.The export structure of another known clock generator 11 is shown in Fig. 1-2, be to chipset 12 by this clock generator 11 outputs one frequency, give a DRAM buffer 13 by these chipset 12 output reference frequencies again, and further expand the clock pin position number that exports this DRAM module 13 to by this DRAM buffer 13.Compared to the structure of Fig. 1-1, the output of the more convenient control of the structure of Fig. 1-2 DRAM frequency.The export structure of another known clock generator 11 is that clock generator 11 and the DRAM buffer 14 with Fig. 1-2 is bonded in the integrated circuit (IC) as Figure 1-3.

If classify according to the output pin position of clock generator 11 again, be broadly divided into a high frequency clock district 21 and a low-frequency clock district 22, as shown in Figure 2.This low-frequency clock district 22 is the fixing clock pin position of output, for example 48/24MHz clock pin position, 14.318MHz clock pin position and SM bus clock substantially.Relatively, the design of pin positions such as the central processing unit clock that this high frequency clock district 21 produced, SDRAM clock, pci clock and AGP clock is often because the demand or the different design of connecting object of different pin position number (are for example adopted push ﹠amp on the motherboard; The design of pull or open drain), must change its inner design.

In other words, known clock generator 11 cooperates the demand of the different clocks pin position of different elements on the motherboard because of needs, and must constantly revise its inner design, thereby causes higher manufacturing cost and lower product compatibility.In view of the problem that known technology exists, the present invention proposes the universal clock generator of a novelty, to overcome above-mentioned shortcoming.

Summary of the invention

Main purpose of the present invention provides a kind of universal clock generator, can be common to the various clock pin number purpose demands on the motherboard.

Second purpose of the present invention provides a kind of universal clock generator, to reduce the design and the testing cost of motherboard and clock generator designer.

In order to achieve the above object, the present invention discloses a kind of universal clock generator, comprises the low-frequency clock district that a high frequency clock district and that is used to produce high frequency clock signal is used to produce low-frequency clock signal.This low-frequency clock district comprises at least one delay-locked loop, the pin position number of the high frequency clock signal in this high frequency clock district that is used to increase.When the pin number of central processing unit clock, SDRAM clock, AGP clock and the pci clock of high frequency is not enough, then can be connected in series the delay-locked loop this low-frequency clock district in, to supply the pin position of deficiency.In addition, the output clock of this delay-locked loop also can provide the function of buffering, and, then can use power supply starting to set pin position (power-on reset pin) and be set at push-pull type (push ﹠amp for the output pin position with variational high frequency clock (for example central processing unit clock etc.); Pull), open-drain (open drain) or differential output (differentialoutput), with the flexibility that keeps using.

Specifically, the present invention discloses a kind of universal clock generator, and it comprises:

One high frequency clock district is used to produce the clock signal of high frequency; And

One low-frequency clock district is connected to this high frequency clock district, comprises:

One phase-locked loop is used to produce the clock signal of low frequency, and an output fundamental frequency of this phase-locked loop is as the input reference in this high frequency clock district; And

At least one delay-locked loop, its input is connected with the clock pin position in this high frequency clock district, with the pin position number of the high frequency clock signal in this high frequency clock district that increases.

Described low-frequency clock district is connected to an oscillator in addition.

Described low-frequency clock district exports the reference frequency of a fundamental frequency as this high frequency clock district.

The output of described delay-locked loop can feed back to input again, with the number of amplification output pin position.

Described high frequency clock district and low-frequency clock district are designed to two independently integrated circuits.

Described high frequency clock district and low-frequency clock district are the integrated circuits that is integrated into a single-chip.

The output pin position of described high frequency clock can use power supply starting setting pin position setting to be push-pull type, open-drain or differential output.

The present invention also discloses a kind of universal clock generator, comprise a high frequency clock district and a low-frequency clock district, it is characterized in that this low-frequency clock district comprises at least one delay-locked loop, the input of this delay-locked loop is connected with the clock pin position in this high frequency clock district, with the pin position number of the high frequency clock signal in this high frequency clock district that increases.

Description of drawings

Fig. 1-1,1-2,1-3 are known clock generators;

Fig. 2 is known clock generator; And

Fig. 3 is the schematic diagram of universal clock generator of the present invention.

Embodiment

Fig. 3 is the schematic diagram of universal clock generator of the present invention, comprises the oscillator 35 that a low-frequency clock district 31, a high frequency clock district 32 and are connected to low-frequency clock district 31.This high frequency clock district 32 and low-frequency clock district 31 can be designed to two independently integrated circuits or be integrated into a slice integrated circuit in the mode of system single chip.Comprise a phase-locked loop 33 in this low-frequency clock district 31, be connected to oscillator 35, and be used to produce 34/48/24.576MHz clock commonly used and 14.318MHz clock.Also comprise a phase-locked loop in this high frequency clock district 32 37, an output fundamental frequency (for example 14.318MHz) that can utilize the phase-locked loop 33 in this low-frequency clock district 31 is as input reference, and generation central processing unit clock (CLK), SDRAM clock (CLK), AGP clock (CLK) and pci clock (CLK).A wherein technical characterictic of the present invention is to comprise in this low-frequency clock district 31 one can provide the zero-lag clock to cushion delay-locked loop (the Delay Lock Loop of (zero-delay clock buffer); DLL) 34, can be used for duplicating required clock pin position.Therefore just can be connected to the input of the delay-locked loop 34 in this low-frequency clock district 31 in the SDRAM in this high frequency clock district 32 clock pin position, to cooperate the demand of motherboard to the SDRAM clock pin position of varying number.In addition, the output of this delay-locked loop 34 also can be connected to its input again, to expand the number of its output pin position once more.Even, also can comprise more than one delay-locked loop 34 in this low-frequency clock district 31 of Fig. 3, to increase the flexibility on using.In other words, universal clock generator of the present invention can pass through simultaneously in the motherboard of various different designs, and the user only allocates the configuration of the delay-locked loop 34 in this low-frequency clock district 31, can obtain requisite number purpose clock pin position.Also, therefore for the design of motherboard, also can reduce the degree of difficulty in many designs because of the present invention carries out standardization with clock generator.

In addition, the output clock of this delay-locked loop also can provide the function of buffering, and for the output pin position with variational high frequency clock (for example central processing unit clock etc.), then can use power supply starting to set pin position setting and be push-pull type, open-drain or differential output, with the flexibility that keeps using.

Technology contents of the present invention and technical characterstic are open as above, yet those of ordinary skills still may do all replacement and modifications that does not deviate from spirit of the present invention based on instruction of the present invention and enlightenment.Therefore, protection scope of the present invention should be not limited to the disclosed content of embodiment, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by claim.

Claims

1. universal clock generator is characterized in that it comprises:

2. universal clock generator as claimed in claim 1 is characterized in that described low-frequency clock district is connected to an oscillator in addition.

3. as claimed in claim 1 ten thousand kinds of type clock generators is characterized in that described low-frequency clock district exports the reference frequency of a fundamental frequency as this high frequency clock district.

4. as claimed in claim 1 ten thousand kinds of type clock generators is characterized in that the output of described delay-locked loop can feed back to input again, with the number of amplification output pin position.

5. universal clock generator as claimed in claim 1 is characterized in that described high frequency clock district and low-frequency clock district are designed to two independently integrated circuits.

6. universal clock generator as claimed in claim 1 is characterized in that described high frequency clock district and low-frequency clock district are the integrated circuits that is integrated into a single-chip.

7. universal clock generator as claimed in claim 1 is characterized in that the output pin position of described high frequency clock can use power supply starting setting pin position setting to be push-pull type, open-drain or differential output.

8. universal clock generator, comprise a high frequency clock district and a low-frequency clock district, it is characterized in that this low-frequency clock district comprises at least one delay-locked loop, the input of this delay-locked loop is connected with the clock pin position in this high frequency clock district, with the pin position number of the high frequency clock signal in this high frequency clock district that increases.

9. universal clock generator as claimed in claim 8 is characterized in that described low-frequency clock district is connected to an oscillator in addition.

10. universal clock generator as claimed in claim 8 is characterized in that described low-frequency clock district exports the reference frequency of a fundamental frequency as this high frequency clock district.

11. universal clock generator as claimed in claim 8 is characterized in that the output of described delay-locked loop can feed back to input again, with the number of amplification output pin position.

12. universal clock generator as claimed in claim 8 is characterized in that described high frequency clock district and low-frequency clock district are designed to two independently integrated circuits.

13. universal clock generator as claimed in claim 8 is characterized in that described high frequency clock district and low-frequency clock district are the integrated circuits that is integrated into a single-chip.

14. universal clock generator as claimed in claim 8 is characterized in that the output pin position of described high frequency clock can use power supply starting setting pin position setting to be push-pull type, open-drain or differential output.