CN118591277A - Capacitor device and manufacturing method thereof - Google Patents
Capacitor device and manufacturing method thereof Download PDFInfo
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- CN118591277A CN118591277A CN202411065835.5A CN202411065835A CN118591277A CN 118591277 A CN118591277 A CN 118591277A CN 202411065835 A CN202411065835 A CN 202411065835A CN 118591277 A CN118591277 A CN 118591277A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000002131 composite material Substances 0.000 claims abstract description 84
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000010410 layer Substances 0.000 claims description 567
- 239000011229 interlayer Substances 0.000 claims description 62
- 230000015556 catabolic process Effects 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 10
- 230000010287 polarization Effects 0.000 description 8
- 239000007772 electrode material Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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Abstract
The application discloses a capacitor device and a manufacturing method thereof, comprising the following steps: a semiconductor substrate, at least two electrode plate layers and a composite insulating layer; at least two electrode plate layers arranged on the semiconductor substrate, wherein the first electrode plate layer is arranged on the semiconductor substrate, and the second electrode plate layer is arranged on the first electrode plate layer; the composite insulating layer is arranged between the first electrode plate layer and the second electrode plate layer, wherein the composite insulating layer comprises at least two insulating layers and at least one breakdown-preventing dielectric layer. Namely, the application reduces the equivalent thickness of the insulating layers by forming the composite insulating layer composed of at least two insulating layers and at least one breakdown-preventing dielectric layer, thereby effectively improving the capacitance value of the capacitor device and improving the performance of subsequent products.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a capacitor device and a method for manufacturing the capacitor device.
Background
In semiconductor technology, a capacitive device is a device that is widely used. The MIM (metal-insulator-metal) capacitor device is generally composed of three layers, including an upper metal layer, a lower metal layer, and an insulating layer between the upper metal layer and the lower metal layer, where the capacitance is generally increased by increasing the capacitance area, decreasing the thickness of the insulating layer, and connecting multiple MIM capacitors in parallel.
In practical operation, the research and development personnel of the application find that reducing the thickness of the insulating layer or connecting multiple MIM capacitors in parallel can lead to complex process and high cost, and the capacitance of the capacitor device is difficult to improve, thus influencing the performance of subsequent products.
Disclosure of Invention
The invention mainly solves the technical problems that: the capacitor device and the manufacturing method thereof are provided, and the MIM capacitor of the composite insulating layer is formed, so that the capacitance of the capacitor device can be effectively improved under the condition of the same thickness, and the performance of subsequent products is improved.
In order to solve the technical problems, the application adopts a technical scheme that: there is provided a capacitive device comprising: a semiconductor substrate, at least two electrode plate layers and a composite insulating layer; at least two electrode plate layers arranged on the semiconductor substrate, wherein a first electrode plate layer is arranged on the semiconductor substrate, and a second electrode plate layer is arranged on the first electrode plate layer; and the composite insulating layer is arranged between the first electrode plate layer and the second electrode plate layer, and comprises at least two insulating layers and at least one breakdown-preventing dielectric layer.
In one embodiment of the present application, the composite insulating layer includes: a first insulating layer disposed on the first electrode plate layer; the breakdown-preventing dielectric layer is arranged on the first insulating layer; and the second insulating layer is arranged on the breakdown preventing dielectric layer.
In an embodiment of the present application, a dielectric constant of the first insulating layer is equal to a dielectric constant of the second insulating layer, and a dielectric constant of the breakdown preventing dielectric layer is smaller than dielectric constants of the first insulating layer and the second insulating layer.
In an embodiment of the present application, the breakdown preventing dielectric layer is a silicon-rich oxide layer.
In an embodiment of the present application, a thickness of the composite insulating layer in a vertical direction is a first thickness, and a thickness of the breakdown preventing dielectric layer in a vertical direction is a second thickness; and determining the capacitance value of the capacitor device by the first thickness and the second thickness.
In an embodiment of the present application, the capacitance value of the capacitive device is calculated as follows:
wherein, A capacitance value of the capacitive device; A dielectric constant that is an insulating layer between electrode plate layers; s is the area corresponding to the electrode plate layer; k is an electrostatic force constant and is a fixed value; d is the distance between the first electrode plate layer and the second electrode plate layer, namely the thickness of the composite insulating layer; d2 is the thickness of the breakdown preventing dielectric layer; a capacitance value of a capacitor device which is a single insulating layer with the same thickness.
In an embodiment of the present application, the capacitor device further includes: the interlayer dielectric layer is arranged on the second electrode plate layer, and a connecting column is formed in the interlayer dielectric layer, and comprises: a first connection post and a second connection post; the first connecting columns are correspondingly connected with the first electrode plate layers, and the second connecting columns are correspondingly connected with the second electrode plate layers.
In an embodiment of the present application, the interlayer dielectric layer includes a first dielectric layer, a first interlayer dielectric layer, a second dielectric layer, and a second interlayer dielectric layer that are sequentially stacked; the first dielectric layer covers the second electrode plate layer and the composite insulating layer, the first interlayer dielectric layer covers the first dielectric layer, the second dielectric layer covers the first interlayer dielectric layer, and the second interlayer dielectric layer covers the second dielectric layer.
In an embodiment of the application, the connecting column further includes a third connecting column; and the third connecting column is correspondingly connected with the metal layer on the substrate in the semiconductor matrix.
In order to solve the technical problems, the application adopts another technical scheme that: provided is a method of manufacturing a capacitive device, including: providing a semiconductor substrate; forming a first electrode plate layer on the semiconductor substrate; and forming a composite insulating layer on the first electrode plate layer, and further forming a second electrode plate layer on the composite insulating layer, wherein the composite insulating layer comprises at least two insulating layers and at least one breakdown preventing dielectric layer.
In an embodiment of the present application, the forming a composite insulating layer on the first electrode plate layer includes: forming a first insulating layer to cover the first electrode plate layer; forming a breakdown preventing dielectric layer to cover the first insulating layer; forming a second insulating layer to cover the breakdown preventing dielectric layer; the dielectric constant of the first insulating layer is equal to that of the second insulating layer, and the dielectric constant of the breakdown preventing dielectric layer is smaller than that of the first insulating layer and that of the second insulating layer.
In one embodiment of the present application, further comprising: forming an interlayer dielectric layer, and forming a connecting column in the interlayer dielectric layer, wherein the connecting column comprises a first connecting column and a second connecting column; the first connecting columns are correspondingly connected with the first electrode plate layers, and the second connecting columns are correspondingly connected with the second electrode plate layers.
In an embodiment of the present application, the interlayer dielectric layer includes a first dielectric layer, a first interlayer dielectric layer, a second dielectric layer, and a second interlayer dielectric layer; the forming an interlayer dielectric layer comprises the following steps: forming a first dielectric layer to cover the second electrode plate layer and the composite insulating layer; sequentially forming a first interlayer dielectric layer, a second dielectric layer and the second interlayer dielectric layer so as to cover the first dielectric layer and the semiconductor substrate; forming a connection post in the interlayer dielectric layer, wherein the connection post comprises: a first connection post and a second connection post; the first connecting columns are correspondingly connected with the first electrode plate layers, and the second connecting columns are correspondingly connected with the second electrode plate layers.
In an embodiment of the present application, further includes: and forming a third connecting column in the interlayer dielectric layer, wherein the third connecting column is correspondingly connected with the metal layer on the substrate in the semiconductor matrix.
Compared with the prior art, the capacitor device provided by the application comprises a semiconductor substrate, at least two electrode plate layers and a composite insulating layer; at least two electrode plate layers are arranged on the semiconductor substrate, wherein a first electrode plate layer is arranged on the semiconductor substrate, and a second electrode plate layer is arranged on the first electrode plate layer; the composite insulating layer is arranged between the first electrode plate layer and the second electrode plate layer, wherein the composite insulating layer comprises at least two insulating layers and at least one breakdown-preventing dielectric layer. Namely, according to the technical scheme, the composite insulating layer formed by at least two insulating layers is formed, so that the equivalent thickness of the insulating layers is reduced, the capacitance value of the capacitor device is further effectively improved, and the performance of subsequent products is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
fig. 1 is a schematic structural view of a first embodiment of a semiconductor device of the present application;
fig. 2 is a schematic diagram of a second embodiment of a capacitive device according to the present application;
FIG. 3 is a schematic top view of a capacitive device of the present application;
FIG. 4 is a schematic view of a composite insulating layer according to the present application;
FIG. 5 is a flow chart of an embodiment of a method for fabricating a capacitive device according to the present application;
FIG. 6 is a schematic diagram of an embodiment of a semiconductor substrate provided in the present application;
FIG. 7 is a schematic view of an embodiment of the present application for forming a first electrode layer;
FIG. 8 is a schematic diagram of an embodiment of forming a composite insulating layer according to the present application;
FIG. 9 is a schematic view of an embodiment of the present application for forming a second electrode layer;
Fig. 10 is a schematic structural view of an embodiment of forming an interlayer dielectric layer and a connection post in the present application.
In the drawings, a semiconductor body 100, a substrate 110, an insulating dielectric layer 120, a metal layer 121, a third dielectric layer 130, a first electrode plate layer 210, a second electrode plate layer 220, a composite insulating layer 300, a first insulating layer 310, a breakdown preventing dielectric layer 320, a second insulating layer 330, an interlayer dielectric layer 400, a first dielectric layer 410, a first interlayer dielectric layer 420, a second dielectric layer 430, a second interlayer dielectric layer 440, a first connection post 401, a second connection post 402, and a third connection post 403.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Current capacitor devices, in particular MIM capacitor devices, i.e. Metal-Insulator-Metal (MIM) capacitor devices, typically consist of three layers: the device comprises an upper metal layer, a lower metal layer and an insulating layer positioned between the upper metal layer and the lower metal layer; the capacitance of the capacitive device is typically increased by increasing the capacitance area and reducing the thickness of the insulating layer, parallel connection of double and multi-layer MIM capacitors, and by using a middle insulating layer with a high dielectric constant; however, increasing the capacitance area and decreasing the thickness of the insulating layer increases the area of the chip; the parallel connection of the multi-layer MIM capacitor and the adoption of the middle insulating layer with high dielectric constant can lead to complex process, high preparation process requirement and high cost, so that the capacitance value of the MIM capacitor device is increased, which is a technical problem to be solved urgently in the industry at present.
Therefore, the application provides a capacitor device, through forming the capacitor device with the composite insulating layer, wherein the composite insulating layer comprises at least two insulating layers and at least one breakdown preventing dielectric layer, and dielectric constants are different, so that the equivalent thickness of the insulating layers is reduced under the condition of the same thickness, and the capacitance value of the capacitor device can be effectively improved.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present application.
As shown in fig. 1, the capacitive device of the present application includes: a semiconductor substrate 100, at least two electrode plate layers, and a composite insulation 300; at least two electrode plate layers are disposed on the semiconductor substrate, and a composite insulating layer comprising two electrode plate layers, a first insulating layer, a breakdown preventing dielectric layer and a second insulating layer is described as an example, and there are a first electrode plate layer 210, a second electrode plate layer 220, a first insulating layer 310, a breakdown preventing dielectric layer 320 and a second insulating layer 330. The first electrode plate layer 210 is disposed on the semiconductor substrate 100, the composite insulating layer 300 is disposed on the first electrode plate layer 210, and the second electrode plate layer 220 is disposed on the composite insulating layer 300, wherein the composite insulating layer 300 includes a first insulating layer 310, a breakdown preventing dielectric layer 320, and a second insulating layer 330.
In some embodiments, three electrode plates, four electrode plates and other layers of electrode plates may be provided, and corresponding composite insulating layers are respectively provided between the electrode plates, which may be set according to practical situations.
In some embodiments, the anti-breakdown dielectric layer has a certain conductivity, and the conductivity level is a microampere level conductivity level, for example, a microampere level conductive film structure, and has corresponding electromagnetic characteristics, so that charges between the first electrode plate layer and the second electrode plate layer are uniformly distributed to perform balance on an electric field, and the possibility that the composite insulating layer is broken down by polarization is reduced, that is, the risk of polarization damage of the local composite insulating layer is reduced.
In this embodiment, by forming the capacitor device with the composite insulating layer, where the composite insulating layer includes at least two insulating layers and at least one breakdown preventing dielectric layer, under the condition of the same thickness, the equivalent thickness of the insulating layers is reduced, and the capacitance value of the capacitor device can be effectively improved, so as to improve the performance of subsequent products.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a second embodiment of a capacitive device according to the present application.
As shown in fig. 2, a composite insulating layer composed of two electrode plate layers, two insulating layers and one breakdown preventing dielectric layer is illustrated as an example. Including a first electrode plate layer 210, a second electrode plate layer 220, a first insulating layer 310, a breakdown preventing dielectric layer 320, and a second insulating layer 330.
Specifically, the first electrode plate layer 210 is formed on the semiconductor substrate 100, the first insulating layer 310, the breakdown preventing dielectric layer 320, and the second insulating layer 330 are stacked to form the composite insulating layer 300, and the second electrode plate layer 220 is formed on the composite insulating layer 300.
The dielectric constant of the first insulating layer 310 is the same as that of the second insulating layer 330, that is, the material of the first insulating layer may be the same as that of the third insulating layer, and may be a nitride layer or other high K dielectric layer, such as silicon nitride (SiN); the breakdown preventing dielectric layer 320 has a certain conductivity, and the conductivity level is a microampere level, for example, a microampere level conductive film structure, and has a corresponding electromagnetic property, so that charges between the first electrode plate layer and the second electrode plate layer are uniformly distributed to perform balance on an electric field, so as to reduce the possibility of polarization breakdown of the composite insulating layer, i.e., reduce the risk of polarization breakdown of the local composite insulating layer, i.e., the dielectric constant of the breakdown preventing dielectric layer is smaller than those of the first insulating layer and the third insulating layer, wherein the breakdown preventing dielectric layer is a silicon-rich oxide layer, for example, the breakdown preventing dielectric layer is a silicon-rich silicon oxide layer (SRO); in addition, the silicon-rich silicon oxide layer (SRO) is used as one of the oxide layers, has a good adhesion effect, enables the first insulating layer and the second insulating layer to be stably adhered together, improves stability among all material layers, and therefore the anti-breakdown dielectric layer is added in the composite insulating layer, and reliability and capacitance density of the capacitor device can be effectively increased.
And the first electrode plate layer, the composite insulating layer and the second electrode plate layer form a capacitor structure, the capacitor device is a MIM capacitor device, and compared with a capacitor device with a single insulating layer under the condition that the insulating layer has the same thickness, the capacitor device provided by the application reduces the equivalent thickness of the insulating layer, and further effectively improves the capacitance value of the capacitor device.
Further, the capacitor device further includes an interlayer dielectric layer 400, in which a plurality of connection pillars are formed, the connection pillars including a first connection pillar 401 and a second connection pillar 402; the first connection pillars 401 are correspondingly connected to the first electrode plate layer 210, and the second connection pillars 402 are correspondingly connected to the second electrode plate layer 220.
In some embodiments, the first connection post 401 is used as a first pole, and the second connection post is used as a second pole, it is understood that the first pole and the second pole do not designate the positive pole and the negative pole of the power supply, and can be set according to practical situations; for example, the first pole may be grounded GND, while the second pole is connected to the positive terminal; or the first pole may be connected to the positive terminal and the second stage to ground GND.
In some embodiments, a third connection post 403 may be further included, and the third connection post 403 is used to connect to a metal layer on a substrate in a semiconductor base.
In some embodiments, the interlayer dielectric layer 400 includes a first dielectric layer 410, a first interlayer dielectric layer 420, a second dielectric layer 430, and a second interlayer dielectric layer 440, which are sequentially stacked; the first dielectric layer covers the second electrode plate layer and the composite insulating layer, the first interlayer dielectric layer 420 covers the first dielectric layer, the second dielectric layer covers the first interlayer dielectric layer, and the second interlayer dielectric layer covers the second dielectric layer.
In some embodiments, the first interlayer dielectric layer covers portions of the semiconductor substrate, including direct covers, i.e., direct contact covers, and indirect covers, i.e., intermediate, where other dielectric layers may also be present.
Wherein the area of the first electrode plate layer 210 is larger than the area of the second electrode plate layer 220, and the area of the first electrode plate layer 210 is smaller than the area of the semiconductor substrate.
In order to better represent the position of the connecting post, it will be presented in top view.
Referring to fig. 3, fig. 3 is a top view of a capacitor device according to the present application.
As shown in fig. 3, the second electrode plate layer 220 is disposed on the first electrode plate layer 210, the first connection post 401 is located at an edge of the first electrode plate layer 210, and the second connection post 402 is located at an edge of the second electrode plate layer 220.
It is understood that the first connection post 401 and the second connection post 402 may be provided at any position of the corresponding electrode plate layer as long as the positions of the first connection post 401 and the second connection post 402 do not overlap, and the first connection post 401 and the second connection post 402 may be plural.
Further, in order to calculate the capacitance value of the capacitive device, it is necessary to determine the change of the capacitance value by the composite insulating layer.
In some embodiments, in the vertical direction, the thickness of the composite insulating layer is a first thickness, the thickness of the breakdown preventing dielectric layer is a second thickness, wherein the thickness of the first insulating layer is a third thickness, the thickness of the second insulating layer is a fourth thickness, and the sum of the second thickness, the third thickness and the fourth thickness is the first thickness, so that the capacitance value of the capacitive device is determined by the first thickness and the second thickness.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a composite insulating layer according to the present application.
As shown in fig. 4, taking an example that the composite insulating layer includes two insulating layers and one breakdown preventing dielectric layer, the composite insulating layer 300 includes a first insulating layer 310, a breakdown preventing dielectric layer 320 and a second insulating layer 330, and assuming that the thickness of the insulating layer between the electrode layers in the prior art is d, there is: in the vertical direction, that is, the first thickness of the composite insulating layer is d, the third thickness of the first insulating layer is d1, the second thickness of the breakdown preventing dielectric layer is d2, the fourth thickness of the second insulating layer is d3, and the total thickness of the composite insulating layer is d.
Specifically, with respect to the capacitance value C MIM of the MIM capacitor with a single insulating layer in the prior art, the capacitance value of the capacitor in the present application is calculated as follows:
wherein, For the capacitance value of the capacitive device in the present application,The dielectric constant of the insulating layer between the electrode plate layers is that S is the area corresponding to the electrode plate layers, k is the electrostatic force constant and is a fixed value; d2 is the thickness of the breakdown preventing dielectric layer, d is the thickness of the composite insulating layer, namely the distance between the first electrode plate layer and the second electrode plate layer; The capacitance value of the MIM capacitor device is the capacitance value of the MIM capacitor device with a single insulating layer under the same thickness.
Therefore, compared with the capacitance value of the current single insulating layer capacitor device, the capacitance value of the capacitor device is improved。
In this embodiment, by forming the composite insulating layer composed of the multiple insulating layers and the breakdown preventing dielectric layer, the equivalent thickness of the insulating layer is reduced under the condition of the same thickness of the insulating layer, so that the capacitance value of the capacitor device is effectively improved, and the performance of subsequent products is improved.
The application also provides a chip comprising the capacitor device.
The application also provides a manufacturing method of the capacitor device.
Referring to fig. 5, fig. 5 is a schematic flow chart of an embodiment of a method for manufacturing a capacitor device according to the present application.
As shown in fig. 5, the manufacturing method of the capacitor device includes the steps of:
s10, providing a semiconductor substrate.
The semiconductor substrate 100 may include a substrate 110, an insulating dielectric layer 120, and a third dielectric layer 130, where the third dielectric layer may be a single-layer structure or a multi-layer structure, and the third dielectric layer may be made of a semiconductor material, for example, the single-layer structure may be an NDC layer, and the NDC layer is a nitrogen doped silicon carbide film (Nitride Doped Silicon Carbide).
Specifically, an insulating dielectric layer 120 is formed on the substrate 110, a metal layer 121 is formed in the insulating dielectric layer 120, and a third dielectric layer 130 covers the insulating dielectric layer 120 to form the semiconductor body 100.
In some embodiments, the insulating dielectric layer 120 may be an oxide layer, wherein the metal layer 121 is formed on a side of the insulating dielectric layer 120 adjacent to the third dielectric layer.
S20, forming a first electrode plate layer on the semiconductor substrate.
Specifically, a conductive material is covered on the semiconductor substrate 100 to form a first electrode plate layer 210.
S30, forming a composite insulating layer on the first electrode plate layer, and further forming a second electrode plate layer on the composite insulating layer, wherein the composite insulating layer comprises at least two insulating layers and at least one breakdown preventing dielectric layer.
The composite insulating layer is formed by combining a plurality of insulating layers and anti-breakdown dielectric layers, and the dielectric constant of the anti-breakdown dielectric layers is smaller than that of the insulating layers; the material of the first electrode plate layer is conductive material, such as TiN layer.
Specifically, after the first electrode plate layer is formed, at least two insulating layers and at least one breakdown preventing dielectric layer are formed on the first electrode plate layer, so that a composite insulating layer is formed, and a conductive material is covered on the composite insulating layer to form the second electrode plate layer.
The breakdown-preventing dielectric layer has certain conductivity, the conductivity level is microampere-level conductivity level, for example, the microampere-level conductivity film structure has corresponding electromagnetic characteristics, so that charges between the first electrode plate layer and the second electrode plate layer are uniformly distributed to balance an electric field, the possibility that the composite insulating layer is broken down by polarization is reduced, and the risk of polarization damage of the local composite insulating layer is reduced.
According to the application, the composite insulating layer comprising at least two insulating layers and at least one breakdown preventing dielectric layer is formed between the electrode plate layers, so that the equivalent thickness of the insulating layers is reduced under the condition of the same thickness of the insulating layers, and the capacitance value of the capacitor device is effectively improved, so that the performance of subsequent products is improved.
Hereinafter, a manufacturing method will be described in connection with a device structure, and a capacitor device will be described by taking a composite insulating layer including a first electrode plate layer, a first insulating layer, a breakdown preventing dielectric layer, and a second insulating layer, and a second electrode plate layer as an example.
A semiconductor substrate is provided.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a semiconductor substrate according to the present application.
As shown in fig. 6, an insulating dielectric layer 120 is covered on a substrate 110, and a third dielectric layer 130 is further formed on the insulating dielectric layer 120 to form a semiconductor body 100.
In some embodiments, the insulating dielectric layer 120 is formed on the substrate 110, and the metal layer 121 is formed in the insulating dielectric layer 120, where the metal layer 121 may be a plurality of layers and may be set according to practical situations.
In some embodiments, the third dielectric layer 130 may be replaced or not provided. In some embodiments, the semiconductor body may comprise only the substrate, and the metal layer may be formed directly over the substrate.
Then, a first electrode plate layer is formed on the semiconductor substrate.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of forming a first electrode plate layer according to the present application.
As shown in fig. 7, a first electrode material layer is formed on the semiconductor substrate 100, and a portion of the first electrode material layer is removed, and the remaining first electrode material layer is used as a first electrode layer 210, wherein a portion of the first electrode material layer is removed corresponding to the metal layer 121 on the substrate in the semiconductor substrate, so that a connection post is formed to lead out the metal layer 121.
Next, a composite insulating layer is formed on the first electrode plate layer.
Referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of forming a composite insulating layer according to the present application.
As shown in fig. 8, taking a composite insulating layer formed by two insulating layers and one breakdown preventing dielectric layer as an example, there are a first insulating layer 310 formed on the first electrode plate layer 210 in sequence, a breakdown preventing dielectric layer 320 formed on the first insulating layer 310, a second insulating layer 330 formed on the breakdown preventing dielectric layer 320, and a composite insulating layer 300 formed by the first insulating layer 310, the breakdown preventing dielectric layer 320 and the second insulating layer 330; wherein the dielectric constants of the first insulating layer and the second insulating layer are equal to those of the first insulating layer, the dielectric constant of the breakdown preventing dielectric layer is smaller than those of the first insulating layer and the third insulating layer, the breakdown preventing dielectric layer has certain conductivity, the conductivity level is microampere level, for example, microampere level conductive film structure, has corresponding electromagnetic property, the electric charges between the first electrode plate layer and the second electrode plate layer are uniformly distributed so as to balance an electric field, the possibility that the composite insulating layer is broken down by polarization is reduced, namely the risk of polarization damage of the partial composite insulating layer is reduced, and the equivalent thickness of the insulating layer is reduced under the condition of the same thickness of the insulating layer, so that the capacitance value of the capacitor device is effectively improved.
Then, a second electrode plate layer is formed on the composite insulating layer.
Referring to fig. 9, fig. 9 is a schematic structural view of an embodiment of forming a second electrode plate layer according to the present application.
As shown in fig. 9, on the basis of fig. 8, a second electrode material layer is formed on the composite insulating layer 300, a portion of the second electrode material layer is removed, and the remaining second electrode material layer is used as the second electrode plate layer 220, wherein the second electrode plate layer covers a portion of the composite insulating layer so that another portion of the composite insulating layer is exposed.
Further, an interlayer dielectric layer is formed, and a connection post is formed in the interlayer dielectric layer.
Referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of forming an interlayer dielectric layer and a connection pillar according to the present application.
As shown in fig. 10, an interlayer dielectric layer 400 is formed on the basis of fig. 9, wherein the interlayer dielectric layer 400 includes a first dielectric layer 410, a first interlayer dielectric layer 420, a second dielectric layer 430, and a second interlayer dielectric layer 440.
The second dielectric layer is a nitride layer, can be of a single-layer structure, can also be of a double-layer or multi-layer structure, can be a SiN layer in the single-layer structure, and can be of a double-layer structure formed by adding the SiN layer into the TiN layer in the double-layer structure; the first and second interlayer dielectric layers are compound layers such as Tetraethoxysilane (TEOS) and the second dielectric layer is a nitride layer such as silicon nitride layer (SiN).
Specifically, a first dielectric layer 410 is formed on the second electrode plate layer to cover the second electrode plate layer and the exposed composite insulating layer, and then a first interlayer dielectric layer 420 is formed on the first dielectric layer 410 to cover the first dielectric layer and a portion of the semiconductor substrate, such as a corresponding portion of the semiconductor substrate of the metal layer 121, then a second dielectric layer 430 is formed on the first interlayer dielectric layer 420, and a second interlayer dielectric layer 440 is formed on the second dielectric layer 430.
In some embodiments, the surface area of the first electrode plate layer is smaller than the surface area of the semiconductor substrate, and the surface area of the second electrode plate layer is smaller than the surface area of the first electrode plate layer, so that the first interlayer dielectric layer needs to cover the semiconductor substrate, the first electrode plate layer and the second electrode plate layer, and the first dielectric layer covers the first interlayer dielectric layer and the second interlayer dielectric layer covers the first dielectric layer.
Then, a through hole is formed by etching, and a conductive material is filled in the through hole to form a first connecting column 401 and a second connecting column 402, wherein the first connecting column 401 is correspondingly connected with the first electrode plate layer 210, and the second connecting column 402 is correspondingly connected with the second electrode plate layer 220.
In some embodiments, a third connection post 403 may also be formed at a location corresponding to the metal layer on the substrate in the semiconductor body, wherein the third connection post corresponds to the metal layer 121 on the substrate in the semiconductor body.
The capacitor device prepared by the embodiment forms the composite insulating layer formed by at least two insulating layers and at least one breakdown preventing dielectric layer, so that the equivalent thickness of the insulating layers is reduced under the condition of the same thickness of the insulating layers, and the capacitance value of the capacitor device is further effectively improved, and the performance of subsequent products is improved.
The foregoing description is only of embodiments of the present invention, and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.
Claims (15)
1. A capacitive device, comprising:
a semiconductor substrate;
at least two electrode plate layers arranged on the semiconductor substrate, wherein a first electrode plate layer is arranged on the semiconductor substrate, and a second electrode plate layer is arranged on the first electrode plate layer;
And the composite insulating layer is arranged between the first electrode plate layer and the second electrode plate layer, and comprises at least two insulating layers and at least one breakdown-preventing dielectric layer.
2. The capacitive device of claim 1, wherein,
The composite insulating layer includes:
a first insulating layer disposed on the first electrode plate layer;
The breakdown-preventing dielectric layer is arranged on the first insulating layer;
And the second insulating layer is arranged on the breakdown preventing dielectric layer.
3. The capacitive device of claim 2, wherein,
The dielectric constant of the first insulating layer is equal to that of the second insulating layer, and the dielectric constant of the breakdown preventing dielectric layer is smaller than that of the first insulating layer and that of the second insulating layer.
4. The capacitive device of claim 1, wherein,
The breakdown preventing dielectric layer is a silicon-rich oxide layer.
5. The capacitive device of claim 1, wherein,
The thickness of the composite insulating layer in the vertical direction is a first thickness, and the thickness of the breakdown preventing dielectric layer in the vertical direction is a second thickness;
And determining the capacitance value of the capacitor device by the first thickness and the second thickness.
6. The capacitive device of claim 5, wherein,
The capacitance value of the capacitive device is calculated as follows:
wherein, A capacitance value of the capacitive device; A dielectric constant that is an insulating layer between electrode plate layers; s is the area corresponding to the electrode plate layer; k is an electrostatic force constant and is a fixed value; d is the distance between the first electrode plate layer and the second electrode plate layer, namely the thickness of the composite insulating layer; d2 is the thickness of the breakdown preventing dielectric layer; a capacitance value of a capacitor device which is a single insulating layer with the same thickness.
7. The capacitive device of claim 1, wherein,
The capacitive device further includes:
the interlayer dielectric layer is arranged on the second electrode plate layer, and a connecting column is formed in the interlayer dielectric layer, and comprises: a first connection post and a second connection post;
The first connecting columns are correspondingly connected with the first electrode plate layers, and the second connecting columns are correspondingly connected with the second electrode plate layers.
8. The capacitive device of claim 7, wherein,
The interlayer dielectric layer comprises a first dielectric layer, a first interlayer dielectric layer, a second dielectric layer and a second interlayer dielectric layer which are sequentially stacked;
The first dielectric layer covers the second electrode plate layer and the composite insulating layer, the first interlayer dielectric layer covers the first dielectric layer, the second dielectric layer covers the first interlayer dielectric layer, and the second interlayer dielectric layer covers the second dielectric layer.
9. The capacitive device of claim 7, wherein,
The connecting column further comprises a third connecting column;
and the third connecting column is correspondingly connected with the metal layer on the substrate in the semiconductor matrix.
10. A method for manufacturing a capacitor device is characterized in that,
Providing a semiconductor substrate;
Forming a first electrode plate layer on the semiconductor substrate;
and forming a composite insulating layer on the first electrode plate layer, and further forming a second electrode plate layer on the composite insulating layer, wherein the composite insulating layer comprises at least two insulating layers and at least one breakdown preventing dielectric layer.
11. The method of manufacturing according to claim 10, wherein,
The forming a composite insulating layer on the first electrode plate layer includes:
forming a first insulating layer to cover the first electrode plate layer;
Forming a breakdown preventing dielectric layer to cover the first insulating layer;
And forming a second insulating layer to cover the breakdown preventing dielectric layer.
12. The method of manufacturing according to claim 11, wherein,
The dielectric constant of the first insulating layer is equal to that of the second insulating layer, and the dielectric constant of the breakdown preventing dielectric layer is smaller than that of the first insulating layer and that of the second insulating layer.
13. The method of manufacturing according to claim 10, characterized by further comprising:
Forming an interlayer dielectric layer, and forming a connecting column in the interlayer dielectric layer, wherein the connecting column comprises a first connecting column and a second connecting column;
The first connecting columns are correspondingly connected with the first electrode plate layers, and the second connecting columns are correspondingly connected with the second electrode plate layers.
14. The method of manufacturing according to claim 13, wherein,
The interlayer dielectric layer comprises a first dielectric layer, a first interlayer dielectric layer, a second dielectric layer and a second interlayer dielectric layer;
the forming an interlayer dielectric layer comprises the following steps:
forming a first dielectric layer to cover the second electrode plate layer and the composite insulating layer;
Sequentially forming a first interlayer dielectric layer, a second dielectric layer and the second interlayer dielectric layer so as to cover the first dielectric layer and the semiconductor substrate;
forming a connection post in the interlayer dielectric layer, wherein the connection post comprises: a first connection post and a second connection post; the first connecting columns are correspondingly connected with the first electrode plate layers, and the second connecting columns are correspondingly connected with the second electrode plate layers.
15. The method of manufacturing according to claim 14, further comprising:
And forming a third connecting column in the interlayer dielectric layer, wherein the third connecting column is correspondingly connected with the metal layer on the substrate in the semiconductor matrix.
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| CN202411065835.5A CN118591277A (en) | 2024-08-05 | 2024-08-05 | Capacitor device and manufacturing method thereof |
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