CN118585141A - Memory and data processing method thereof - Google Patents
Memory and data processing method thereof Download PDFInfo
- Publication number
- CN118585141A CN118585141A CN202411067359.0A CN202411067359A CN118585141A CN 118585141 A CN118585141 A CN 118585141A CN 202411067359 A CN202411067359 A CN 202411067359A CN 118585141 A CN118585141 A CN 118585141A
- Authority
- CN
- China
- Prior art keywords
- data
- host data
- host
- physical address
- certain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 12
- 239000000872 buffer Substances 0.000 claims abstract description 111
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 15
- 238000013506 data mapping Methods 0.000 claims description 32
- 238000013507 mapping Methods 0.000 claims description 14
- 238000012005 ligant binding assay Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 12
- 238000012545 processing Methods 0.000 description 9
- 101000648827 Homo sapiens TPR and ankyrin repeat-containing protein 1 Proteins 0.000 description 6
- 102100028173 TPR and ankyrin repeat-containing protein 1 Human genes 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000005192 partition Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a memory and a data processing method thereof, wherein the memory comprises: the flash memory comprises a plurality of blocks for storing host data; and the main controller is electrically connected with the flash memory and is used for distributing a physical address and a write cache area for the host data in the writing process of the host data; in the writing process of a batch of host data, the main controller allocates a physical address and a writing buffer area for a certain host data, counts other host data which are completely the same as the certain host data in the batch of host data, shares the same physical address and the writing buffer area with the other host data and writes the other host data and the certain host data into the flash memory. The invention can improve the writing efficiency of host data in the host to the memory, and can improve the service performance and service life of the memory.
Description
Technical Field
The invention relates to the technical field of static storage, in particular to a memory and a data processing method thereof.
Background
Memory chips are a specific application of the concept of embedded system chips in the memory industry. Whether a system chip or a memory chip, the system chip and the memory chip are realized by embedding software in a single chip, so that the system chip can realize multifunction, high performance and support to various protocols, various hardware and different applications. The memory chip is widely applied to the fields of computers, mobile equipment, internet of things and the like, and is used for storing various data such as an operating system, application programs, music, videos, photos and the like.
The service performance of the storage data in the flash memory of the storage chip is influenced by the data writing performance, and the condition that the operation of the storage system is slow can occur due to the poor writing performance of the storage chip at present. Therefore, there is a need for improvement.
Disclosure of Invention
The invention provides a memory and a data processing method thereof, which are used for solving the technical problem that the operation of a memory system is slow when the writing performance of the current memory chip is poor.
The invention provides a memory, comprising:
the flash memory comprises a plurality of blocks for storing host data; and
The main controller is electrically connected with the flash memory and is used for distributing a physical address and a write buffer area for the host data in the writing process of the host data;
in the writing process of a batch of host data, the main controller allocates a physical address and a writing buffer area for a certain host data, counts other host data which are completely the same as the certain host data in the batch of host data, shares the same physical address and the writing buffer area with the other host data, and then writes the other host data and the certain host data into the flash memory.
In one embodiment of the present invention, the flash memory is configured to store a data mapping table, where the data mapping table stores mapping information of logical addresses and physical addresses of host data;
The main controller associates the same physical address and the same write buffer for a plurality of logical addresses corresponding to other host data and a certain host data.
In one embodiment of the invention, a data register is arranged in the main controller, and a repeated data identification bit and a write buffer zone bit are arranged in the data register;
The repeated data flag bit represents whether the repeated data flag bit has information of other host data which is completely the same as a certain host data in a batch of host data, and the writing buffer bit represents the serial number of the writing buffer area associated with the certain host data.
In one embodiment of the present invention, after the host controller allocates a physical address and a write buffer for a certain host data, when counting that the batch of host data has other host data completely identical to the certain host data, the host controller sets a duplicate data identification bit in the data register;
After the main controller allocates a physical address and a write buffer area for a certain host data, when the statistics is carried out on the host data of the batch, and other host data which has the same data as the certain host data does not exist in the host data of the batch, the repeated data identification bit in the data register is not set.
In one embodiment of the present invention, after the main control sets the repeated data identification bit in the data register, the main control shares the physical address and the write buffer of a certain host data with other host data;
And after the main control does not set the repeated data identification bit in the data register, a new physical address and a new write buffer area are allocated for the data of another host.
The invention also provides a data processing method of the memory, which comprises the following steps:
Host data written by a host are received and stored in a plurality of blocks of the flash memory;
in the writing process of host data of a batch, a physical address and a writing buffer area are allocated for a certain host data;
In the batch of host data, other host data which is completely the same as a certain host data is counted, and the other host data and the certain host data share the same physical address and write buffer;
And writing other host data and certain host data into the flash memory.
In one embodiment of the present invention, after the step of counting other host data that is identical to a certain host data in the batch of host data and sharing the physical address and the write buffer of the certain host data with the other host data, the method includes:
storing a data mapping table into the flash memory, wherein the data mapping table stores mapping information of a logical address and a physical address of host data;
for a plurality of logical addresses corresponding to other host data and a certain host data, the same physical address and the same write buffer are associated.
In one embodiment of the present invention, after the step of counting other host data identical to a certain host data in the batch of host data, the method includes:
In a batch of host data, characterizing information whether other host data which is identical to a certain host data exists as repeated data flag bits;
and characterizing the serial number of the write buffer area associated with one host data as a write buffer area bit.
In one embodiment of the present invention, after the step of characterizing whether the information identical to a certain host data in a batch of host data is repeated as a repeated data flag bit, the method includes:
after a physical address and a write buffer area are allocated for a certain host data, when other host data with the same data as the certain host data in the batch of host data is detected, setting the repeated data identification bit;
After a physical address and a write buffer area are allocated to a certain host data, when other host data which is the same as the certain host data does not exist in the batch of host data, the repeated data identification bit is not set.
In one embodiment of the present invention, the step of sharing the physical address and the write buffer of a certain host data with other host data includes:
after setting the repeated data identification bit in the data register, sharing the physical address and the write buffer area of one host data with other host data;
After the repeated data identification bit in the data register is not set, a new physical address and a new write buffer area are allocated for the data of another host.
The invention has the beneficial effects that: the memory and the data processing method thereof can improve the writing efficiency of host data in a host to the memory, and can improve the service performance and the service life of the memory.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a memory according to an embodiment of the invention.
FIG. 2 is a diagram of write host data for a memory according to the prior art.
Fig. 3 is a schematic diagram of write host data of a memory according to an embodiment of the invention.
Fig. 4 is a schematic diagram illustrating steps of a data processing method of a memory according to an embodiment of the invention.
Fig. 5 is a schematic diagram illustrating steps after step S30 in fig. 4 according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating steps after step S30 in fig. 4 according to another embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating steps after step S321 in fig. 6 according to an embodiment of the present invention.
Reference numerals illustrate: 10. a host; 20. a memory; 30. a main controller; 31. a central processing unit; 32. a direct memory access unit; 40. a flash memory; 41. a block; 42. pages.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
Referring to fig. 1 to 7, the present invention provides a memory and a data processing method thereof, which can be applied to memory devices such as eMMC (Embedded Multi MEDIA CARD), SSD (Solid STATE DISK ), UFS (Univeral Flash Storage, universal flash memory) and the like. In the process of writing host data, when the host data has repeated data, the repeated data share a physical address and a writing buffer area, and the host data refers to application data written by the host 10. The present invention can store the repeated data in the flash memory 40 under the operation of writing the flash memory 40 at one time. The invention can improve the writing efficiency of host data in the host 10 to the memory 20, and can further improve the service performance and service life of the memory 20. The following is a detailed description of specific embodiments.
Referring to fig. 1, in an embodiment of the present invention, a memory 20 is provided, the memory 20 is provided with a bus interface, the memory 20 is electrically connected to a host 10 through the bus interface, the host 10 can write host data and send commands to the memory 20, or the host 10 can read host data and receive commands from the memory 20. The host 10 may be a communication device such as a personal computer (PC, personal Computer), a tablet (Pad), a mobile Phone (Cell Phone), etc.
Referring to fig. 1, in one embodiment of the present invention, a memory 20 may include a main controller 30 and a flash memory 40. The flash memory 40 is a nonvolatile memory, and is generally used for storing host data, system programs, and the like. The main controller 30 is mainly used for operating and managing the flash Memory 40, and the main controller 30 also provides functions of Cache (Cache), memory array (Memory array), and interleaving (interleaving). The main controller 30 is electrically connected to the flash memory 40, and the main controller 30 can control various functions of the flash memory 40, such as bad fast management, wear leveling, error Checking and Correction (ECC), etc., and the main controller 30 can greatly improve the read-write and moving performance of host data in the flash memory 40.
Referring to fig. 1, in an embodiment of the present invention, a flash memory interface is disposed on a main controller 30 inside a memory 20, and the main controller 30 is electrically connected to a flash memory 40 through the flash memory interface. The main controller 30 may include a central processing unit (CPU, central Processing Unit) 31 and a direct memory access unit (DMA, direct Memory Access) 32, the central processing unit 31 being an operation core and a control core of the memory device, such as allocating physical addresses (PBA, physics Block Address) and write buffers (WriteBuf) for host data. The direct memory access unit 32 is used for transferring host data and does not need to occupy the central processing unit 31. The direct memory access unit 32 can handle other things when transmitting host data, and the central processing unit 31 works in a similar way to multithreading.
Specifically, the physical address is a real address corresponding to the block 41 in the flash memory 40, which is also referred to as a real address. Corresponding to the physical address is a logical address (LBA, logical Block Address), which refers to a relative address used in the user program, also referred to as a virtual address, which is generated by the central processing unit 31 for accessing data in the flash memory 40. For host data to be written into the flash memory 40 by the host controller 30, the host data may be temporarily stored in the write buffer, and then written into the flash memory 40 at a low speed.
Referring to fig. 1, in one embodiment of the present invention, the flash memory 40 may include a plurality of blocks (blocks) 41, the blocks 41 may be used to store data mapping tables (L2P, logic Block Address to Physical Block Address Table and host data written by the host 10. One Block 41 may also include a plurality of pages (pages) 42. The data mapping tables store mapping information of logical addresses and physical addresses of the host data. The mapping information in the data mapping tables is queried by using the logical addresses, so that corresponding physical addresses can be found, and then the host data on the corresponding physical addresses in the flash memory 40 is read, written, moved, etc.
Specifically, in the case where the host 10 writes host data to the memory 20, the central processing unit 31 allocates a physical address and a write buffer to the host data. Under the action of the direct memory access unit 32, host data is first stored in the write buffer, then the host data in the write buffer is rewritten in the flash memory 40, and then the memory space on the write buffer can be released, and mapping information between the logical address and the physical address associated with the host data is recorded. In the case that the host 10 reads the host data from the memory 20, after the host 10 reads a certain logical address, the memory 20 may search the data mapping table, find a physical address corresponding to the certain logical address, read the storage data on the physical address, and transfer the storage data to the host 10.
Table 1, partition table of user space
In one embodiment of the present invention, as shown in Table 1, the user space may be divided into LBAs 0-LBA (M-1) in units of 512 bytes.
Table 2, dividing Table of flash memory 40 positions
In one embodiment of the present invention, as shown in Table 2, the flash memory 40 locations may be partitioned into PBA0-PBA (N-1) in units of 512 bytes, with N+.gtoreq.M.
TABLE 3 partition Table for write buffer
In one embodiment of the present invention, as shown in Table 3, the write buffer may be divided into Buf 0-Buf (L-1) in units of 512 bytes.
A mapping between a logical address and a physical address may be represented using a data mapping entry in the following format:
The memory 20 records and updates a data mapping Table (L2P Table), in which one logical address (LBA) corresponds to one physical address (LBA), a written logical address has a physical address corresponding thereto, and a logical address not written has no physical address corresponding thereto, and the format of the data mapping Table (L2P Table) is as follows:
Table 4, initial state of data mapping table
In the prior art, as shown in fig. 2, in the case where the host 10 writes host data to the memory 20, for example, logical addresses corresponding to the host 10 writing host data are LBA0-LBA (M-1), and host data corresponding to logical addresses of LBA0-LBA7 are the same, (M-1) > 7. At this time, the cpu 31 may be the logical addresses of LBA0-LBA7, and may allocate 8 physical addresses and 8 write buffers. The physical addresses may be PBA4, PBA5, PBA6, PBA7, PBA8, PBA9, PBA10, and PBA11, and the write buffers may be Buf2, buf3, buf4, buf5, buf6, buf7, buf8, and Buf9.
Specifically, as shown in fig. 2, first, under the action of the direct memory access unit 32, host data is first stored in the write buffer, where LBA0 corresponds to Buf2, LBA1 corresponds to Buf3, … …, and LBA7 corresponds to Buf9. Secondly, host data in the write buffer is rewritten into the flash memory 40, buf2 corresponds to PBA4, buf3 corresponds to PBA5, … …, and Buf9 corresponds to PBA11. The storage space on the write buffer may then be freed and mapping information between the logical and physical addresses associated with the host data recorded. The information in the data mapping Table (L2P Table) is as follows:
Table 5, first state of data mapping table
As can be seen from the above data mapping Table (L2P Table), the physical addresses corresponding to the logical addresses of LBAs 0-LBA7 are PBA4-PBA11. In the prior art, in the process of writing host data into the memory 20 by the host 10, even if the corresponding 8 host data on the logical addresses LBA0-LBA7 are the same data, 8 physical addresses and 8 write buffers are required, and multiple writes to the flash memory 40 are required. The speed at which host 10 writes host data is limited by the number of physical addresses, the size of the write buffer, and the time to write to flash memory 40.
In the prior art, as shown in fig. 2, when the host 10 reads host data from the memory 20, after the host 10 reads a certain logical address as LBA1, the memory 20 can search the data mapping Table (L2P Table), find the physical address PBA5 corresponding to the logical address as LBA1, read the storage data on the physical address PBA5, and transmit the storage data to the host 10.
Referring to fig. 1 and 3, in order to improve the writing efficiency of host data into the memory 20 in the host 10 and improve the service performance and service life of the memory 20. In the process of writing a batch of host data, first, the main controller 30 allocates a physical address and a write buffer for a certain host data, respectively, and counts other host data which are identical to the certain host data in the batch of host data. And secondly, sharing the same physical address and the same write buffer area with other host data and certain host data. Then, other host data and certain host data are written into the flash memory 40.
Specifically, as shown in fig. 3, in the case where the host 10 writes host data to the memory 20, for example, logical addresses corresponding to the host 10 writing host data are LBA0 to LBA (M-1), and host data corresponding to logical addresses of LBA0 to LBA7 are identical, (M-1) > 7.
First, the main controller 30 allocates a physical address and a write buffer for a certain host data, and counts other host data having the same data as the certain host data in the batch of host data. For example, a write buffer Buf2 and a physical address PBA4 are allocated for a host data with a logical address of LBA 0. Statistics are performed on the batch of host data, such as the direct memory access unit 32 checking the data in units of 512 bytes. After the host data with logical addresses LBA1-LBA7 and the host data with logical address LBA0 are found to be the same data, the host data with logical addresses LBA1-LBA7 may be recorded as other host data. Next, for other host data with logical addresses LBA1-LBA7, the physical address PBA4 and the write buffer Buf2 may be shared with a certain host data with logical address LBA 0. Then, other host data with logical addresses of LBA1 through LBA7 and a certain host data with logical address of LBA0 are written into the flash memory 40.
It should be noted that, in order to distinguish between a batch of host data, one of the host data may be denoted as a certain host data, the same host data may be denoted as other host data, and the remaining host data in a batch may be denoted as remaining host data.
Specifically, as shown in fig. 3, first, under the action of the direct memory access unit 32, host data is first stored in the write buffer, where LBA0 corresponds to Buf2, LBA1 corresponds to Buf2, … …, LBA7 corresponds to Buf2, that is, the write buffers corresponding to logical addresses of LBA0-LBA7 are all Buf2. Next, the host data in the write buffer Buf2 is rewritten into the flash memory 40, and the write buffer Buf2 corresponds to the physical address PBA4. Then, the memory space on the write buffer Buf2 can be released, and mapping information between the logical address and the physical address associated with the host data can be recorded. The information in the data mapping Table (L2P Table) is as follows:
TABLE 6 second State of data mapping Table
Referring to fig. 2, 3, 5 and 6, it can be seen from table 6 that the physical address corresponding to the logical addresses of LBA0-LBA7 is PBA4. In this embodiment, in the process of writing host data into the memory 20 by the host 10, when the corresponding 8 host data with logical addresses LBA0-LBA7 are the same data, only 1 physical address and 1 write buffer are needed, and only one write is needed to the flash memory 40. This embodiment does not require the use of 8 physical addresses and 8 write buffers as in the prior art of fig. 2 and table 5, nor does it require multiple writes to flash memory 40. In this embodiment, the speed of writing host data into the host 10 is reduced due to the number of physical addresses, the size of the write buffer, and the time for writing into the flash memory 40, and the writing speed of the host 10 can be improved.
FIG. 7 is a table showing the write-in of host data in the prior art and the present embodiment
Referring to fig. 1, in one embodiment of the present invention, a data register may be provided in the direct memory access unit 32, and the data register may include a repeat data flag bit and a write buffer bit, and the data register has 16 bits (bits) in the format shown in table 8 below. The repeated data flag bit represents whether other host data which is identical to a certain host data in a batch of host data is reflected by bit 15. The write buffer bit characterizes the serial number of the write buffer associated with a host data, and is reflected by bits 0-14.
Specifically, after allocating a physical address and writing a buffer for a certain host data, when counting other host data that is identical to the certain host data in the batch of host data, the main controller 30 sets the duplicate data identification bit15 in the data register, for example, to 1. After allocating a physical address and writing a buffer area to a certain host data, when it is counted that there is no other host data with the same data as the certain host data in the batch of host data, the main controller 30 does not set the duplicate data identification bit15 in the data register, for example, it is kept to 0.
Table 8, format table of data register
Referring to fig. 1, in one embodiment of the present invention, the memory 20 may expand the data mapping table and the data register to form an expanded entry of the data mapping table, record mapping information between the logical address and the physical address, and record information in the data register. As shown in table 9 below:
Table 9, extension entry of data mapping table
Referring to fig. 3 and table 9, in one embodiment of the present invention, the analysis is performed in conjunction with the data register during the writing of host data to the memory 20 by the host 10. As shown in fig. 3, in the case where the host 10 writes host data to the memory 20, for example, logical addresses corresponding to the host 10 writing host data are LBA0-LBA (M-1), and host data corresponding to logical addresses of LBA0-LBA7 are the same, (M-1) > 7.
Specifically, the host controller 30 allocates a write buffer Buf2 and a physical address PBA4 to a host data with a logical address of LBA 0. Statistics is performed on the batch of host data, and it is found that the host data with logical addresses of LBA1-LBA7 and the other host data with logical address of LBA0 are the same data. The direct memory access unit 32 finds the same, and sets the duplicate data identification bit15 in the data register, for example, to 1, and the write buffer bit can record the serial number of the write buffer, which is Buf2. Next, for other host data with logical addresses LBA1-LBA7, the physical address PBA4 and the write buffer Buf2 of a certain host data with logical address LBA0 may be shared. And records an extended entry table of the data mapping table as shown in table 10 below.
Table 10, extended entry table of data mapping table
Referring to tables 8 and 10, in one embodiment of the present invention, after setting the duplicate data identification bit15 in the data register, for example, to 1, other host data share the physical address PBA4 and the write buffer Buf2 of a certain host data. In addition, if after the duplicate data identification bit15 in the data register is not set, for example, kept at 0, a new physical address and a new write buffer are allocated to another host data.
Referring to fig. 4, in an embodiment of the present invention, a data processing method of a memory is provided, which may include the following steps:
step S10, host data written by a host are received and stored in a plurality of blocks of the flash memory.
Step S20, in the process of writing a batch of host data, a physical address and a write buffer are allocated for a certain host data.
In step S30, in the batch of host data, other host data completely identical to a certain host data is counted, and the other host data and the certain host data share the same physical address and write buffer.
Step S40, writing other host data and a certain host data into the flash memory.
The following is a detailed description of specific embodiments.
Step S10, host data written by a host are received and stored in a plurality of blocks of the flash memory.
In one embodiment of the present invention, as shown in fig. 1, the flash memory 40 may include a plurality of blocks (blocks) 41, the blocks 41 may be used to store data mapping tables (L2P, logic Block Address to Physical Block Address Table and host data written by the host 10, and one Block 41 may further include a plurality of pages (pages) 42. The data mapping tables store mapping information of logical addresses and physical addresses of the host data.
Step S20, in the process of writing a batch of host data, a physical address and a write buffer are allocated for a certain host data.
In one embodiment of the present invention, as shown in fig. 3, in the case where the host 10 writes host data to the memory 20, the central processing unit 31 allocates a physical address and a write buffer to the host data. Under the action of the direct memory access unit 32, host data is first stored in the write buffer, then the host data in the write buffer is rewritten in the flash memory 40, and then the memory space on the write buffer can be released, and mapping information between the logical address and the physical address associated with the host data is recorded. In the case that the host 10 reads the host data from the memory 20, after the host 10 reads a certain logical address, the memory 20 may search the data mapping table, find a physical address corresponding to the certain logical address, read the storage data on the physical address, and transfer the storage data to the host 10.
In step S30, in the batch of host data, other host data completely identical to a certain host data is counted, and the other host data and the certain host data share the same physical address and write buffer.
In one embodiment of the present invention, as shown in FIG. 3, in the case where host 10 writes host data to memory 20, for example, host 10 writes host data corresponding to logical addresses LBA0-LBA (M-1), and LBA0-LBA7 corresponding to host data is the same, (M-1) > 7.
Specifically, as shown in fig. 3, the main controller 30 allocates a physical address and a write buffer for a certain host data, and counts other host data having the same data as the certain host data in the batch of host data. For example, a write buffer Buf2 and a physical address PBA4 are allocated for a host data with a logical address of LBA 0. Statistics are performed on the batch of host data, such as the direct memory access unit 32 checking the data in units of 512 bytes. After the host data with logical addresses LBA1-LBA7 and the host data with logical address LBA0 are found to be the same data, the host data with logical addresses LBA1-LBA7 may be recorded as other host data. Next, for other host data with logical addresses LBA1-LBA7, the physical address PBA4 and the write buffer Buf2 of a certain host data with logical address LBA0 may be shared.
Step S40, writing other host data and a certain host data into the flash memory.
In one embodiment of the present invention, other host data with logical addresses LBA1-LBA7 and some host data with logical address LBA0 are written into flash memory 40.
Referring to fig. 5, in an embodiment of the present invention, step S30 may be followed by step S310 and step S311. Step S310 may be represented as storing a data mapping table in the flash memory 40, where the data mapping table stores mapping information of logical addresses and physical addresses of host data. Step S311 may be expressed as associating the same physical address and the same write buffer for a plurality of logical addresses corresponding to other host data and a certain host data.
Specifically, as shown in fig. 3, under the action of the direct memory access unit 32, host data is first stored in the write buffer, where LBA0 corresponds to Buf2, LBA1 corresponds to Buf2, … …, LBA7 corresponds to Buf2, that is, the write buffers corresponding to logical addresses of LBA0-LBA7 are all Buf2. Next, the host data in the write buffer Buf2 is rewritten into the flash memory 40, and the write buffer Buf2 corresponds to the physical address PBA4.
Referring to fig. 6, in an embodiment of the present invention, step S30 may further include step S320 and step S321. Step S320 may be represented as a repeated data flag bit representing information about whether there is exactly the same other host data as a certain host data in a batch of host data. Step S321 may be represented by characterizing the serial number of the write buffer associated with a host data as a write buffer bit.
In one embodiment of the present invention, as shown in Table 8, a data register may be provided, which may include a repeat data flag bit and a write buffer bit, the data register having 16 bits (bits) in the format shown in Table 8 below. The repeated data flag bit indicates whether there is other host data having the same data as a certain host data in a batch of host data, and is reflected by bit 15. The write buffer bit characterizes the sequence number of the write buffer associated with a host data and is reflected by bits 0-14.
Referring to fig. 7, in an embodiment of the present invention, step S321 may be followed by steps S322 to S325. Step S322 may represent that after allocating a physical address and a write buffer for a certain host data, when it is detected that the batch of host data has other host data identical to the certain host data, the duplicate data identification bit is set, for example, to 1. Step S323 may be expressed as setting the duplicate data identification bit in the data register, for example, to 1, and then sharing the same physical address and write buffer with other host data and some host data. Step S324 may represent that after allocating a physical address and a write buffer for a certain host data, when no other host data with the same data as the certain host data is detected in the batch of host data, the duplicate data identification bit is not set, for example, is kept to be 0. Step S325 may be expressed as allocating a new physical address and a new write buffer to another host data after the duplicate data identification bit in the data register is not set, e.g., remains at 0.
Specifically, as shown in table 8, after allocating a physical address and writing a buffer area to a certain host data, when counting that other host data having the same data as the certain host data in the batch of host data, the duplicate data identification bit15 in the data register is set, for example, to 1. After allocating a physical address and writing a buffer area to a certain host data, when it is counted that there is no other host data with the same data as the certain host data in the batch of host data, the main controller 30 does not set the duplicate data identification bit15 in the data register, for example, it is kept to 0.
In summary, the present invention provides a memory and a data processing method thereof, and in the process of writing host data, when the host data has repeated data, the repeated data share a physical address and a write buffer area. The invention can store the repeated data into the flash memory under the operation of writing the flash memory once. The invention can improve the writing efficiency of host data in the host to the memory, and can further improve the service performance and service life of the storage device.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A memory, comprising:
the flash memory comprises a plurality of blocks for storing host data; and
The main controller is electrically connected with the flash memory and is used for distributing a physical address and a write buffer area for the host data in the writing process of the host data;
in the writing process of a batch of host data, the main controller allocates a physical address and a writing buffer area for a certain host data, counts other host data which are completely the same as the certain host data in the batch of host data, shares the same physical address and the writing buffer area with the other host data, and then writes the other host data and the certain host data into the flash memory.
2. The memory of claim 1, wherein the flash memory is configured to store a data mapping table, the data mapping table storing mapping information of logical addresses and physical addresses of host data;
and the main controller associates the same physical address and the same write cache area with a plurality of logical addresses corresponding to the other host data and the certain host data.
3. The memory of claim 1, wherein a data register is provided in the main controller, and wherein a duplicate data identification bit and a write buffer bit are provided in the data register;
and the repeated data flag bit represents whether the repeated data flag bit has the information of the other host data which is completely the same as the certain host data in a batch of host data, and the writing buffer bit represents the serial number of the writing buffer area associated with the certain host data.
4. The memory according to claim 3, wherein after the host controller allocates a physical address and a write buffer for the certain host data, when the batch of host data is counted to have the other host data identical to the certain host data, the repeated data identification bit in the data register is set;
After the main controller allocates a physical address and a write buffer area for the host data, when the host data of the batch is counted to have no other host data with the same data as the host data, the repeated data identification bit in the data register is not set.
5. The memory of claim 4 wherein said main control, after setting said duplicate data identification bit in said data register, shares said physical address of said certain host data with said write buffer with said other host data;
And after the main control does not set the repeated data identification bit in the data register, a new physical address and a new write buffer area are allocated for the data of another host.
6. A data processing method of a memory, comprising:
Host data written by a host are received and stored in a plurality of blocks of the flash memory;
in the writing process of host data of a batch, a physical address and a writing buffer area are allocated for a certain host data;
In the batch of host data, counting other host data which are completely the same as the certain host data, and sharing the same physical address and write cache area with the other host data;
And writing the other host data and the certain host data into the flash memory.
7. The method according to claim 6, wherein after the step of counting the other host data which is identical to the certain host data in the batch of host data and sharing the same physical address and write buffer with the certain host data, the method further comprises:
storing a data mapping table into the flash memory, wherein the data mapping table stores mapping information of a logical address and a physical address of host data;
And associating the same physical address and the same write cache area with a plurality of logical addresses corresponding to the other host data and the certain host data.
8. The method according to claim 6, wherein after the step of counting the other host data identical to the certain host data in the batch of host data, the method comprises:
in a batch of host data, characterizing whether the information of the other host data which is completely the same as the certain host data is repeated data flag bits;
and characterizing the serial number of the write buffer area associated with the host data as a write buffer area bit.
9. The method according to claim 8, wherein after the step of characterizing whether the information identical to the certain host data is repeated data flag bits in a batch of host data, the method comprises:
After a physical address and a write buffer area are allocated to the certain host data, when the other host data with the same data as the certain host data in the batch of host data is detected, setting the repeated data identification bit;
After a physical address and a write buffer area are allocated to the certain host data, when the other host data which is not the same as the certain host data in the batch of host data is detected, the repeated data identification bit is not set.
10. The method of claim 9, wherein the step of sharing the same physical address and write buffer with the other host data and the certain host data comprises:
after setting the repeated data identification bit in the data register, sharing the same physical address and write buffer area with the other host data and the certain host data;
After the repeated data identification bit in the data register is not set, a new physical address and a new write buffer area are allocated for the data of another host.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411067359.0A CN118585141A (en) | 2024-08-06 | 2024-08-06 | Memory and data processing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411067359.0A CN118585141A (en) | 2024-08-06 | 2024-08-06 | Memory and data processing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118585141A true CN118585141A (en) | 2024-09-03 |
Family
ID=92528496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411067359.0A Pending CN118585141A (en) | 2024-08-06 | 2024-08-06 | Memory and data processing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118585141A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110389718A (en) * | 2018-04-16 | 2019-10-29 | 东芝存储器株式会社 | The control method of storage system and nonvolatile memory |
| CN110543435A (en) * | 2019-09-05 | 2019-12-06 | 北京兆易创新科技股份有限公司 | Mixed mapping operation method, device and equipment of storage unit and storage medium |
| CN111881065A (en) * | 2020-07-30 | 2020-11-03 | 北京浪潮数据技术有限公司 | Physical address processing method, device, equipment and medium for data deduplication operation |
| CN112053735A (en) * | 2019-06-05 | 2020-12-08 | 建兴储存科技(广州)有限公司 | Repeated data processing method of solid-state storage device |
| CN112559388A (en) * | 2020-12-14 | 2021-03-26 | 杭州宏杉科技股份有限公司 | Data caching method and device |
| WO2023029417A1 (en) * | 2021-08-31 | 2023-03-09 | 华为技术有限公司 | Data storage method and device |
| CN116932426A (en) * | 2022-04-07 | 2023-10-24 | 中山市江波龙电子有限公司 | Method for managing stored data, electronic device and computer readable storage device |
-
2024
- 2024-08-06 CN CN202411067359.0A patent/CN118585141A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110389718A (en) * | 2018-04-16 | 2019-10-29 | 东芝存储器株式会社 | The control method of storage system and nonvolatile memory |
| CN112053735A (en) * | 2019-06-05 | 2020-12-08 | 建兴储存科技(广州)有限公司 | Repeated data processing method of solid-state storage device |
| CN110543435A (en) * | 2019-09-05 | 2019-12-06 | 北京兆易创新科技股份有限公司 | Mixed mapping operation method, device and equipment of storage unit and storage medium |
| CN111881065A (en) * | 2020-07-30 | 2020-11-03 | 北京浪潮数据技术有限公司 | Physical address processing method, device, equipment and medium for data deduplication operation |
| CN112559388A (en) * | 2020-12-14 | 2021-03-26 | 杭州宏杉科技股份有限公司 | Data caching method and device |
| WO2023029417A1 (en) * | 2021-08-31 | 2023-03-09 | 华为技术有限公司 | Data storage method and device |
| CN116932426A (en) * | 2022-04-07 | 2023-10-24 | 中山市江波龙电子有限公司 | Method for managing stored data, electronic device and computer readable storage device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110781096B (en) | Apparatus and method for performing garbage collection by predicting demand time | |
| US11513948B2 (en) | Controller and memory system | |
| KR20200022118A (en) | Data storage device and operating method thereof | |
| US11249897B2 (en) | Data storage device and operating method thereof | |
| KR20190090635A (en) | Data storage device and operating method thereof | |
| CN107797934B (en) | Method for processing de-allocation command and storage device | |
| CN110837342A (en) | Data storage device and operation method thereof | |
| US11210226B2 (en) | Data storage device and method for first processing core to determine that second processing core has completed loading portion of logical-to-physical mapping table thereof | |
| CN110928807A (en) | Apparatus and method for checking valid data in a memory system | |
| US20220138096A1 (en) | Memory system | |
| US8429339B2 (en) | Storage device utilizing free pages in compressed blocks | |
| CN107797938B (en) | Method for accelerating de-allocation command processing and storage device | |
| CN114371812B (en) | Controller and operation method thereof | |
| CN110781093B (en) | Data storage device capable of changing mapping cache buffer size | |
| US10466938B2 (en) | Non-volatile memory system using a plurality of mapping units and operating method thereof | |
| CN111966281A (en) | Data storage device and data processing method | |
| CN108877862B (en) | Data organization of page stripes and method and device for writing data into page stripes | |
| CN113885782A (en) | Storage device and operation method thereof | |
| CN112328516A (en) | Controller, method of operating the controller, and storage device including the controller | |
| CN118585141A (en) | Memory and data processing method thereof | |
| CN112099731A (en) | Data storage device and data processing method | |
| CN111857565A (en) | Memory system, data processing system and operation method thereof | |
| US11294587B2 (en) | Data storage device capable of maintaining continuity of logical addresses mapped to consecutive physical addresses, electronic device including the same, and method of operating the data storage device | |
| US20240176736A1 (en) | Memory system and a method for garbage collection of the memory system | |
| CN118426707A (en) | Storage device and data processing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |