CN118585141A - A memory and data processing method thereof - Google Patents

Abstract

The present invention provides a memory and a data processing method thereof, wherein the memory comprises: a flash memory, comprising a plurality of blocks, for storing host data; and a main controller, electrically connected to the flash memory, and the main controller is used to allocate a physical address and a write buffer area for the host data during the writing process of the host data; wherein, during the writing process of a batch of host data, the main controller allocates a physical address and a write buffer area for a certain host data, counts other host data in the batch of host data that are completely identical to a certain host data, and shares the same physical address and write buffer area with the other host data, and then writes the other host data and the certain host data into the flash memory. The present invention can improve the writing efficiency of the host data in the host to the memory, and can improve the use performance and service life of the memory.

Description

A memory and data processing method thereof

Technical Field

The present invention relates to the field of static storage technology, and in particular to a memory and a data processing method thereof.

Background Art

Memory chips are the specific application of the concept of embedded system chips in the storage industry. Both system chips and memory chips embed software in a single chip to achieve multi-function, high performance and support for multiple protocols, multiple hardware and different applications. Memory chips are widely used in computers, mobile devices, the Internet of Things and other fields to store various data, such as operating systems, applications, music, videos, photos, etc.

The performance of data stored in the flash memory of the storage chip is affected by the data writing performance. Currently, the writing performance of the storage chip is poor, which may cause the storage system to run slowly. Therefore, there is room for improvement.

Summary of the invention

The present invention provides a memory and a data processing method thereof, so as to solve the technical problem that the writing performance of the current memory chip is poor and the memory system runs slowly.

The present invention provides a memory, comprising:

A flash memory including a plurality of blocks for storing host data; and

A main controller, electrically connected to the flash memory, and configured to allocate a physical address and a write buffer area to the host data during the writing process of the host data;

Among them, during the writing process of a batch of host data, the main controller allocates a physical address and a write cache area to a certain host data, counts other host data in the batch of host data that are exactly the same as the certain host data, and makes the other host data share the same physical address and write cache area with the certain host data, and then writes the other host data and the certain host data into the flash memory.

In one embodiment of the present invention, the flash memory is used to store a data mapping table, and the data mapping table stores mapping information between logical addresses and physical addresses of host data;

The main controller associates the same physical address and the same write cache area with respect to multiple logical addresses corresponding to other host data and a certain host data.

In one embodiment of the present invention, a data register is provided in the main controller, and a duplicate data identification bit and a write cache bit are provided in the data register;

The duplicate data flag bit indicates whether there is information of other host data that is completely identical to a certain host data in a batch of host data, and the write cache area bit indicates the serial number of the write cache area associated with a certain host data.

In one embodiment of the present invention, after the main controller allocates a physical address and a write buffer area for a certain host data, when other host data identical to the certain host data is counted in the batch of host data, a duplicate data identification bit in the data register is set;

After the main controller allocates a physical address and a write buffer area for a certain host data, when there is no other host data with the same data as the certain host data in the batch of host data, the duplicate data identification bit in the data register is not set.

In one embodiment of the present invention, the master control, after setting the duplicate data identification bit in the data register, shares the physical address and write buffer area of a certain host data with other host data;

The master control allocates a new physical address and a new write buffer area for another host data after the duplicate data identification bit in the data register is not set.

The present invention also provides a data processing method of a memory, comprising:

receiving host data written by the host and storing the data in a plurality of blocks of the flash memory;

In the process of writing a batch of host data, a physical address and a write buffer area are allocated for a certain host data;

In the batch of host data, other host data that are completely identical to a certain host data are counted, and the other host data and the certain host data share the same physical address and write buffer area;

Other host data and certain host data are written into the flash memory.

In one embodiment of the present invention, after the step of counting other host data that are identical to a certain host data in the batch of host data and sharing the physical address and write buffer area of the certain host data with the other host data, the method includes:

Storing a data mapping table in the flash memory, wherein the data mapping table stores mapping information between logical addresses and physical addresses of host data;

For other host data and multiple logical addresses corresponding to a certain host data, the same physical address and the same write buffer area are associated.

In one embodiment of the present invention, after the step of counting other host data that are completely identical to a certain host data in the batch of host data, the method includes:

In a batch of host data, whether there is other host data that is completely identical to a certain host data is represented as a duplicate data flag;

The serial number of the write cache area associated with a certain host data is represented as a write cache area bit.

In one embodiment of the present invention, after the step of representing information in a batch of host data as a duplicate data flag whether it is completely identical to a certain host data, the method includes:

After allocating a physical address and a write buffer area for a certain host data, when checking that other host data in the batch of host data has the same data as the certain host data, the duplicate data identification bit is set;

After allocating a physical address and a write buffer area for a certain host data, when it is checked that there is no other host data with the same data as the certain host data in the batch of host data, the duplicate data identification bit is not set.

In one embodiment of the present invention, the step of sharing the physical address and write buffer area of a certain host data with other host data includes:

After the duplicate data identification bit in the data register is set, other host data share the physical address and write buffer area of a certain host data;

After the duplicate data identification bit in the data register is not set, a new physical address and a new write buffer area are allocated for another host data.

Beneficial effects of the present invention: The present invention proposes a memory and a data processing method thereof, which can improve the efficiency of writing host data into the memory in the host, and can improve the performance and service life of the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG. 1 is a schematic diagram of the structure of a memory provided by an embodiment of the present invention.

FIG. 2 is a schematic diagram of writing host data into a memory in the prior art.

FIG. 3 is a schematic diagram of writing host data into a memory provided by an embodiment of the present invention.

FIG. 4 is a schematic diagram of steps of a data processing method for a memory provided by an embodiment of the present invention.

FIG. 5 is a schematic diagram of steps after step S30 in FIG. 4 provided by an embodiment of the present invention.

FIG. 6 is a schematic diagram of steps after step S30 in FIG. 4 provided by another embodiment of the present invention.

FIG. 7 is a schematic diagram of steps after step S321 in FIG. 6 provided by an embodiment of the present invention.

Description of the accompanying drawings: 10, host; 20, memory; 30, main controller; 31, central processing unit; 32, direct storage access unit; 40, flash memory; 41, block; 42, page.

DETAILED DESCRIPTION

The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

Please refer to Figures 1 to 7. The present invention proposes a memory and a data processing method thereof, which can be applied to storage devices such as eMMC (Embedded Multi Media Card), SSD (Solid State Disk), and UFS (Univeral Flash Storage). In the process of writing host data, when there is duplicate data in the host data, the duplicate data share a physical address and a write cache area. The host data refers to the application data written by the host 10. The present invention can save the above-mentioned duplicate data in the flash memory 40 under the operation of writing to the flash memory 40 once. The present invention can improve the writing efficiency of the host data in the host 10 to the memory 20, and can further improve the performance and service life of the memory 20. The following is a detailed description through specific embodiments.

Referring to FIG. 1 , in one embodiment of the present invention, a memory 20 is provided, and a bus interface is provided on the memory 20. The memory 20 is electrically connected to a host 10 through the bus interface. The host 10 can write host data and send commands to the memory 20, or the host 10 can read host data and receive commands from the memory 20. The host 10 can be a communication device such as a personal computer (PC), a tablet computer (Pad), or a mobile phone (Cell Phone).

Please refer to FIG. 1 . In one embodiment of the present invention, the memory 20 may include a main controller 30 and a flash memory 40. The flash memory 40 is a non-volatile memory, which is usually used to store host data and system programs. The main controller 30 is mainly used to operate and manage the flash memory 40, and the main controller 30 also provides functions such as cache, memory array and interleave. The main controller 30 is electrically connected to the flash memory 40. The main controller 30 can control many functions of the flash memory 40, such as bad block management, wear leveling, error checking and correction (ECC, Error Checking and Correcting), etc. The main controller 30 can greatly improve the read, write and move operation performance of the host data in the flash memory 40.

Please refer to FIG. 1 . In one embodiment of the present invention, inside the memory 20 , a flash memory interface is provided on the main controller 30 . The main controller 30 is electrically connected to the flash memory 40 through the flash memory interface. The main controller 30 may include a central processing unit (CPU) 31 and a direct memory access unit (DMA) 32 . The central processing unit 31 is the computing core and control core of the storage device, for example, it allocates a physical address (PBA) and a write buffer (WriteBuf) for host data. The direct memory access unit 32 is used to transmit host data and does not need to occupy the central processing unit 31 . When the direct memory access unit 32 transmits host data, the central processing unit 31 can handle other things, and the working process is similar to a multi-threaded method.

Specifically, the physical address is the actual address corresponding to the block 41 in the flash memory 40, also known as the real address. Corresponding to the physical address is the logical address (LBA, Logical Block Address), which refers to the relative address used in the user program, also known as the virtual address. The logical address is generated by the central processing unit 31 and is used to access the data in the flash memory 40. For the host data that the main controller 30 is going to write into the flash memory 40, it can be temporarily stored in the write cache area, and then the write cache area is written into the flash memory 40 at a low speed.

Referring to FIG. 1 , in one embodiment of the present invention, a flash memory 40 may include a plurality of blocks 41. The blocks 41 may be used to store a data mapping table (L2P, Logic Block Address to Physical Block Address Table) and host data written by the host 10. A block 41 may also include a plurality of pages 42. The data mapping table stores mapping information of the logical address and the physical address of the host data. By querying the mapping information in the data mapping table using the logical address, the corresponding physical address can be found, and then the host data at the corresponding physical address in the flash memory 40 can be read, written, moved, etc.

Specifically, when the host 10 writes host data to the memory 20, the central processing unit 31 allocates a physical address and a write buffer area to the host data. Under the action of the direct storage access unit 32, the host data is first stored in the write buffer area, and then the host data in the write buffer area is written to the flash memory 40, after which the storage space on the write buffer area can be released, and the mapping information between the logical address and the physical address associated with the host data is recorded. When the host 10 reads the host data from the memory 20, after the host 10 reads a certain logical address, the memory 20 can search the data mapping table, find the physical address corresponding to a certain logical address, read the storage data at the physical address and pass it to the host 10.

Table 1: User space division table

In one embodiment of the present invention, as shown in Table 1, the user space may be divided into LBA0-LBA(M-1) in units of 512 bytes.

Table 2: Partition table of flash memory 40 locations

In one embodiment of the present invention, as shown in Table 2, the flash memory 40 location can be divided into PBA0-PBA(N-1) in units of 512 bytes, and N≥M.

Table 3. Write cache area division table

In one embodiment of the present invention, as shown in Table 3, the write buffer area may be divided into Buf0-Buf(L-1) in units of 512 bytes.

The mapping relationship between a logical address and a physical address can be represented by a data mapping entry in the following format:

The memory 20 records and updates the data mapping table (L2P Table), in which a logical address (LBA) corresponds to a physical address (LBA). A written logical address has a physical address corresponding to it, and an unwritten logical address has no physical address corresponding to it. The format of the data mapping table (L2P Table) is as follows:

Table 4. Initial state of the data mapping table

In the prior art, as shown in FIG. 2 , when the host 10 writes host data to the memory 20, for example, the logical address corresponding to the host data written by the host 10 is LBA0-LBA (M-1), and the host data corresponding to the logical addresses of LBA0-LBA7 are the same, (M-1)>7. At this time, the central processing unit 31 can be the logical address of LBA0-LBA7, and 8 physical addresses and 8 write buffers can be allocated. The physical addresses can be PBA4, PBA5, PBA6, PBA7, PBA8, PBA9, PBA10 and PBA11, and the write buffers can be Buf2, Buf3, Buf4, Buf5, Buf6, Buf7, Buf8 and Buf9.

Specifically, as shown in FIG2 , first, under the action of the direct storage access unit 32, the host data is first stored in the write cache area, LBA0 corresponds to Buf2, LBA1 corresponds to Buf3, ..., LBA7 corresponds to Buf9. Secondly, the host data in the write cache area is then written to the flash memory 40, Buf2 corresponds to PBA4, Buf3 corresponds to PBA5, ..., Buf9 corresponds to PBA11. Then, the storage space on the write cache area can be released, and the mapping information between the logical address and the physical address associated with the host data can be recorded. The information in the data mapping table (L2P Table) is as follows:

Table 5. First state of data mapping table

It can be seen from the above data mapping table (L2P Table) that the physical addresses corresponding to the logical addresses LBA0-LBA7 are PBA4-PBA11. In the prior art, when the host 10 writes host data to the memory 20, even if the 8 host data corresponding to the logical addresses LBA0-LBA7 are the same data, 8 physical addresses and 8 write buffers are still needed, and they need to be written to the flash memory 40 multiple times. The speed at which the host 10 writes host data is limited by the number of physical addresses, the size of the write buffer, and the time to write to the flash memory 40.

In the prior art, as shown in FIG. 2 , when the host 10 reads host data from the memory 20 , after the host 10 reads a logical address LBA1, the memory 20 can search the data mapping table (L2P Table), find the physical address PBA5 corresponding to the logical address LBA1, read the storage data at the physical address PBA5 and pass it to the host 10 .

Please refer to FIG. 1 and FIG. 3 , in order to improve the writing efficiency of the host data in the host 10 to the memory 20, and to improve the performance and service life of the memory 20. In the process of writing a batch of host data, first, the main controller 30 allocates physical addresses and write buffers to certain host data, and counts other host data in the batch of host data that are exactly the same as the certain host data. Secondly, the other host data and the certain host data share the same physical address and write buffer. Then, the other host data and the certain host data are written into the flash memory 40.

Specifically, as shown in FIG3 , when the host 10 writes host data to the memory 20 , for example, the logical address corresponding to the host data written by the host 10 is LBA0-LBA (M-1), and the host data corresponding to the logical addresses LBA0-LBA7 are the same, (M-1)>7.

First, the main controller 30 allocates a physical address and a write cache area to a certain host data, and counts other host data in the batch of host data that have the same data as the certain host data. For example, a write cache area Buf2 and a physical address PBA4 are allocated to a certain host data with a logical address of LBA0. Statistics are performed on the batch of host data, for example, the direct storage access unit 32 checks the data in units of 512 bytes. After it is found that the host data with logical addresses LBA1-LBA7 is the same data as the host data with logical address LBA0, the host data with logical addresses LBA1-LBA7 can be recorded as other host data. Secondly, for other host data with logical addresses LBA1-LBA7, the physical address PBA4 and the write cache area Buf2 can be shared with a certain host data with a logical address of LBA0. Then, the other host data with logical addresses LBA1-LBA7 and a certain host data with a logical address of LBA0 are written into the flash memory 40.

It is worth mentioning that in order to distinguish a batch of host data, one of the host data can be recorded as a certain host data, the host data that is exactly the same as a certain host data can be recorded as other host data, and the remaining host data in a batch can be recorded as remaining host data.

Specifically, as shown in FIG3 , first, under the action of the direct storage access unit 32, the host data is first stored in the write cache area, LBA0 corresponds to Buf2, LBA1 corresponds to Buf2, ..., LBA7 corresponds to Buf2, that is, the write cache area corresponding to the logical address of LBA0-LBA7 is Buf2. Secondly, the host data in the write cache area Buf2 is then written to the flash memory 40, and the write cache area Buf2 corresponds to the physical address PBA4. Then, the storage space on the write cache area Buf2 can be released, and the mapping information between the logical address and the physical address associated with the host data can be recorded. The information in the data mapping table (L2P Table) is as follows:

Table 6. Second state of data mapping table

Please refer to FIG. 2, FIG. 3, Table 5 and Table 6. It can be seen from Table 6 that the physical address corresponding to the logical address of LBA0-LBA7 is PBA4. In this embodiment, when the host 10 writes host data to the memory 20, when the 8 host data corresponding to the logical addresses LBA0-LBA7 are the same data, only 1 physical address and 1 write buffer area need to be used, and only one write to the flash memory 40 is needed. This embodiment does not need to use 8 physical addresses and 8 write buffer areas as in the prior art of FIG. 2 and Table 5, nor does it need to be written to the flash memory 40 multiple times. In this embodiment, the speed of the host 10 writing host data is reduced due to the restrictions of the number of physical addresses, the size of the write buffer area and the time of writing to the flash memory 40. This embodiment can improve the write speed of the host 10.

FIG. 7 is a comparison table of the host data written in the prior art and the present embodiment.

Please refer to FIG. 1 . In one embodiment of the present invention, a data register may be provided in the direct storage access unit 32. The data register may include a duplicate data flag bit and a write cache area bit. The data register has 16 bits, and its format is shown in Table 8 below. The duplicate data flag bit indicates whether other host data in a batch of host data is completely identical to a certain host data, and is reflected by bit 15. The write cache area bit indicates the serial number of the write cache area associated with a certain host data, and is reflected by bit 0-bit 14.

Specifically, after the main controller 30 allocates a physical address and a write buffer area for a certain host data, when other host data identical to the certain host data is counted in the batch of host data, the duplicate data identification bit 15 in the data register is set, for example, to 1. After the main controller 30 allocates a physical address and a write buffer area for a certain host data, when other host data identical to the certain host data is counted in the batch of host data, the duplicate data identification bit 15 in the data register is not set, for example, maintained at 0.

Table 8. Data register format

Referring to FIG. 1 , in one embodiment of the present invention, the memory 20 can expand the data mapping table and the data register to form an extended entry of the data mapping table, can record the mapping information between the logical address and the physical address, and can also record the information in the data register. As shown in Table 9 below:

Table 9. Extended entries in the data mapping table

Please refer to FIG3 and Table 9. In one embodiment of the present invention, in the process of the host 10 writing host data to the memory 20, analysis is performed in combination with the data register. As shown in FIG3, in the case where the host 10 writes host data to the memory 20, for example, the logical address corresponding to the host data written by the host 10 is LBA0-LBA (M-1), and the host data corresponding to the logical addresses of LBA0-LBA7 are the same, (M-1)>7.

Specifically, the main controller 30 allocates a write cache area Buf2 and a physical address PBA4 for a host data with a logical address of LBA0. Statistics are taken on the host data of this batch, and it is found that the host data with logical addresses LBA1-LBA7 are the same data as other host data with a logical address of LBA0. The direct storage access unit 32 finds that they are exactly the same. In the data register, the duplicate data identification bit bit15 is set, for example, to 1, and the write cache area bit can record the serial number of the write cache area, which is Buf2. Secondly, for other host data with logical addresses LBA1-LBA7, the physical address PBA4 and the write cache area Buf2 of a host data with a logical address of LBA0 can be shared. And record the extended entry table of the data mapping table, as shown in Table 10 below.

Table 10: Extended entry table of data mapping table

Please refer to Table 8 and Table 10. In one embodiment of the present invention, after the duplicate data identification bit 15 in the data register is set, for example, to 1, the physical address PBA4 and write buffer area Buf2 of a certain host data are shared by other host data. In addition, if the duplicate data identification bit 15 in the data register is not set, for example, it is kept at 0, a new physical address and a new write buffer area are allocated to another host data.

Please refer to FIG. 4 . In one embodiment of the present invention, the present invention provides a data processing method for a memory, which may include the following steps:

Step S10: receiving host data written by the host, and storing the data in a plurality of blocks of the flash memory.

Step S20: during the writing process of a batch of host data, a physical address and a write buffer area are allocated for a certain host data.

Step S30 , counting other host data that are completely identical to a certain host data in the batch of host data, and making the other host data and the certain host data share the same physical address and write buffer area.

Step S40: write other host data and a certain host data into the flash memory.

The following is a detailed description through specific embodiments.

Step S10: receiving host data written by the host, and storing the data in a plurality of blocks of the flash memory.

In one embodiment of the present invention, as shown in FIG. 1 , a flash memory 40 may include a plurality of blocks 41, and the blocks 41 may be used to store a data mapping table (L2P, Logic Block Address to Physical Block Address Table) and host data written by the host 10. A block 41 may also include a plurality of pages 42. The data mapping table stores mapping information of the logical address and the physical address of the host data. By querying the mapping information in the data mapping table using the logical address, the corresponding physical address can be found, and then the host data at the corresponding physical address in the flash memory 40 can be read, written, moved, and other processes.

Step S20: during the writing process of a batch of host data, a physical address and a write buffer area are allocated for a certain host data.

In one embodiment of the present invention, as shown in FIG3 , when the host 10 writes host data to the memory 20, the central processing unit 31 allocates a physical address and a write buffer area to the host data. Under the action of the direct storage access unit 32, the host data is first stored in the write buffer area, and then the host data in the write buffer area is written to the flash memory 40, after which the storage space on the write buffer area can be released, and the mapping information between the logical address and the physical address associated with the host data is recorded. When the host 10 reads the host data from the memory 20, after the host 10 reads a certain logical address, the memory 20 can search the data mapping table, find the physical address corresponding to a certain logical address, read the storage data at the physical address and pass it to the host 10.

Step S30 , counting other host data that are completely identical to a certain host data in the batch of host data, and making the other host data and the certain host data share the same physical address and write buffer area.

In one embodiment of the present invention, as shown in FIG3 , when the host 10 writes host data to the memory 20 , for example, the logical address corresponding to the host data written by the host 10 is LBA0-LBA (M-1), and the host data corresponding to the logical addresses of LBA0-LBA7 are the same, (M-1)＞7.

Specifically, as shown in FIG3 , the main controller 30 allocates a physical address and a write cache area to a certain host data, and counts other host data in the batch of host data that have the same data as the certain host data. For example, a write cache area Buf2 and a physical address PBA4 are allocated to a certain host data with a logical address of LBA0. Statistics are performed on the batch of host data, for example, the direct storage access unit 32 checks the data in units of 512 bytes. After it is found that the host data with logical addresses LBA1-LBA7 is the same data as the host data with logical address LBA0, the host data with logical addresses LBA1-LBA7 can be recorded as other host data. Secondly, for other host data with logical addresses LBA1-LBA7, the physical address PBA4 and the write cache area Buf2 of a certain host data with a logical address of LBA0 can be shared.

Step S40: write other host data and a certain host data into the flash memory.

In one embodiment of the present invention, other host data with logical addresses LBA1-LBA7 and a certain host data with logical address LBA0 are written into the flash memory 40.

Referring to FIG. 5 , in one embodiment of the present invention, step S30 may include step S310 and step S311. Step S310 may be represented by storing a data mapping table in the flash memory 40, wherein the data mapping table stores mapping information of the logical address and the physical address of the host data. Step S311 may be represented by associating the same physical address and the same write buffer area for multiple logical addresses corresponding to other host data and a certain host data.

Specifically, as shown in FIG3 , under the action of the direct storage access unit 32, the host data is first stored in the write buffer area, LBA0 corresponds to Buf2, LBA1 corresponds to Buf2, ..., LBA7 corresponds to Buf2, that is, the write buffer area corresponding to the logical address of LBA0-LBA7 is Buf2. Secondly, the host data in the write buffer area Buf2 is then written to the flash memory 40, and the write buffer area Buf2 corresponds to the physical address PBA4.

Please refer to FIG. 6 . In one embodiment of the present invention, step S30 may further include step S320 and step S321. Step S320 may be represented as representing information about whether there are other host data that are completely identical to a certain host data in a batch of host data as a duplicate data flag. Step S321 may be represented as representing the serial number of the write cache area associated with a certain host data as a write cache area bit.

In one embodiment of the present invention, as shown in Table 8, a data register may be provided, and the data register may include a duplicate data flag bit and a write cache area bit. The data register has 16 bits, and its format is shown in Table 8. The duplicate data flag bit indicates whether there are other host data with the same data as a certain host data in a batch of host data, and is reflected through bit 15. The write cache area bit indicates the serial number of the write cache area associated with a certain host data, and is reflected through bit 0-bit 14.

Please refer to FIG. 7 . In one embodiment of the present invention, after step S321, steps S322 to S325 may be included. Step S322 may represent that after a physical address and a write buffer area are allocated to a certain host data, when it is checked that there are other host data in the batch of host data that are exactly the same as the certain host data, the duplicate data identification bit is set, for example, to 1. Step S323 may represent that after the duplicate data identification bit in the data register is set, for example, to 1, the other host data and the certain host data share the same physical address and write buffer area. Step S324 may represent that after a physical address and a write buffer area are allocated to a certain host data, when it is checked that there are no other host data with the same data as the certain host data in the batch of host data, the duplicate data identification bit is not set, for example, maintained at 0. Step S325 may represent that after the duplicate data identification bit in the data register is not set, for example, maintained at 0, a new physical address and a new write buffer area are allocated to another host data.

Specifically, as shown in Table 8, after a physical address and a write buffer area are allocated to a certain host data, when other host data with the same data as the certain host data are counted in the batch of host data, the duplicate data identification bit 15 in the data register is set, for example, to 1. After the main controller 30 allocates a physical address and a write buffer area to a certain host data, when other host data with the same data as the certain host data are counted in the batch of host data, the duplicate data identification bit 15 in the data register is not set, for example, maintained at 0.

In summary, the present invention provides a memory and a data processing method thereof. In the process of writing host data, when there is duplicate data in the host data, the duplicate data share a physical address and a write buffer area. The present invention can save the duplicate data in the flash memory in a one-time write operation. The present invention can improve the writing efficiency of the host data in the host to the memory, and can further improve the performance and service life of the storage device.

The flow chart and block diagram in the accompanying drawings illustrate the possible implementation architecture, function and operation of the method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and/or flow chart, and the combination of the boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

Claims (10)

1. A memory, comprising:

the flash memory comprises a plurality of blocks for storing host data; and

The main controller is electrically connected with the flash memory and is used for distributing a physical address and a write buffer area for the host data in the writing process of the host data;

in the writing process of a batch of host data, the main controller allocates a physical address and a writing buffer area for a certain host data, counts other host data which are completely the same as the certain host data in the batch of host data, shares the same physical address and the writing buffer area with the other host data, and then writes the other host data and the certain host data into the flash memory.

2. The memory of claim 1, wherein the flash memory is configured to store a data mapping table, the data mapping table storing mapping information of logical addresses and physical addresses of host data;

and the main controller associates the same physical address and the same write cache area with a plurality of logical addresses corresponding to the other host data and the certain host data.

3. The memory of claim 1, wherein a data register is provided in the main controller, and wherein a duplicate data identification bit and a write buffer bit are provided in the data register;

and the repeated data flag bit represents whether the repeated data flag bit has the information of the other host data which is completely the same as the certain host data in a batch of host data, and the writing buffer bit represents the serial number of the writing buffer area associated with the certain host data.

4. The memory according to claim 3, wherein after the host controller allocates a physical address and a write buffer for the certain host data, when the batch of host data is counted to have the other host data identical to the certain host data, the repeated data identification bit in the data register is set;

After the main controller allocates a physical address and a write buffer area for the host data, when the host data of the batch is counted to have no other host data with the same data as the host data, the repeated data identification bit in the data register is not set.

5. The memory of claim 4 wherein said main control, after setting said duplicate data identification bit in said data register, shares said physical address of said certain host data with said write buffer with said other host data;

And after the main control does not set the repeated data identification bit in the data register, a new physical address and a new write buffer area are allocated for the data of another host.

6. A data processing method of a memory, comprising:

Host data written by a host are received and stored in a plurality of blocks of the flash memory;

in the writing process of host data of a batch, a physical address and a writing buffer area are allocated for a certain host data;

In the batch of host data, counting other host data which are completely the same as the certain host data, and sharing the same physical address and write cache area with the other host data;

And writing the other host data and the certain host data into the flash memory.

7. The method according to claim 6, wherein after the step of counting the other host data which is identical to the certain host data in the batch of host data and sharing the same physical address and write buffer with the certain host data, the method further comprises:

storing a data mapping table into the flash memory, wherein the data mapping table stores mapping information of a logical address and a physical address of host data;

And associating the same physical address and the same write cache area with a plurality of logical addresses corresponding to the other host data and the certain host data.

8. The method according to claim 6, wherein after the step of counting the other host data identical to the certain host data in the batch of host data, the method comprises:

in a batch of host data, characterizing whether the information of the other host data which is completely the same as the certain host data is repeated data flag bits;

and characterizing the serial number of the write buffer area associated with the host data as a write buffer area bit.

9. The method according to claim 8, wherein after the step of characterizing whether the information identical to the certain host data is repeated data flag bits in a batch of host data, the method comprises:

After a physical address and a write buffer area are allocated to the certain host data, when the other host data with the same data as the certain host data in the batch of host data is detected, setting the repeated data identification bit;

After a physical address and a write buffer area are allocated to the certain host data, when the other host data which is not the same as the certain host data in the batch of host data is detected, the repeated data identification bit is not set.

10. The method of claim 9, wherein the step of sharing the same physical address and write buffer with the other host data and the certain host data comprises:

after setting the repeated data identification bit in the data register, sharing the same physical address and write buffer area with the other host data and the certain host data;

After the repeated data identification bit in the data register is not set, a new physical address and a new write buffer area are allocated for the data of another host.