CN118471312A - Chip - Google Patents

Abstract

The embodiment of the disclosure discloses a chip. The chip comprises: the system comprises a memory, a service function module, a test module, a first power domain module and a second power domain module, wherein: the first power domain module is used for disconnecting the power supply of the service function module when the test of the memory is executed, and the service function module is used for executing corresponding service functions; the second power domain module is used for disconnecting power supply of the test module when the service function is executed, and the test module is used for executing test on the memory. According to the embodiment of the disclosure, the business function module and the test module on the chip work independently by dividing the different power domain modules, so that the power consumption is effectively saved.

Description

Chip

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a chip.

Background

With the increase of the functional complexity of integrated circuits, embedded memories have become an indispensable component in ASICs (Application SPECIFIC INTEGRATED circuits) and SOCs (System on Chip). Meanwhile, the progress of process nodes makes the embedded memory gradually enter a high-density and high-capacity stage, so that the power consumption problem of MBIST (Memory Built-In Self-test) technology widely applied to memory testing is also more and more prominent, and a plurality of challenges are brought to design. The memory bank has great instant power consumption during test, and the memory bank has to be designed in an optimized power consumption mode so as to avoid the damage of the chip during the test and have great influence on the reliability of the circuit.

Disclosure of Invention

In view of this, an embodiment of the present disclosure provides a chip, including:

memory, business function module, test module, first power domain module and second power domain module, wherein:

The first power domain module is used for disconnecting the power supply of the service function module when the test of the memory is executed, and the service function module is used for executing corresponding service functions;

The second power domain module is used for disconnecting the power supply of the test module when the service function is executed, and the test module is used for executing the test on the memory.

In some embodiments, the first power domain module is further configured to power the service function module when the service function is performed;

the second power domain module is further configured to supply power to the test module when the memory test is performed.

In some embodiments, the chip further comprises:

A first isolation unit connected between the test module and a pin of the memory; the first isolation unit is used for isolating the test module from the memory when the service function is executed.

In some embodiments, the first isolation unit is connected between the first control signal end of the test module and a corresponding first pin on the memory, and the first isolation unit is specifically configured to: isolating a first control signal of the first control signal end into an invalid state when the service function is executed; wherein the first control signal is used to control the memory when a test of the memory is performed.

In some embodiments, the chip further comprises:

The second isolation unit is connected between the service function module and a pin of the memory; the second isolation unit is used for isolating the business function module from the memory when the test of the memory is executed.

In some embodiments, the second isolation unit is connected between a second control signal end of the service function module and a corresponding second pin on the memory, and the second isolation unit is used for: isolating a second control signal of the second control signal terminal into an invalid state when a test of the memory is executed; wherein the second control signal is used to control the memory when the service function is performed.

In some embodiments, the chip further comprises: a third power domain module for powering the memory and/or clock module; wherein the third power domain module is independent of the first power domain module and the second power domain module; the clock module is used for providing a clock signal for the memory when the service function is executed or the memory is tested.

In some embodiments, the memory includes a plurality of grouped memory cells, the memory cells of different groups using different of the clock signals;

The test module comprises a plurality of grouped test circuits; the test circuits of the same group are used to test the memory cells of the same group.

In some embodiments, the clock module comprises:

At least one selection circuit; the first input end of each selection circuit is used for receiving a test operation signal indicating whether a group of test circuits operate or not, the second input end is used for receiving a service function enabling signal indicating whether the service function module operates or not, and the control end is used for receiving a mode selection signal; the mode selection signal is used for indicating the selection circuit to output the service function enabling signal or the test running signal;

At least one AND gate; the first input end of each AND gate is used for receiving the clock signals used by a group of memory units, and the second input end is connected with the output end of the selection circuit and used for receiving service function enabling signals or the test running signals.

In some embodiments, the clock module further comprises:

The test control module comprises at least one output end for outputting the test running signal, and each output end is respectively connected with one selection circuit.

In some embodiments, the chip further comprises:

the third isolation unit is connected between the output end of one AND gate of the clock module and the memory; and the third isolation unit is used for isolating the AND gate and the corresponding storage unit when the AND gate of the clock module does not output a clock signal.

The chip provided by the embodiment of the disclosure is provided with a first power domain module and a second power domain module which work independently, and when the test module tests the memory, the service function module is powered off by the first power domain module; and powering off the test module by using the second power domain module when executing the service function. Therefore, the service function module has no extra power consumption when testing, and the test module has no extra power consumption when executing the service function, thereby effectively saving the power consumption of the chip compared with the prior art.

Drawings

Fig. 1 is a block diagram of a chip according to an embodiment of the disclosure.

Fig. 2 is a block diagram of a second chip according to an embodiment of the disclosure.

Fig. 3 is a block diagram of a chip according to an embodiment of the disclosure.

Fig. 4 is a block diagram of a chip according to an embodiment of the disclosure.

Fig. 5 is a schematic diagram of grouping of test modules and memories in a chip according to an embodiment of the disclosure.

Fig. 6 is a schematic diagram of a clock module in a chip according to an embodiment of the disclosure.

Fig. 7 is a schematic diagram two of a clock module in a chip according to an embodiment of the disclosure.

Fig. 8 is a block diagram of a chip according to an embodiment of the disclosure.

Fig. 9 is a block diagram of a chip according to an embodiment of the disclosure.

Fig. 10 is a schematic diagram III of a clock module in a chip according to an embodiment of the disclosure.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. In embodiments of the present application, the terms "first," "second," "third," "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", "a third" and a fourth "may explicitly or implicitly include one or more such feature.

It should be understood that in the description of the embodiments of the present application, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements.

In the embodiment of the application, a power domain (power domain) refers to a region which is formed by different power supply devices and power management devices inside a chip, and aims to ensure that each module inside the chip can obtain stable voltage and current.

MBIST is a built-in self-test (BIST, built-IN SELF TEST) circuit applied to memory, which is a self-test technique embedded in an integrated circuit for testing and diagnosing faults in the circuit. It can be tested during chip fabrication or during chip operation to ensure the correctness and reliability of the circuit.

In the disclosed embodiment, MBIST technology is used to test Memory circuits such as RAM (Random Access Memory) or ROM (Read-Only Memory). Illustratively, MBIST comprises the following major components: first, vector generation circuit: for generating test vectors, i.e. input signals, to simulate different test situations. Second, BIST control circuit: the system consists of a state machine and is used for controlling the flow and the time sequence of the test process. It is responsible for initiating tests, selecting test vectors, controlling test patterns, and processing test results. Third response analyzer: is composed of a comparator and a MISR (Multiple Input SHIFT REGISTER ) for comparing the difference between the actual output and the desired output and generating a test result. The comparator is used to compare the value of each output bit, and the MISR is used to generate a signature or fault fingerprint for fault diagnosis.

The BIST technology has the advantages that automatic testing can be performed in the chip manufacturing process, and testing cost and time are reduced. In addition, the BIST technology can also perform self-checking when the chip runs, so that the reliability and fault tolerance of the system are improved.

However, when the BIST technology is used for testing the memory bank, a great amount of instantaneous power consumption exists, so that the power consumption of the memory bank must be optimally designed, so that the chip is prevented from being damaged during the test, and the reliability of the circuit is greatly affected. In order to optimize the power consumption during MBIST testing, in some embodiments, serial-parallel combination is generally used to perform embedded MBIST design, but with the continuous increase of chip integration, the greater the number of gate stages, the greater the static power consumption of the functional circuits of the chip. However, as the process is advanced, the leakage current is larger, and the static power consumption is higher. Therefore, the embodiment of the disclosure provides a chip for optimizing power consumption during MBIST test aiming at the characteristic of static power consumption.

In the following, a chip provided by an embodiment of the present application will be described with reference to the accompanying drawings, it is to be understood that the accompanying drawings may be used to represent different modules, where some block-to-block inclusion relationships do not represent block-to-block inclusion relationships in an actual chip structure, for example, between the first power domain module 140 and the service function module 120 may be spatially separated. The second power domain module 150 may be spatially separated from the test module 130.

As shown in fig. 1, an embodiment of the present disclosure provides a chip 100, including:

A memory 110, a business function module 120, a test module 130, a first power domain module 140, and a second power domain module 150, wherein:

The first power domain module 140 is configured to disconnect power from the service function module 120 when a test is performed on the memory 110, where the service function module 120 is configured to perform a corresponding service function;

the second power domain module 150 is configured to disconnect power from the test module 130 when the service function is executed, and the test module 130 is configured to execute a test on the memory 110.

Here, the memory 110 includes a memory array, a memory peripheral circuit, and the like. The memory 110 may be a volatile memory such as RAM (Random Access Memory ) like DRAM (dynamic memory), SRAM (static memory), etc. Non-Volatile Memory (NVM) may also be used, including ROM (Read-Only Memory), flash Memory (Flash Memory), and the like. The memory 110 is embedded in the chip 100 using SOC technology.

The service function module 120 is a logic circuit or a chip for implementing a chip function, and a combination thereof, and the service function module 120 may include a controller of a memory for implementing control of operations such as reading, writing, erasing, and the like of the memory, for example.

Test module 130 may include one or more of the MBIST circuits described above, each of which may be used to perform at least one functional test. The test module 130 may be used for testing the memory 110, so that the test module 130 is connected to the memory 110 and may perform operations such as reading and writing on the memory cell array in the memory 110.

In the embodiment of the present disclosure, the first power domain module 140 may include a power source or a related circuit connected to the power source, and is connected to the service function module 120. When the test module is detected to start testing the memory, the first power domain module 140 may disconnect the power supply of the service function module 120 through a circuit module such as a switch, so that the service function module 120 is in a power-down state. Illustratively, the first power domain module 140 may receive an associated indication signal that the test module is beginning to operate, triggering it to turn off the power to the service function module 120.

Accordingly, the second power domain module 150 may also include a power source or related circuitry connected to the power source and connected to the test module 130. The second power domain module 150 is independent of the first power domain module 140. And, the second power domain module 150 may disconnect the power supply of the test module 130 through a circuit module such as a switch, so that the test module 130 is in a power-down state. The second power domain module 150 may also trigger it to disconnect the power to the test module 130 by receiving an associated indication signal to begin performing a service function, for example.

As such, the business function module 120 has no power consumption when performing the test of the memory 110; the test module 130 has no power consumption when performing the service function. Therefore, compared with the situation that the test module and the service function module share the power domain, the scheme can effectively reduce power consumption.

In some embodiments, the first power domain module 140 is further configured to supply power to the service function module when performing the service function;

the second power domain module 150 is further configured to supply power to the test module when the memory test is performed.

In the disclosed embodiment, the first power domain module 140 may be a power source and related circuitry for powering the business function module 120, and the second power domain module 150 may be a power source and related circuitry for powering the test module 130.

When the test is required, the second power domain module supplies power to the test module 130, so that the test module 130 can perform test operations, including operations such as reading and writing to the memory 110. At this time, the first power domain module disconnects the power supply of the service function module 120, so that the service function module 120 is in a non-powered state. Therefore, at this time, the clock and other components in the service function module 120 do not operate, and thus there is no power consumption.

When the service function is required to be used and the test is not required, the first power domain module supplies power to the service function module 120, so that the service function module 120 can perform related control operations on the memory 110. At this time, the second power domain module cuts off the power supply to the test module, so that each circuit in the test module does not work, and therefore, no power consumption exists.

Of course, in some embodiments, if testing is required while performing the service function, the first power domain may supply power to the service function module 120 while the second power domain supplies power to the test module 130. Thus, both can operate simultaneously, and of course, both can also generate corresponding power consumption.

It can be understood that by the above design of distinguishing the power domains used by the service functional module and the test module, the power consumption of the service functional module and the test module can be controlled independently. Compared with the related technology that the service function module does not work but has power consumption during testing or the service function is not used normally but the power consumption of the testing module exists during testing, the scheme of the embodiment of the application can effectively save the power consumption.

In some embodiments, as shown in fig. 2, the chip 100 further comprises:

A first isolation unit 210 connected between the test module 130 and a pin of the memory 110; the first isolation unit 210 is configured to isolate the test module 130 from the memory 110 when performing the service function.

In an embodiment, the test module 130 may include a plurality of signal terminals respectively connected to pins of the memory 110 for signal transmission therebetween. The first isolation unit 210 may be disposed between each pin of the memory 110 and each terminal of the test module 130, and may switch the on/off state of the first isolation unit, and when the first isolation unit is turned on, signals may be transmitted, so that the test module 130 may test the memory 110. When the first isolation unit 210 is disconnected, the test module 130 and the memory 110 can be isolated, so that signal interference and electric leakage between the memory 110 and the test module 130 are reduced, and static power consumption is reduced.

In some embodiments, the first isolation unit 210 is turned on when the test module 130 is powered on, and an output signal or data of the test module 130 is input to the memory 110 through the first isolation unit 210; or the data output from the memory 110 is transmitted to the test module 130 through the first isolation unit 210.

In some embodiments, the first isolation unit 210 is connected between a first control signal end of the test module 130 and a corresponding first pin on the memory 110, where the first isolation unit 210 is specifically configured to: isolating a first control signal of the first control signal end into an invalid state when the service function is executed; wherein the first control signal is used to control the memory 110 when a test of the memory 110 is performed.

Here, the first isolation unit 210 is not required to be disposed at the data input/output ends of the test module 130 and the memory 110, but may connect the first control signal end with the corresponding first pin, so that the first control signal is in an inactive state by isolating the signal transmission between the first control signal end and the first pin when the test is not required. That is, the first isolation unit 210 invalidates the first control signal output from the test module 130 to the memory 110, so that the test of the memory cannot be realized.

In some embodiments, as shown in fig. 3, the chip 100 further comprises:

A second isolation unit 310 connected between the service function module 120 and a pin of the memory 110; the second isolation unit 310 is configured to isolate the service function module 120 from the memory 110 when performing a test on the memory 110.

In the embodiment of the present disclosure, the service function module 120 may also have a plurality of signal terminals respectively connected to the pins of the memory 110 for implementing signal transmission between the two. The second isolation unit 310 is connected between one or more signal terminals of the service function module 120 and pins of the memory 110, and can switch on/off states thereof. The signal may be transmitted when turned on so that the service function module 120 may perform a corresponding service function using the memory 110. When the second isolation unit 310 is opened, the service function module 120 and the memory 110 can be isolated, so that signal interference and electric leakage between the memory 110 and the service function module are reduced, and static power consumption is further reduced. In some embodiments, when the service function module 120 is powered on, the second isolation unit 310 is turned on, and the output signal or data of the service function module 120 is transmitted to the memory 110 through the second isolation unit 310, and the data output from the memory may also be transmitted to the service function module 120 through the second isolation unit 310.

In some embodiments, the second isolation unit 310 is connected between a second control signal end of the service function module 120 and a corresponding second pin on the memory 110, where the second isolation unit 310 is configured to: isolating the second control signal at the second control signal terminal to an inactive state while performing the test on the memory 110; wherein the second control signal is used to control the memory 110 when the service function is performed.

Here, the second isolation unit 310 is not required to be disposed at the data input/output ends of the service function module 120 and the memory 110, but may connect the second control signal end with the corresponding second pin, so that the second control signal is in an inactive state by isolating the signal transmission between the second control signal end and the second pin when the service function is not required to be performed. That is, the second isolation unit 310 invalidates the second control signal output from the service function module 120 to the memory 110, so that the corresponding service function cannot be implemented.

In some embodiments, as shown in fig. 4, the chip 100 further includes: a third power domain module 410 for powering the memory 110 and/or the clock module 420; wherein the third power domain module 410 is independent of the first power domain module 140 and the second power domain module 150; the clock module 420 is configured to provide a clock signal to the memory 110 when performing the service function or testing the memory 110.

In one embodiment, the third power domain module 410 supplies power to the memory 110 and the clock module 420.

In another embodiment, the third power domain module 410 includes a first sub-power domain module and a second sub-power domain module that are independent of each other, wherein the first sub-power domain module provides power to the memory 110; the second sub-power domain module provides power to the clock module 420.

Since it is also necessary to ensure that the service function module 120 and the test module 130 can perform operations on the memory 110 and use clock signals provided by the clock module 420, respectively, in the case where the first power domain module 140 and the second power domain module 150 are isolated from each other; it is therefore necessary to delineate separate power domains for memory 110 and clock module 420 as well.

The disclosed embodiments provide the third power domain module 410 described above for powering the memory 110 and/or the clock module 420.

In this way, the second power domain module 150 may be enabled to supply power to the test module 130 when the test is needed, and the third power domain module 410 may be used to supply power to the memory 110, and the third power domain module 410 may also be used to supply power to the clock module 420 when the clock signal is needed. In this way, test module 130 may implement testing of memory 110. Also, the first power domain module 140 at this time cuts off the power supply to the service function module 120, and thus there is no power consumption.

When the service function is needed to operate the memory 110, the first power domain module 140 may be used to power the service function module 120, while the third power domain module may be used to power the memory 110, and when the clock signal is needed, the third power domain module 410 may also be used to power the clock module 420. In this way, the business function module 120 can implement operations on the memory 110. Accordingly, the second power domain module 150 cuts off power to the test module 130 at this time, thereby saving power consumption.

It should be noted that, the clock module 420 may provide clock signals of various portions of the chip 100, and specifically, the clock module 420 may provide clock signals required for reading and writing to the memory 110. Since the clock signal used when the test module 130 tests the memory may be different from the clock signal used when the service function module 120 is used to control the memory 110 to read and write. Thus, clock module 420 may provide clock signals of different frequencies to memory 110 under different circumstances.

In addition, the clock module 420 may also provide the required clock signal for the service function module 120 and the required clock signal for the test module 130. The clock module 140 may also output multiple identical or different clock signals simultaneously to different circuit modules. These clock signals may be aligned to enable signal synchronization when different circuit modules are operating. Of course, the clock module 420 may also provide clock signals having a phase difference, i.e., not aligned.

Illustratively, the clock module 420 may include a crystal oscillator that generates a fixed frequency clock signal when the clock module 420 is powered up. In addition, the clock module 420 may further include several frequency dividing circuits for dividing the clock signal generated by the crystal oscillator one or more times, so as to generate clock signals with different frequencies. The clock module 420 may further include a plurality of delay circuits for delaying clock signals generated by the crystal oscillator or clock signals with different frequencies after frequency division to obtain clock signals with different phases.

In some embodiments, as shown in fig. 5, the memory 110 includes a plurality of grouped memory cells 111, and different groups of memory cells use different clock signals clk;

the test module 130 includes a plurality of grouped test circuits 131; the test circuits of the same group are used to test the memory cells of the same group.

Here, the size of the memory cells 111 corresponding to each group may be different for different test circuit 131 groups, and thus the serial length may also be different. Thus, the run time of each set of test circuits 131 will also be different. Different clock signals may be used for the test circuits 131 and the memory cells 111 of the different groups, and conversely, the same clock signal may be used for the same group of test circuits 131 and memory cells 111. In this way, the clock module 420 may supply power to the storage units 111 of different groups, so that the test modules 130 of different groups may be controlled to perform the test, respectively.

However, for the whole chip, as long as a set of test circuits is running, all memory operations are always on, which results in greater power consumption.

Thus, in some embodiments, as shown in fig. 6, the clock module 420 includes:

At least one selection circuit 421; a first input terminal of each selection circuit 421 is configured to receive a test operation signal bist _en indicating whether a set of the test circuits 131 is operated, a second input terminal is configured to receive a service function enable signal work_en indicating whether the service function module 120 is operated, and a control terminal is configured to receive a mode selection signal test_mode; wherein the mode selection signal test_mode is used for instructing the selection circuit 141 to output the service function enabling signal work_en or the test running signal bist _en; the output signal is a clock gating signal gate_en for indicating whether to output a clock signal;

At least one and gate 422; the first input terminal of each and gate 422 is used for receiving the clock signal work_clk used by a group of memory cells, and the second input terminal is connected to the output terminal of the selection circuit, and is used for receiving a service function enable signal or the test running signal.

In some embodiments, as shown in fig. 7, the clock module 420 further includes:

the test control module 423 includes at least one output terminal for outputting the test running signal bist _en, and each output terminal is connected to one of the selection circuits 421.

The number of output terminals of the test control module 423 may be the same as the number of test circuit groups, i.e. one output terminal for each group of test circuits. The test running signal bist _ eni (i is an integer greater than or equal to 1) output by the output terminal is used to indicate whether the set of test circuits is running. Accordingly, it is

Thus, each test running signal bist _ eni output by the test control module 423 can control the output of a corresponding clock signal to each group of test circuits, respectively.

In some embodiments, as shown in fig. 8, the chip 100 further includes:

A third isolation unit 710 connected between the output of an and gate of the clock module 420 and the memory; the third isolation unit 710 is configured to isolate the and gate and the corresponding memory unit when the and gate of the clock module does not output the clock signal.

In the embodiment of the present disclosure, the first isolation unit 710 may switch the on-off state, and when the first isolation unit is turned on, a signal may be transmitted between the clock module 420 and the memory, so that the clock signal is transmitted to the memory. When the third isolation unit 710 is turned off, signal transmission between the clock module 420 and the memory can be isolated.

In this way, the noise signal generated by the unused clock circuit can be prevented from interfering with the memory cell. Meanwhile, the electric leakage among different power domains can be reduced, so that the power consumption is further reduced.

Embodiments of the present disclosure also provide examples of:

DFT (Design For Test), in which various hardware logic For improving the testability (including controllability and observability) of the chip is inserted in the stage of the original Design of the chip, detects whether the chip has defects in the manufacturing process, and is used For a sieve sheet before mass production. That is, the chip comprises a service function design and a DFT aided test design which are needed to be realized, and the DFT design needs to be forbidden to be enabled when the service is applied, otherwise, the service function design is uncontrollable. In DFT screen bars, the functional design does not work. And for MBIST in DFT, it is an independent built-in self-test circuit, and only the MBIST circuit is required to work when MBIST is tested. And during DFT test, the power supply of the chip comes from external irrigation, and the whole chip is in a power-on state. Based on the above background, there are two problems:

for the traditional circuit, the MBIST and the functional circuit are in the same power domain, and other circuits of the chip are in a non-working and power-on state during MBIST test, so that certain static power consumption can be generated, and the instant power consumption during MBIST can be increased. Conversely, when the chip applies the service, the MBIST is in a non-working and powered-on state, and with the high-density integration of the embedded memory, the static power consumption of a large number of MBIST circuits generates a certain challenge to the low power consumption of the chip, and the overall performance of the chip is affected.

For MBIST packets, the corresponding memory cell sizes are different for each group, and the serial lengths (step) are also different, so are the test run times for each group. For the whole chip, as long as a group of MBIST is running, all the memory working clocks are in an on state, and the continuous inversion of the clocks increases the power consumption during test.

In view of the first problem, the embodiment of the present disclosure provides a structure as shown in fig. 9. In the structure, a power domain (MBIST domain) is divided for all MBISTs independently, a service power domain (FUNC domain) is divided for a service function module, a power domain (RAM domain) is divided for a memory and memory controller, a power domain (CLK_GEN domain) is divided for a clock generation module, and the RAM domain and the CLK_GEN domain are in power-on states in service application and MBIST test so as to provide a memory working clock and access the memory. The MBIST domain is isolated from the RAM by an isolation unit (ISO). It will be appreciated that isolation may be performed for signals that are prone to power consumption and not for signals that are not prone to power consumption. Illustratively, signals 1 through 7 from the MBIST domain to the RAM in the figures are isolated by ISO, and signals from the RAM to the MBIST domain, such as DATA (DATA), may not require isolation. When the MBIST is tested, the MBIST domain is electrified, the FUNC domain is powered down, and the memory test is directly carried out; when the business is applied, the MBIST domain is powered down, the FUNC domain is powered up, and the TEST related control signals of the MBIST are isolated into an invalid state. Thus, the static power consumption of the FUNC domain can be saved when the MBIST is applied, and the static power consumption of the MBIST circuit can be saved when the service function is applied.

For problem two, the disclosed embodiments provide a circuit as shown in fig. 10. The circuit is used for providing a working clock of a memory, a test control module BIST_CTR outputs a test working signal BIST _run (1 to N, N is an integer greater than or equal to 0) of each memory array to be corresponding BIST _gate_en, then the test control module BIST_mbist_mode is 1 when MBIST is tested, BIST _gate_en is selected, and a function gating signal work_gate_en is selected when function is applied. The output gate of the selector acts on the gating of the memory operating clock so that the clock is active when MBIST and is off when testing is complete. If the clock signal work_clk used by each memory array is the same, then the selection circuit may be multiplexed to OR the respective test operation signals bist _run (1 through N), and bist _gate_en may be enabled when any one or more of the test circuits are running. When the selector selects the test mode, if bist _gate_en is enabled, GATE outputs the clock signal mem_clk of the memory, and if bist _gate_en is not enabled, i.e., the test operation signals bist _run (1 to N) are all 0, no test circuit is operated, no clock signal is output at this time, thereby reducing power consumption.

Therefore, unnecessary power consumption expenditure is saved through power domain division, instant power consumption is reduced in DFT test, and reliability of the sieve sheet is ensured. And in the service application, static power consumption caused by a test circuit is avoided, and the performance of the chip is improved. And meanwhile, during MBIST test, the clock is automatically and dynamically controlled, so that unnecessary power consumption is reduced.

It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is merely an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about the changes or substitutions within the technical scope of the present disclosure, and should be covered by the protection scope of the present disclosure.

Claims (11)

1. A chip, comprising:

memory, business function module, test module, first power domain module and second power domain module, wherein:

The first power domain module is used for disconnecting the power supply of the service function module when the test of the memory is executed, and the service function module is used for executing corresponding service functions;

The second power domain module is used for disconnecting the power supply of the test module when the service function is executed, and the test module is used for executing the test on the memory.

2. The chip of claim 1, wherein the first power domain module is further configured to power the business function module when performing the business function;

the second power domain module is further configured to supply power to the test module when the memory test is performed.

3. The chip of claim 1, wherein the chip further comprises:

A first isolation unit connected between the test module and a pin of the memory; the first isolation unit is used for isolating the test module from the memory when the service function is executed.

4. The chip of claim 3, wherein the first isolation unit is connected between a first control signal terminal of the test module and a corresponding first pin on the memory, and the first isolation unit is specifically configured to: isolating a first control signal of the first control signal end into an invalid state when the service function is executed; wherein the first control signal is used to control the memory when a test of the memory is performed.

5. The chip of claim 1, wherein the chip further comprises:

The second isolation unit is connected between the service function module and a pin of the memory; the second isolation unit is used for isolating the business function module from the memory when the test of the memory is executed.

6. The chip of claim 5, wherein the second isolation unit is connected between a second control signal terminal of the service function module and a corresponding second pin on the memory, and the second isolation unit is configured to: isolating a second control signal of the second control signal terminal into an invalid state when a test of the memory is executed; wherein the second control signal is used to control the memory when the service function is performed.

7. The chip of claim 1, wherein the chip further comprises: a third power domain module for powering the memory and/or clock module; wherein the third power domain module is independent of the first power domain module and the second power domain module; the clock module is used for providing a clock signal for the memory when the service function is executed or the memory is tested.

8. The chip of claim 7, wherein the memory includes a plurality of grouped memory cells, different groups of memory cells using different ones of the clock signals;

The test module comprises a plurality of grouped test circuits; the test circuits of the same group are used to test the memory cells of the same group.

9. The chip of claim 8, wherein the clock module comprises:

At least one selection circuit; the first input end of each selection circuit is used for receiving a test operation signal indicating whether a group of test circuits operate or not, the second input end is used for receiving a service function enabling signal indicating whether the service function module operates or not, and the control end is used for receiving a mode selection signal; the mode selection signal is used for indicating the selection circuit to output the service function enabling signal or the test running signal;

At least one AND gate; the first input end of each AND gate is used for receiving the clock signals used by a group of memory units, and the second input end is connected with the output end of the selection circuit and used for receiving service function enabling signals or the test running signals.

10. The chip of claim 9, wherein the clock module further comprises:

The test control module comprises at least one output end for outputting the test running signal, and each output end is respectively connected with one selection circuit.

11. The chip of claim 9, wherein the chip further comprises:

the third isolation unit is connected between the output end of one AND gate of the clock module and the memory; and the third isolation unit is used for isolating the AND gate and the corresponding storage unit when the AND gate of the clock module does not output a clock signal.