CN118367908A - Transistor element with gate current splitting capability and related method - Google Patents

Abstract

The present disclosure relates to transistor elements having gate current splitting capability and related methods. A transistor assembly with gate current splitting capability includes a first Field Effect Transistor (FET), a first pull-up current source, a first pull-down current source, a first switching device, a control circuit, a capacitor, and a second FET. The first FET is an N-channel FET that includes a first gate, a first drain, and a first source. The first drain is electrically coupled to a first power source. Each of the pull-up current source and the pull-down current source is electrically coupled to the first gate. The first switching device is electrically coupled in series with the first pull-down current source and is controlled by a first control signal. The control circuit is at least partially powered by the second power source and generates the first control signal. The capacitor and the second FET cooperate to shunt current away from the first gate during a pre-power operating state of the transistor assembly.

Description

Transistor element with gate current splitting capability and related method

Background

Transistors are widely used in circuits, for example for switching or amplifying. Examples of transistors include, but are not limited to, field Effect Transistors (FETs), bipolar Junction Transistors (BJTs), and insulated gate bipolar junction transistors (IGBTs). FETs are widely used in modern integrated circuits and a given integrated circuit may include many FETs. FETs have a high gate impedance and thus FETs can be considered voltage controlled devices.

Disclosure of Invention

In a first aspect, a transistor assembly having gate current splitting capability, comprises: (1) a first Field Effect Transistor (FET) comprising a first gate, a first drain, and a first source, the first FET being an N-channel FET and the first drain being electrically coupled to a first power supply, (2) a first pull-up current source electrically coupled to the first gate, (3) a first pull-down current source electrically coupled to the first gate, (4) a first switching device electrically coupled in series with the first pull-down current source, the first switching device configured to be controlled by a first control signal, (5) a control circuit at least partially powered by a second power supply and configured to generate the first control signal to control an operating state of the first FET, and (6) a capacitor and a second FET, collectively configured to shunt current away from the first gate during a pre-power operating state of the transistor assembly characterized at least in part by (a) the first power supply being active and (b) the second power supply being passive.

In an embodiment of the first aspect, the capacitor is electrically coupled to a gate of the second FET.

In another embodiment of the first aspect, (1) the second FET is an N-channel FET comprising a second gate, a second drain, and a second source, (2) the second drain is electrically coupled to the first gate, and (3) the capacitor is electrically coupled between the first power source and the second gate.

In another embodiment of the first aspect, the second source is electrically coupled to the first source.

In another embodiment of the first aspect, the second source is electrically coupled to a reference node.

In another embodiment of the first aspect, the transistor assembly further comprises a second switching device configured to discharge a gate-to-source capacitance of the second FET in response to a second control signal generated by the control circuit.

In another embodiment of the first aspect, the control circuit is further configured to assert the second control signal when the second power supply is active, thereby causing the second switching device to operate in its on-state.

In another embodiment of the first aspect, the transistor assembly further comprises a resistor, the second switching device and the resistor being electrically coupled in series between the second gate and a reference node.

In another embodiment of the first aspect, the transistor assembly further comprises a second switching device configured to discharge a gate-to-source capacitance of the second FET in response to a second control signal generated by the control circuit.

In another embodiment of the first aspect, the control circuit is further configured to assert the second control signal to operate the second switching device in its on state when the second power supply is active.

In a second aspect, a method for shunting current from a gate of a first N-channel Field Effect Transistor (FET) including a drain electrically coupled to a first power supply includes the steps of: (1) Charging a gate-to-source capacitance of the second N-channel FET via a capacitor electrically coupled to a gate of the second N-channel FET; and (2) shunting current away from the gate of the first N-channel FET via the second N-channel FET, the drain of the second N-channel FET being electrically coupled to the gate of the first N-channel FET.

In an embodiment of the second aspect, shunting current away from the gate of the first N-channel FET via the second N-channel FET includes shunting current around the gate-to-source capacitance of the first N-channel FET.

In another embodiment of the second aspect, shunting current away from the gate of the first N-channel FET via the second N-channel FET includes shunting current from the gate of the first N-channel FET to a reference node.

In another embodiment of the second aspect, the method further comprises discharging a gate-to-source capacitance of the second N-channel FET once the second power supply becomes active.

In another embodiment of the second aspect, the second power supply is configured to supply power to a control circuit configured to control an operating state of the first N-channel FET.

In a third aspect, a circuit configured to be electrically coupled to a load includes (1) a first power supply, (2) a second power supply, and (3) a transistor assembly. The transistor assembly includes: (1) A first Field Effect Transistor (FET) and a second FET configured to be electrically coupled in series between the first power source and the load, each of the first FET and the second FET being a respective N-channel FET, (2) a control circuit at least partially powered by the second power source, the control circuit configured to control a respective operating state of each of the first FET and the second FET; and (3) a capacitor and a third FET collectively configured to shunt current away from a gate of the first FET during a pre-power operating state of the transistor assembly, the pre-power operating state of the transistor assembly characterized at least in part by (a) the first power supply being active and (b) the second power supply being passive.

In an embodiment of the third aspect, the load comprises a camera.

In another embodiment of the third aspect, (1) a third FET includes a gate and a drain, (2) the capacitor is electrically coupled between the first power supply and the gate of the third FET, and (3) the drain of the third FET is electrically coupled to the gate of the first FET.

In another embodiment of the third aspect, a source of the third FET is electrically coupled to one of (a) a power supply of the first FET and (b) a reference node.

In another embodiment of the third aspect, the circuit further comprises a switching device configured to discharge a gate-to-source capacitance of the third FET in response to a signal asserted after the second power supply is active.

Drawings

Fig. 1 is a schematic diagram of a circuit including a transistor assembly and two power supplies.

Fig. 2 is a graph illustrating one example of a power sequence during start-up of the circuit of fig. 1.

FIG. 3 is a schematic diagram of the circuit of FIG. 1, showing one example of the operation of the circuit during a pre-power state.

Fig. 4 is a cross-sectional view of an embodiment of a Field Effect Transistor (FET) of the transistor assembly of fig. 1.

Fig. 5 is a schematic diagram of a circuit including a transistor element with gate current splitting capability, according to an embodiment.

Fig. 6 is a graph showing one example of a power sequence during start-up of the circuit of fig. 5.

Fig. 7 is a schematic diagram of the circuit of fig. 5, showing one example of the operation of the circuit during a pre-power state.

Fig. 8 is a schematic diagram of one embodiment of a pull-up current source of the transistor assembly of fig. 5.

Fig. 9 is a schematic diagram of one embodiment of a pull-down current source of the transistor assembly of fig. 5.

Fig. 10 is a schematic diagram of an alternative embodiment of the circuit of fig. 5, wherein the FET is configured to shunt gate current to ground.

Fig. 11 is a schematic diagram of an alternative embodiment of the circuit of fig. 5 with one FET and related elements omitted.

Fig. 12 is a schematic diagram of an alternative embodiment of the circuit of fig. 5 further including a protection circuit.

Fig. 13 is a schematic diagram of one embodiment of a protection circuit of the circuit of fig. 12.

Fig. 14 is a schematic diagram of another embodiment of a protection circuit of the circuit of fig. 12.

Fig. 15 is a schematic diagram of an embodiment of the circuit of fig. 5, wherein the load is implemented by a camera.

Fig. 16 includes five graphs illustrating one example of the operation of the circuit of fig. 1.

Fig. 17 includes five graphs illustrating one example of the operation of the embodiment of the circuit of fig. 5.

Detailed Description

Many circuits operate using two or more power supplies. For example, fig. 1 is a schematic diagram of a circuit 100, the circuit 100 including a transistor assembly 102, a first power supply 104, a second power supply 106, and a load 108. The first power supply 104 has a voltage V _h and the second power supply 106 has a voltage V _c. Transistor assembly 102 includes a Field Effect Transistor (FET) 110, a pull-up current source 112, a pull-down current source 114, a switching device 116, a control circuit 118, a FET 120, a pull-up voltage source 122, a pull-down current source 124, and a switching device 126. Each of FETs 110 and 120 is an N-channel FET including a respective gate (G), a respective drain (D), and a respective source (S). The drain of FET 110 is electrically coupled to first power supply 104, and the source of FET 110 is electrically coupled to the source of FET 120. The drain of FET 120 is electrically coupled to load 108.

The gate of FET 110 is electrically coupled to each of pull-up current source 112 and switching device 116, and switching device 116 is electrically coupled between the gate of FET 110 and pull-down current source 114. The switching device 116 is controlled by a control signal Φ1 generated by a control circuit 118. Similarly, the gate of FET 120 is electrically coupled to each of pull-up current source 122 and switching device 126, and switching device 126 is electrically coupled between the gate of FET 120 and pull-down current source 124. The switching means 126 are also controlled by a control signal Φ1 generated by the control circuit 118. In this document, a "pull-up current source" is a current source configured to charge a gate capacitance of a FET, such as a gate-to-source capacitance and/or a gate-to-drain capacitance. Conversely, a "pull-down current source" is a current source configured to discharge the gate capacitance of a FET, such as a gate-to-source capacitance and/or a gate-to-drain capacitance.

The control circuit 118 is powered by the second power supply 106. Thus, the control circuit 118 is not operational unless the second power supply 106 is active. Pull-up current source 112, pull-down current source 114, pull-up current source 122, and pull-down current source 124 are directly or indirectly powered by first power source 104 and/or second power source 106. In this document, the term "ground" (designated by the downward triangular arrow in the figure) may be any reference node, including a ground, chassis ground, or a reference node that is at a different potential than ground or chassis ground.

The transistor assembly 102 is configured as a switch assembly, wherein the transistor assembly 102 controls the flow of the current I _load to the load 108 in response to a control signal Φ1 generated by the control circuit 118. Specifically, when the control signal Φ1 is inactive, the switching device 116 is in its off state, and the pull-up current source 112 accordingly charges the gate-to-source capacitance (not shown in fig. 1) of the FET 110, such that the voltage V _gs between the gate and source of the FET 110 is greater than the threshold gate-to-source voltage of the FET 110. Thus, FET 110 is in its on state. Similarly, when control signal Φ1 is inactive, switching device 126 is in its off state, and pull-up current source 122 accordingly charges the gate-to-source capacitance (not shown in fig. 1) of FET 120, such that voltage V _gs between the gate and source of FET 120 is greater than the threshold gate-to-source voltage of FET 120. Thus, FET 120 is also in its on state. Thus, when the control signal Φ1 is inactive, both FETs 110 and 120 are in their respective conductive states, which allows current I _load to flow from the first power supply 104 to the load 108. In this document, a switching device (e.g., a transistor) is in an "off state" when the switching device is in a non-conductive state (ignoring possible parasitic current paths, e.g., through a body diode of a FET), and in an on state when the switching device is in a conductive state.

When the control signal Φ1 is asserted, the switching device 116 is in its on state, and the pull-down current source 114, which has a larger current magnitude than the pull-up current source 112, prevents the pull-up current source 112 from charging the gate-to-source capacitance of the FET 110. Thus, the voltage V _gs of FET110 is lower than the gate-to-source threshold voltage of FET110, and FET110 is therefore in its off state. Similarly, when control signal Φ1 is asserted, switching device 126 is in its on state and pull-down current source 124 has a greater current magnitude than pull-up current source 122, preventing pull-up current source 122 from charging the gate-to-source capacitance of FET 120. Thus, the voltage V _gs of FET 120 is lower than the gate-to-source threshold voltage of FET 120, and FET 120 is therefore in its off state. Thus, when the control signal Φ1 is active, both FETs 110 and 120 are in their respective off states, and together, the two FETs block current I _load from flowing to load 108. It should be noted that the respective body diodes 128 and 130 of FETs 110 and 120 have opposite orientations relative to current I _load, which prevents current I _load from flowing through body diodes 128, 130 when FETs 110 and 120 are in their respective off states.

The first power supply 104 and the second power supply 106 may become active at different times during start-up of the circuit 100, for example if the second power supply 106 is generated from a voltage regulator powered by the first power supply 104. In this document, a power supply is an "active" power supply if the power supply voltage is at a non-zero steady state value, e.g., the voltage is at a predetermined prescribed value within a prescribed tolerance range. For example, if the voltage of the power supply is in the range of 4.5 volts to 5.5 volts, a power supply designated to provide a voltage of 5 volts within +/-10% tolerance value is effective. In contrast, in this document, the power supply is "inactive" if the power supply voltage is zero or not at a steady state value. For example, a power supply that provides a voltage of 5 volts within +/-10% tolerance is designated as an inactive power supply if its voltage is outside the range of 4.5 volts to 5.5 volts.

Fig. 2 is a graph 200 of voltage versus time showing one example of a power sequence during start-up of circuit 100. Graph 200 includes a graph representing each of voltage V _h of first power supply 104 and voltage V _c of second power supply 106. The circuit 100 starts at time t ₀ and the first power supply 104 reaches its steady state voltage V _{h_s} at time t ₁. However, the second power supply 106 does not reach its steady state value V _{c_s} until a significantly later time t ₂. For example, the second power supply 106 may be generated by a linear regulator or by a switching power converter powered by the first power supply 104, and the linear regulator or switching power converter may not be able to start until the first power supply 104 is activated. during the pre-power-up state of the transistor assembly 102 between times t ₀ and t ₂, therefore, the first power supply 104 is active, i.e. its voltage V _h is at its steady-state value V _{h_s}, While the second power supply 106 is inactive, i.e. its voltage V _c is not at its steady state value V _{c_s}. The first power supply 104 and the second power supply 106 are both active in the power-on state of the transistor assembly 102, which begins when the pre-power-on state of time t ₂ ends. During the pre-power state, i.e., the first power source 104 is active and the second power source 106 is inactive, differences in power operating states can be problematic.

For example, fig. 3 is a schematic diagram of circuit 100, illustrating one example of the operation of circuit 100 during a pre-power-up state of transistor assembly 102. Fig. 3 symbolically shows the gate-to-source capacitance C _gs and the gate-to-drain capacitance C _gd of FET 110. Assume that the transistor component 102 operates in its pre-power state in the example of fig. 3, in which the first power supply 104 is active but the second power supply 106 is inactive. The control circuit 118 is inoperable because the second power source 106 is inactive. Thus, control circuit 118 is unable to control the operating state of FET 110 or FET 120 during the pre-power-up state. Further, pull-up current source 112, pull-down current source 114, pull-up current source 122, and pull-down current source 124 are also typically inoperable during the pre-power-up state.

However, during the pre-power state, due to the rise in voltage V _h of the first power supply 104, current I _gd flows through the gate-to-drain capacitance C _gd and current I _gs flows through the gate-to-source capacitance C _gs. The current flowing through the capacitor is proportional to the change in voltage across the capacitor over time, so the magnitude of each of current I _gd and current I _gs will increase with increasing slope dv/dt of the first supply voltage V _h (see fig. 2). Current I _gs will charge gate-source capacitance C _gs and can raise voltage V _gs above the threshold gate-source voltage of FET 110, thereby operating FET 110 in its on state and not blocking the flow of current I _load.

Further, once FET 110 begins to operate in its on state, FET 120 will provide a path for current I _load. For example, fig. 4 is a cross-sectional view of FET 400 as one possible embodiment of FET 120. FET 400 includes a p-type substrate (PSUB) 402, a deep n-type well (DNWELL) 404, a p-type well (PWELL) 406, and a gate 408.FET 400 additionally forms a drain 410, a source 412, a body diode 414, and a parasitic PNP Bipolar Junction Transistor (BJT) 416. Once FET 110 begins to operate in its on state during the pre-power state of transistor assembly 102, a portion of current I _load, referred to as current I _b, will flow through body diode 414 even though FET 120 is in its off state and current I _d is therefore zero. Further, BJT 416 may operate in its on state, causing a portion of current I _load, referred to as substrate current I _sub, to flow through BJT 416. The magnitude of current I _sub may be large due to the current gain of BJT 416 (referred to as beta), which may cause latch-up and permanent damage to FET 400. Thus, if FET 110 is operating in its on state during the pre-power-up state of transistor element 102, FET 120 may provide a path for a substantial current I _load even though FET 120 is in its off state.

Thus, during the pre-power state of the transistor component 102, particularly when the slope dv/dt of the first supply voltage V _h is high, the magnitude of the current I _load may be uncontrolled. Such uncontrolled current I _load may result in improper operation of circuit 100, damage to one or more components of circuit 100 and the circuitry connected to circuit 100, and/or safety issues. This problem can be particularly acute when modern FET fabrication processes are used, where the gate-to-source threshold voltage is relatively low, e.g., about 0.8 volts, so that FET 110 may have a high likelihood of turning on during a pre-power-up state. Thus, the potentially uncontrolled operation of FET 110 in its on state during the pre-power-up state of transistor component 102 can lead to significant problems.

Disclosed herein are novel transistor assemblies with gate current splitting capability and related methods that at least partially address the above-described problems. Some embodiments of the new transistor assembly include a transistor (or other switching device) that shunts current away from the gate of the FET during the pre-power state, thereby minimizing or even eliminating the possibility of uncontrolled operation of the FET in its on state during the pre-power state. Further, some embodiments are capable of operating over a wide range of supply voltage slopes during start-up, and some embodiments do not affect transistor assembly operation during power-on states.

Fig. 5 is a schematic diagram of a circuit 500 including a transistor element 502, first and second power supplies 504, 506, and a load 508, wherein the transistor element 502 is one embodiment of a new transistor element having gate current splitting capability. The first power supply 504 has a voltage V _h and the second power supply 506 has a voltage V _c. Transistor component 502 includes FET 510, pull-up current source 512, pull-down current source 514, switching device 516, control circuit 518, FET 520, pull-up voltage source 522, pull-down voltage source 524, switching device 526, FET 528, capacitor 530, switching device 532, and resistor 534.

Each of FETs 510 and 520 is an N-channel FET including a respective gate (G), a respective drain (D), and a respective source (S). In addition, FETs 510 and 520 include respective body diodes 536 and 538. The drain of FET510 is electrically coupled to first power supply 504, and the source of FET510 is electrically coupled to the source of FET 520. The drain of FET 520 is electrically coupled to load 508. Load 508 is electrically coupled between the drain of FET 520 and ground. Thus, FETs 510 and 520 are electrically coupled in series between first power source 504 and load 508.

The gate of FET 510 is electrically coupled to each of pull-up current source 512 and switching device 516, and switching device 516 is electrically coupled between the gate of FET 510 and pull-down current source 514. In some embodiments, switching device 516 is a transistor, such as an N-channel FET, a P-channel FET, or a BJT. The switching device 516 is controlled by a control signal Φ1 generated by a control circuit 518. In some alternative embodiments, the topological locations of the pull-down current source 514 and the switching device 516 are swapped in the transistor component 502. The gate of FET 520 is electrically coupled to each of pull-up current source 522 and switching device 526, and switching device 526 is electrically coupled between the gate of FET 520 and pull-down current source 524. In some embodiments, switching device 526 is a transistor, such as an N-channel FET, a P-channel FET, or a BJT. In some alternative embodiments, the topological locations of the pull-down current source 524 and the switching device 526 are swapped in the transistor assembly 502. The switching device 526 is also controlled by a control signal Φ1 generated by the control circuit 518. However, in some alternative embodiments, switching device 516 and switching device 526 are controlled by different respective control signals, rather than by a common control signal Φ1. In some embodiments, control signal Φ1 is active when in a logic high state, while in some other embodiments control signal Φ1 is active when in a logic low state.

The control circuit 518 is at least partially powered by the second power supply 506, and the pull-up current source 512, the pull-down current source 514, the pull-up current source 522, and the pull-down current source 524 are optionally directly or indirectly powered by the first power supply 504 and/or the second power supply 506. The control circuit 518 is implemented, for example, by analog electronics and/or digital electronics. Although the control circuit 518 is described as being incorporated within the transistor assembly 502, the control circuit 518 may alternatively be partially or completely external to the transistor assembly 502 without departing from the scope herein. Further, although the control circuit 518 is illustrated as a single element, the control circuit 518 may include multiple elements that need not be collocated. Furthermore, although the control circuit 518 is shown as a discrete element, the control circuit 518 may be partially or fully combined with one or more other elements.

FET 528 is an N-channel FET that includes a gate (G), a drain (D), a source (S), and a body diode 540. The drain of FET 528 is electrically coupled to the gate of FET 510, and the source of FET 528 is electrically coupled to the ground source of FET 510. A capacitor 530 is electrically coupled between the first power supply 504 and the gate of FET 528. The switching device 532 and the resistor 534 are electrically coupled in series between the gate of the FET 528 and ground such that the switching device 532 is electrically coupled between the gate of the FET 528 and ground through the resistor 534. In some alternative embodiments, the topological locations of the switching device 532 and resistor 534 are exchanged in the transistor assembly 502. Furthermore, in some other embodiments, resistor 534 is omitted such that switching device 532 is directly electrically coupled between the gate of FET 528 and ground. The switching device 532 is controlled by a control signal Φ2 generated by the control circuit 518. In some embodiments, switching device 532 is a transistor, such as an N-channel FET, a P-channel FET, or a BJT. In some embodiments, control signal Φ2 is active when in a logic high state, while in some other embodiments control signal Φ2 is active when in a logic low state.

The transistor element 502 is configured as a switch element, wherein the transistor element 502 controls the flow of the current I _load to the load 508 in response to a control signal Φ1 generated by the control circuit 518. Specifically, when the control signal Φ1 is inactive, the switching device 516 is in its off state, and the pull-up current source 512 accordingly charges the gate-to-source capacitance (not shown in fig. 5) of the FET 510, such that the voltage V _gs between the gate and source of the FET 510 is greater than the threshold gate-to-source voltage of the FET 510. Thus, FET 510 is in its on state. Similarly, when control signal Φ1 is inactive, switching device 526 is in its off state, and pull-up current source 522 accordingly charges the gate-to-source capacitance (not shown in fig. 5) of FET 520, such that voltage V _gs between the gate and source of FET 520 is greater than the threshold gate-to-source voltage of FET 520. Thus, FET 520 is also in its on state. Thus, when the control signal Φ1 is inactive, both FETs 510 and 520 are in their respective conductive states, which allows current I _load to flow from the first power supply 504 to the load 508 via FETs 510, 520.

On the other hand, when the control signal Φ1 is active, the switching device 516 is in its on state, and the pull-down current source 514, which has a larger current magnitude than the pull-up current source 512, prevents the pull-up current source 512 from charging the gate-to-source capacitance of the FET 510. Thus, the voltage V _gs is lower than the threshold gate-source voltage of the FET 510, and the FET 510 is therefore in its off state. Similarly, when the control signal Φ1 is active, the switching device 526 is in its on state, and the pull-down current source 524, which has a larger current magnitude than the pull-up current source 522, prevents the pull-up current source 522 from charging the gate-to-source capacitance of the FET 520. Thus, voltage V _gs is lower than the threshold gate-source voltage of FET 520, and FET 520 is therefore in its off state. Thus, when the control signal Φ1 is active, both FETs 510 and 520 are in their respective off states, and together, the two FETs block current I _load from flowing to load 508. Accordingly, the control circuit 518 is configured to control the respective operating states of the FETs 510 and 520 by generating a control signal Φ1. It should be noted that the respective body diodes 536 and 538 of FETs 510 and 520 have opposite orientations with respect to current I _load, which prevents current I _load from flowing through body diodes 536 and 538 when FETs 510, 520 are in their respective off states.

In a manner similar to that discussed above with respect to fig. 1 and 2, the first power supply 504 may become active before the second power supply 506. The control circuit 518 is configured to enable the control signal Φ2 in response to the control circuit 518 being able to control the operational state of at least the FET 510, for example in response to the second power supply 506 being activated. For example, the control circuit 518 may enable the control signal Φ2 in response to the voltage V _c of the second power supply 506 reaching its steady state value, in response to the voltage V _c of the second power supply 506 reaching a predetermined minimum threshold, and/or in response to V _c of the third power supply 506 being within a predetermined range of values.

Fig. 6 is a graph 600 of voltage versus time showing one example of a power sequence during start-up of circuit 500. Graph 600 includes a graph representing each of voltage V _h of first power supply 504, voltage V _c of second power supply 506, and control signal Φ2. The circuit 500 starts at time t ₀ and the first power supply 504 reaches its steady state voltage V _{h_s} at time t ₁. However, the second power supply 506 does not reach its steady state value V _{c_s} until a significantly later time t ₂. For example, the second power supply 506 may be generated by a linear regulator or by a switching power converter powered by the first power supply 504, and the linear regulator or switching power converter may not be able to start until the first power supply 504 is activated. During the pre-power-up state of the transistor assembly 502 between times t ₀ and t ₂, therefore, the first power supply 504 is active, i.e. its voltage V _h is at its steady-state value V _{h_s}, while the second power supply 506 is inactive, i.e., its voltage V _c is not at its steady state value V _{c_s}. Both the first power supply 504 and the second power supply 506 are active in the power-on state of the transistor assembly 502, which begins when the pre-power-on state of time t ₂ ends. When the second power supply 506 is activated, the control circuit 518 enables the control signal Φ2 at time t ₃. As long as the second power supply 506 is active when the control signal Φ2 is asserted by the control circuit 518, the time at which the control signal Φ2 is asserted by the control circuit 518 can be varied to ensure that the control circuit 518 is able to control the operational state of at least the FET 510 when the control signal Φ2 is asserted. For example, in some embodiments, the control circuit 518 is configured to immediately activate the control signal Φ2 in response to the second power supply 506 being activated, and in some other embodiments, the control circuit 518 is configured to activate the control signal Φ2 in response to the second power supply 506 being activated after the delay period expires. Although fig. 6 shows the control signal Φ2 being in a logic high state when active, the control signal Φ2 may have a different polarity, e.g., the control signal Φ2 may be in a logic low state when active.

FET 528 and capacitor 530 are collectively configured to shunt current away from the gate of FET 510 when transistor element 502 is in its pre-power state, thereby reducing or eliminating the possibility of FET 510 operating in its on state, while transistor element 502 is in its pre-power state. For example, fig. 7 is a schematic diagram of circuit 500, showing one example of the operation of circuit 500 during a pre-power state. Fig. 7 symbolically shows the gate-to-source capacitance C _gs and the gate-to-drain capacitance C _gd of FET 510, and fig. 7 also symbolically shows the gate-to-power capacitance C _gs of FET 528. Assume in the example of fig. 6 that the transistor component 502 is operating in its pre-power state, wherein the first power supply 504 is active and the second power supply 506 is inactive. The control circuit 518 is inoperable because the second power supply 506 is inactive. Thus, during the pre-power-up state of transistor element 502, control circuit 518 is unable to control the operating state of FET 510 or FET 520. Further, although not required, pull-up current source 512, pull-down current source 514, pull-up current source 522, and pull-down current source 524 are also typically not operational during the pre-power-up state.

However, current I _cap flows from the first power supply 504 through capacitor 530 to the gate of FET 528 while transistor assembly 502 is in its pre-power state and the magnitude of voltage V _h is changing. Current I _cap charges the gate-source capacitance of FET 528 such that voltage V _gs between the gate and source of FET 528 is greater than the threshold gate-source voltage of FET. Thus, FET 528 is in its on state, and as shown in FIG. 7, FET 524 shunts current I _gd flowing through gate-to-drain capacitance C _gd of FET 510 away from the FET 510 gate via the drain of FET 528, such that current I _gd flows through gate-to-source capacitance C _gs of FET 520 and through body diode 538 of the FET. Thus, the gate-to-source capacitance C _gs of FET 510 is not charged by current I _gd, and the voltage V _gs between the gate and source of FET 510 is therefore less than the threshold gate-to-source voltage of FET 510. Thus, when the transistor component 502 is in its pre-powered state, the FET 510 is non-conductive, thereby preventing the problems discussed above with respect to the circuit 100, wherein the magnitude of the current I _load may not be controlled during the pre-powered state.

As described above, once the second power supply 506 is in its active state, the control circuit 518 asserts the control signal Φ2, which causes the switching device 532 to operate in its on state, discharging the gate-to-source capacitance C _gs of FET 528 to ground through resistor 534, which causes the voltage V _gs between the gate and source of FET 528 to drop less than the threshold gate-to-source voltage of FET 528, causing FET0528 to transition from its on state to its off state. Thus, FET 528 does not affect the operation of transistor element 502 after control circuit 518 enables control signal Φ2. Assuming that the magnitude of the voltage V _h of the first power supply 504 is substantially constant, the magnitude of the current I _cap will typically be minimal once the transistor assembly 502 is operated in its powered state. In any event, switching device 532 will shunt any current I _cap to ground through resistor 534 during the power-on state, thereby preventing FET 528 from operating in its on-state when transistor assembly 502 is operating in its power-on state.

Fig. 8 is a schematic diagram of a pull-up current source 800, which is one possible embodiment of a pull-up current source 512 of the transistor element 502. Pull-up current source 522 may also be implemented in a manner similar to that shown in fig. 8. However, pull-up current sources 512 and 522 are not limited to implementation according to fig. 8.

The pull-up current source 800 includes a current source 802, a first P-channel FET 804, a second P-channel MOSFET 806, and a power supply 808 configured to supply power to the pull-up current source 800. The power supply 808 is, for example, a charge pump power supply powered by the first power supply 504 such that the voltage V _cp of the power supply 808 has a greater magnitude than the voltage V _h of the first power supply 504 to ensure that the pull-up current source 800 is able to charge the gate-to-source capacitance of the FET 510 to a voltage high enough to enable the FET 510 to operate in its on state. For example, in some embodiments where FET 510 has a gate-source threshold voltage of about 1.8 volts, voltage V _cp is at least 1.8 volts greater than voltage V _h. The first P-channel FET 804 and the second P-channel FET 806 are collectively configured to mirror the current of the current source 802, thereby generating a pull-up current I _up for charging the gate-to-supply capacitance of the FET 510.

Fig. 9 is a schematic diagram of a pull-down current source 900, which is one possible embodiment of pull-down current source 514 of transistor element 502. The pull-down current source 524 may also be implemented in a manner similar to that shown in fig. 9. However, pull-down current sources 514 and 524 are not limited to implementation according to fig. 9.

Pull-down current source 900 includes a current source 902, a first N-channel FET 904, and a second N-channel FET 906. The first N-channel FET 904 and the second N-channel FET 906 are collectively configured to mirror the current of the current source 902, thereby generating a pull-down current I _down for discharging the gate-to-source capacitance of the FET 510.

Referring again to fig. 5, as long as the transistor element 502 is capable of shunting current away from the gate of the FET 510 during a pre-power-up state of the transistor element 502, changes may be made to the transistor element 502 without departing from the scope herein. For example, fig. 10 is a schematic diagram of a circuit 1000, the circuit 1000 being an alternative embodiment of the circuit 500 of fig. 5, wherein the transistor element 502 is replaced by a transistor element 1002. Transistor assembly 1002 is similar to transistor assembly 502 except that the source of FET 528 is electrically coupled to ground instead of to the source of FET 510. Thus, in the pre-power state of transistor assembly 1002, FET 528 will shunt current away from the gate of FET 510 and ground.

As another example, fig. 11 is a schematic diagram of a circuit 1100, the circuit 1100 being an alternative embodiment of the circuit 500 of fig. 5, in which the transistor element 502 is replaced by a transistor element 1102. Transistor assembly 1102 is similar to transistor assembly 502 except that FET 520, pull-up current source 522, pull-down current source 524, and switching device 526 are omitted. The transistor assembly 1102 may be used in applications where it is not necessary to be able to block the flow of current I _load having a negative polarity, i.e., current flowing from the load 508 to the first power supply 504, for example, in the transistor assembly 1102.

Referring again to fig. 5, certain alternative embodiments of the transistor assembly 502 further include respective protection circuits for one or more of the FETs 510, 520, and 528 to protect the FETs from excessive gate-to-source voltage magnitudes and/or to protect the FETs from reverse polarity gate-to-source voltages. For example, fig. 12 is a schematic diagram of a circuit 1200, the circuit 1200 being an alternative embodiment of the circuit 500 of fig. 5, in which the transistor element 502 is replaced by a transistor element 1202. Transistor assembly 1202 is similar to transistor assembly 502 except that transistor assembly 1202 also includes protection circuit (P) 1204, protection circuit 1206, and protection circuit 1208. However, in some alternative embodiments, one or both instances of the protection circuit are omitted from the transistor assembly 1202. For example, alternative embodiments of transistor assembly 1202 include protection circuits 1204 and 1206, but omit protection circuit 1208.

Each of the protection circuits 1204, 1206, and 1208 is configured to protect its respective FET 510, 520, and 528 from the magnitude of the excessive gate-to-source voltage V _gs by preventing V _gs from exceeding a predetermined maximum value, such as by clamping the voltage V _gs in response to the voltage V _gs rising to a threshold value. Further, each of the protection circuits 1204, 1206, and 1208 is configured to protect its respective FET 510, 520, and 528 from the gate-source voltage of the reverse polarity by clamping the magnitude of the reverse polarity gate-source voltage V _gs, i.e., the forward conduction voltage of one or more diodes in the event that the magnitude of the voltage at the source is greater than the magnitude of the voltage at the gate.

Fig. 13 is a schematic diagram of a protection circuit 1300, which is one possible embodiment of the protection circuit 1204 of fig. 12. The protection circuit 1206 may also be implemented in a manner similar to that shown in fig. 13. However, the protection circuits 1204 and 1206 are not limited to be implemented according to fig. 13.

The protection circuit 1300 includes a current source 1302, a P-channel FET 1304, a first resistor 1306, a second resistor 1308, and a diode 1310. The current source 1302 is electrically coupled to the gate (G) of the P-channel FET 1304, and the first resistor 1306 is electrically coupled between the gate of the P-channel FET 1304 and the source of the FET 510. Diode 1310 is electrically coupled between the gate and source of FET510 such that the cathode (K) of diode 1310 is electrically coupled to the gate of FET510 and the anode (a) of diode 1310 is electrically coupled to the source of FET 510. The source (S) of the P-channel FET 1304 is electrically coupled to the gate of the FET510, and a second resistor 1308 is electrically coupled between the drain (D) of the P-channel FET 1304 and the source of the FET 510. The current source 1302, the P-channel FET 1304, the first resistor 1306, and the second resistor 1308 together prevent the voltage gate-to-source voltage V _gs of the FET510 from exceeding the voltage V _max by a magnitude, where V _max is defined as V _max＝(I₁₃₀₂*R₁₃₀₆+V_{th_1}), where I ₁₃₀₂ is the magnitude of the current from the current source 1302, R ₁₃₀₆ is the resistance of the first resistor 1306, and V _{th_1} is the gate-to-source threshold voltage of the P-channel FET 1304. Diode 1310 conducts current with a reverse polarity voltage applied between the gate of FET510 and the source of FET510, clamping the magnitude of the reverse polarity voltage to the forward conduction voltage of diode 1310, e.g., about 0.6 volts to 0.7 volts.

Fig. 14 is a schematic diagram of a protection circuit 1400. The protection circuit 1400 is one possible embodiment of the protection circuit 1208 of fig. 12. However, the protection circuit 1208 is not limited to be implemented according to fig. 14. The protection circuit 1400 includes a first N-channel FET 1402, a second N-channel FET 1404, and a third N-channel FET 1406 electrically coupled in series between the gate of FET 528 and the source of FET 528. In particular, each of the gate (G) and the drain (D) of the first N-channel FET 1402 is electrically coupled to the gate of FET 528 and the source (S) of the first N-channel FET 1402 is electrically coupled to each of the drain (D) and the gate (G) of the second N-channel FET 1404. The source (S) of the second N-channel FET 1404 is electrically coupled to each of the drain (D) and gate (G) of the third N-channel FET 1406, and the source of the third N-channel FET 1406 (S) is electrically coupled to the source of FET 528. The first N-channel FET 1402, the second N-channel FET 1404, and the third N-channel FET 1406 collectively limit the gate-source V _gs of the FET 528 to the sum of the respective threshold voltages of each of the three N-channel FETs, e.g., to about 1.8 volts. In addition, the respective body diodes 1408, 1410, and 1412 of N-channel FETs 1402, 1404, and 1406, in combination with resistor 534 (fig. 5), clamp the magnitude of any reverse polarity voltage applied between the gate of FET 528 and the source of FET 528, for example, about the magnitude of the forward turn-on voltages of the three body diodes.

Fig. 15 is a schematic diagram of a circuit 1500, the circuit 1500 being an embodiment of the circuit 500 (fig. 5) in which the load 508 is implemented by a camera 1508. In some embodiments, camera 1508 is a camera of an automobile. However, it should be appreciated that the load 508 (fig. 5) is not limited to a camera, and that the load 508 may be substantially any type of electrical load. For example, in some embodiments, the load 508 includes an inductor of a switched power converter or a capacitor of a switched capacitor converter. Further, the load 508 need not be a discrete component, but may be a circuit, system, or the like. The load 508 also does not need to be referenced to ground.

Applicant has conducted simulations that demonstrate that certain embodiments of the novel transistor assembly with gate current splitting capability can achieve significantly higher performance than transistor assemblies without gate current splitting capability. For example, fig. 16 includes five graphs 1602, 1604, 1606, 1608, and 1610, which illustrate one example of the operation of the circuit 100 (fig. 1) without gate current splitting capability. Each of graphs 1602, 1604, 1606, 1608, and 1610 share a common horizontal axis representing time, where a time of zero corresponds to circuit 100 beginning to start. Graph 1602 shows analog voltage V _h of first power supply 104 versus time, graph 1604 shows analog voltage V _gs of FET 110 versus time, graph 1606 shows analog input current I _in (see fig. 1) versus time, graph 1608 shows analog channel current I _ch of FET 120 versus time, and graph 1610 shows analog substrate current I _sub of FET 120 (see fig. 4) versus time. Each simulation of fig. 16 assumes that the voltage V _h of the first power supply 104 has a slope of 1.6x10 ⁷ picovolts/microsecond during start-up of the circuit 100. As is apparent from the graph of fig. 16, the channel current and the substrate current have large peak amplitudes, i.e., about 36 amps and 3 amps, respectively, during operation of the transistor assembly 102 in the pre-power state. Such large peak current amplitudes are undesirable and may result in improper operation of the circuit 100, damage to one or more components of the circuit 100 and the circuit connected to the circuit 100, and/or safety issues.

Fig. 17 includes five graphs 1702, 1704, 1706, 1708 and 1710 that illustrate one example of the operation of an embodiment of the circuit 500 (fig. 5), the circuit 500 having gate current splitting capability. Each of graphs 1702, 1704, 1706, 1708 and 1710 share a common horizontal axis representing time, where a time of zero corresponds to circuit 500 beginning to start. Graph 1702 shows analog voltage V _h versus time for first power supply 504, graph 1704 shows analog voltage V _gs versus time for FET 510, graph 1706 shows analog input current I _in (see fig. 5) versus time, graph 1708 shows analog channel current I _ch versus time for FET 520, and graph 1710 shows analog substrate current I _sub versus time for FET 520. Each simulation of fig. 17 assumes that the voltage V _h of the first power supply 504 has a slope of 1.6x10 ⁷ picovolts/microsecond during start-up of the circuit 500. The peak channel current and substrate current for the fig. 17 simulation were only about 3 milliamp and 4 milliamp, respectively, which are significantly lower than similar values for the fig. 16 simulation. Thus, simulations of fig. 16 and 17 show that the new transistor assembly with gate current splitting capability is able to achieve significantly lower peak current amplitudes during the pre-power state than a transistor assembly without gate current splitting capability.

Variations may be made in the above methods, apparatus, and systems without departing from the scope hereof. It should be noted, therefore, that what is included in the foregoing description and shown in the accompanying drawings is to be interpreted as illustrative rather than limiting. The following claims are intended to cover all statements of the general and specific features described herein, as well as the scope of the present methods and systems, which, as a matter of language, might be said to fall therebetween.

Claims (20)

1. A transistor element having gate current splitting capability, comprising:

A first Field Effect Transistor (FET) comprising a first gate, a first drain, and a first source, the first FET being an N-channel FET, and the first drain being electrically coupled to a first power supply;

a first pull-up current source electrically coupled to the first gate;

a first pull-down current source electrically coupled to the first gate;

A first switching device electrically coupled in series with the first pull-down current source, the first switching device configured to be controlled by a first control signal;

A control circuit powered at least in part by a second power supply and configured to generate the first control signal to control an operating state of the first FET; and

A capacitor and a second FET collectively configured to shunt current away from the first gate during a pre-power operating state of the transistor assembly characterized at least in part by (a) the first power supply being active and (b) the second power supply being passive.

2. The transistor assembly of claim 1, wherein the capacitor is electrically coupled to a gate of the second FET.

3. The transistor assembly of claim 1, wherein:

The second FET is an N-channel FET including a second gate, a second drain, and a second source;

the second drain is electrically coupled to the first gate; and

The capacitor is electrically coupled between the first power source and the second gate.

4. The transistor component of claim 3 wherein the second source is electrically coupled to the first source.

5. The transistor component of claim 3, wherein the second source is electrically coupled to a reference node.

6. The transistor assembly of claim 3, further comprising a second switching device configured to discharge a gate-to-source capacitance of the second FET in response to a second control signal generated by the control circuit.

7. The transistor assembly of claim 6, wherein the control circuit is further configured to assert the second control signal when the second power supply is active, thereby causing the second switching device to operate in its on state.

8. The transistor assembly of claim 6, further comprising a resistor, the second switching device and the resistor being electrically coupled in series between the second gate and a reference node.

9. The transistor assembly of claim 1, further comprising a second switching device configured to discharge a gate-to-source capacitance of the second FET in response to a second control signal generated by the control circuit.

10. The transistor assembly of claim 9, wherein the control circuit is further configured to assert the second control signal to operate the second switching device in its on state when the second power supply is active.

11. A method for shunting current from a gate of a first N-channel Field Effect Transistor (FET) including a drain electrically coupled to a first power supply, the method comprising:

Charging a gate-to-source capacitance of the second N-channel FET via a capacitor electrically coupled to a gate of the second N-channel FET; and

Current is shunted away from the gate of the first N-channel FET via the second N-channel FET, the drain of which is electrically coupled to the gate of the first N-channel FET.

12. The method of claim 11, wherein shunting current away from a gate of the first N-channel FET via the second N-channel FET comprises shunting current around a gate-to-source capacitance of the first N-channel FET.

13. The method of claim 11, wherein shunting current away from the gate of the first N-channel FET via the second N-channel FET comprises shunting current from the gate of the first N-channel FET to a reference node.

14. The method of claim 11, further comprising discharging a gate-to-source capacitance of the second N-channel FET once a second power supply becomes active.

15. The method of claim 14, wherein the second power supply is configured to supply power to a control circuit configured to control an operating state of the first N-channel FET.

16. A circuit configured to be electrically coupled to a load, comprising:

A first power supply;

a second power supply; and

A transistor assembly, comprising:

A first Field Effect Transistor (FET) and a second FET configured to be electrically coupled in series between the first power source and the load, each of the first FET and the second FET being a respective N-channel FET,

A control circuit at least partially powered by the second power supply, the control circuit configured to control a respective operating state of each of the first and second FETs, and

A capacitor and a third FET collectively configured to shunt current away from a gate of the first FET during a pre-power operating state of the transistor assembly characterized at least in part by (a) the first power supply being active and (b) the second power supply being passive.

17. The circuit of claim 16, wherein the load comprises a camera.

18. The circuit of claim 16, wherein:

the third FET includes a gate and a drain;

the capacitor is electrically coupled between the first power supply and the gate of the third FET; and

The drain of the third FET is electrically coupled to the gate of the first FET.

19. The circuit of claim 18, wherein a source of the third FET is electrically coupled to one of (a) a power supply of the first FET and (b) a reference node.

20. The circuit of claim 18, further comprising a switching device configured to discharge a gate-to-source capacitance of the third FET in response to a signal asserted after the second power supply is active.