CN118366499A - Ferroelectric memory, refresh method thereof, memory device and electronic device - Google Patents

Abstract

The embodiment of the application provides a ferroelectric memory, a refreshing method thereof, memory equipment and electronic equipment, which relate to the technical field of memory and are used for improving the problem of low refreshing efficiency of the ferroelectric memory. The ferroelectric memory includes: the main memory array comprises a plurality of word lines and a plurality of memory cells, and the memory cells distributed along the first direction are connected with the same word line; the memory cell comprises an access transistor and a plurality of ferroelectric capacitors, wherein the access transistor is connected with first polar plates of the plurality of ferroelectric capacitors, the word line is configured to control the conduction state of the access transistor, when the access transistor is conducted, data can be written into the ferroelectric capacitors or data stored in the ferroelectric capacitors can be read, the counting circuit is connected with a plurality of word lines of the main memory array, and the counting circuit is configured to count the access times of the plurality of word lines; the main memory array is configured to refresh memory cells to which the plurality of word lines are connected when the number of accesses of the plurality of word lines reaches a preset number.

Description

Ferroelectric memory, refresh method thereof, memory device and electronic device

Technical Field

The present application relates to the field of memory technologies, and in particular, to a ferroelectric memory, a refresh method thereof, a memory device, and an electronic device.

Background

A ferroelectric random access memory (ferroelectric random access memory, feRAM), which may also be referred to as a "ferroelectric memory", which performs data storage by utilizing the characteristic that a ferroelectric material can undergo spontaneous polarization and the polarization intensity can be reoriented with the action of an external electric field; when the electric field is removed, part of the polarization state can be maintained, the polarization intensity is called remnant polarization, and the electric field in the same direction is applied by utilizing the difference of the remnant polarization direction, and the flip charges are different, so that the data "0" and "1" can be stored.

The memory cell of the ferroelectric memory with the 1TnC structure comprises an access transistor (transistor, abbreviated as T) and a plurality of ferroelectric capacitors (capacitor, abbreviated as C), wherein the gate of the access transistor is connected with a word line, the first end of the access transistor is connected with a bit line, the first polar plates of the ferroelectric capacitors are connected with the second end of the access transistor, each ferroelectric capacitor can be used for storing 1 bit of data, but when any one ferroelectric capacitor is accessed, the first polar plates of the ferroelectric capacitors are connected with the second end of the access transistor, the first polar plates of the ferroelectric capacitors can cause interference to other unselected ferroelectric capacitors, and the data stored by the ferroelectric capacitors is invalid due to excessive interference, so that the data stored by the ferroelectric capacitors need to be refreshed, for example, the whole memory bank is refreshed after the access times of the whole memory bank reach the preset times, but the efficiency of the refresh mode is lower.

Disclosure of Invention

The embodiment of the application provides a ferroelectric memory, a refreshing method thereof, a memory device and an electronic device, which are used for solving the problem of low refreshing efficiency of the ferroelectric memory.

In a first aspect, there is provided a ferroelectric memory comprising: the memory comprises a main memory array and a counting circuit, wherein the main memory array comprises a plurality of word lines and a plurality of memory cells, the word lines extend along a first direction, and the memory cells distributed along the first direction are connected with the same word line; the memory cell comprises an access transistor and a plurality of ferroelectric capacitors, wherein the access transistor is connected with first polar plates of the plurality of ferroelectric capacitors, the word line is configured to control the conduction state of the access transistor in the memory cell, when the access transistor is conducted, data can be written into the ferroelectric capacitors or data stored in the ferroelectric capacitors can be read, the counting circuit is connected with a plurality of word lines of the main memory array, and the counting circuit is configured to count the access times of the plurality of word lines; the main memory array is configured to refresh memory cells to which the plurality of word lines are connected when a result of counting the number of accesses to the plurality of word lines reaches a preset number.

According to the scheme provided by the embodiment of the application, the total access times of the plurality of word lines in the main memory array are counted by the counting circuit, when the total access of the plurality of word lines reaches the preset times, the memory cells connected with the plurality of word lines are refreshed instead of refreshing the whole memory bank, when the total access times of the memory bank reach the preset times, the refresh of the whole memory bank possibly causes that the access times of the memory cells on part of the word lines are less or even not accessed, so that the refresh times are increased, and the refresh efficiency is reduced.

In one possible implementation, the counting circuit includes a mapping circuit and a mirrored memory array, the mirrored memory array including: the memory cell of the mirror image memory array comprises an access transistor and a plurality of ferroelectric capacitors, wherein the gate electrode of the access transistor is connected with the word line, the first end of the access transistor is connected with the bit line of the mirror image memory array, the second end of the access transistor is connected with a first polar plate of the plurality of ferroelectric capacitors, a second polar plate of the first ferroelectric capacitor of the plurality of ferroelectric capacitors is connected with a first plate line of the mirror image memory array, and a second polar plate of the second ferroelectric capacitor of the plurality of ferroelectric capacitors is connected with a second plate line of the mirror image memory array; the ferroelectric capacitor in the mirror memory array is configured to store a first logic value, the word line of the mirror memory array is configured to be in a first level state, so that the access transistor in the mirror memory array is configured to be in an on state; a plurality of word lines of the main memory array are correspondingly connected with one bit line in the mirror image memory array through a mapping circuit.

According to the counting circuit provided by the embodiment of the application, the mirror image storage array is utilized for fuzzy counting, the access times of a plurality of word lines on the main storage array can be mapped to the storage units on one bit line in the mirror image storage array, the word lines of the mirror image storage array are configured to be in a first level state so as to fully configure the access transistors in the mirror image storage array to be in a conducting state, thus each time the plurality of word lines on the main storage array are accessed, the ferroelectric capacitors on the bit lines in the corresponding mirror image storage array are interfered, the fuzzy technology is performed by utilizing the characteristics of ferroelectric materials, and when the ferroelectric capacitors of the mirror image storage array bear the interference times to reach the performance indexes of the ferroelectric materials, the stored data can be overturned, and the method can be used for indicating that the access times of the plurality of word lines of the main storage array reach the preset times.

In one possible implementation, the primary storage array further includes: bit lines and plate lines; the gate of the access transistor of the main memory array is connected with the word line of the main memory array, the first end of the access transistor is connected with the bit line of the main memory array, and the second end of the access transistor is connected with the first polar plates of the ferroelectric capacitors; the second polar plate of the first ferroelectric capacitor in the plurality of ferroelectric capacitors is connected with the first plate line in the plate line of the main memory array, and the second polar plate of the second ferroelectric capacitor in the plurality of ferroelectric capacitors is connected with the second plate line in the plate line of the main memory array.

In one possible implementation, the main memory array includes a plurality of sets of word lines, each set of word lines including a plurality of word lines, the plurality of sets of word lines of the main memory array being in one-to-one correspondence with bit lines of the mirror memory array.

In one possible implementation, the mapping circuit includes a multiplexer through which a set of word lines of the main memory array are coupled to bit lines in a mirror memory array such that any one of the set of word lines of the main memory array is mapped to a bit line of the mirror memory array to count the number of accesses to the set of word lines of the main memory array.

In one possible implementation, when a first logic value stored by a ferroelectric capacitor connected to a bit line in the mirror memory array is converted to a second logic value with an opposite state, it is determined that the number of accesses to a plurality of word lines in a main memory array connected to the bit line in the mirror memory array reaches a preset number.

In a second aspect, an embodiment of the present application further provides a method for refreshing a ferroelectric memory, where the ferroelectric memory includes: the memory comprises a main memory array and a counting circuit, wherein the main memory array comprises a plurality of word lines and a plurality of memory cells, the word lines extend along a first direction, and the memory cells distributed along the first direction are connected with the same word line; the memory cell includes an access transistor and a plurality of ferroelectric capacitors, the access transistor is connected with a first polar plate of the plurality of ferroelectric capacitors, the word line is configured to control a conduction state of the access transistor in the memory cell, and the counting circuit is connected with the plurality of word lines, the method includes: the counting circuit counts the access times of a plurality of word lines in the main memory array; and refreshing the memory cells connected with the plurality of word lines in the main memory array when the result of the access times counting of the plurality of word lines in the main memory array reaches the preset times.

In one possible implementation, the counting circuit includes a mapping circuit and a mirrored memory array, the mirrored memory array including: the memory cell of the mirror memory array comprises an access transistor and a plurality of ferroelectric capacitors, wherein the gate of the access transistor is connected with the word line, the first end of the access transistor is connected with the bit line of the mirror memory array, the second end of the access transistor is connected with a first polar plate of the plurality of ferroelectric capacitors, a second polar plate of the first ferroelectric capacitors is connected with a first polar plate of the plate line of the mirror memory array, a second polar plate of the second ferroelectric capacitors is connected with a second polar plate of the plate line of the mirror memory array, the ferroelectric capacitors in the mirror memory array are configured to store a first logic value, the word line of the mirror memory array is configured to be in a first level state, so that the access transistor in the mirror memory array is configured to be in a conducting state, and the plurality of word lines of the main memory array are correspondingly connected with one bit line in the mirror memory array through a mapping circuit, and the method further comprises: when the ferroelectric capacitor connected with the bit line in the mirror image storage array stores the first logic value which is stored in advance and is turned to the second logic value with opposite states, the access times of a plurality of word lines in the main storage array corresponding to the bit line in the mirror image storage array are determined to reach the preset times.

In one possible implementation manner, when the result of the count of the number of accesses to the plurality of word lines in the main memory array reaches a preset number, after refreshing the memory cells connected to the plurality of word lines in the main memory array, the method further includes: all memory cells connected by bit lines in the mirror image memory array are refreshed, and because the interference born by all memory cells connected by one bit line in the mirror image memory array is consistent, when the result of counting the access times of a plurality of word lines in the main memory array reaches the preset times, all ferroelectric capacitor stored data on the one bit line in the mirror image memory array are overturned, so that all memory cells connected by the one bit line in the mirror image memory array are refreshed while the memory cells on the plurality of word lines in the main memory array are refreshed, and the access times of the plurality of word lines in the refreshed main memory array can be counted again.

In a third aspect, embodiments of the present application further provide a memory device, including a controller and a ferroelectric memory as provided in any one of the implementations of the first aspect, where the controller is coupled to the ferroelectric memory for controlling reading and writing of data from the ferroelectric memory.

In a fourth aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes a processor and a ferroelectric memory connected to the processor, where the ferroelectric memory is a ferroelectric memory provided in any implementation manner of the first aspect.

Drawings

Fig. 1 is a schematic diagram of a system architecture of an electronic device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a ferroelectric hysteresis loop of a ferroelectric material according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a memory according to an embodiment of the present application;

FIG. 5 is another schematic diagram of a memory according to an embodiment of the present application;

fig. 6 is a schematic circuit diagram of a ferroelectric memory according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a ferroelectric memory according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 9 is a schematic diagram of another ferroelectric memory according to an embodiment of the present application;

FIG. 10 is a schematic circuit diagram of another ferroelectric memory according to an embodiment of the present application;

FIG. 11 is a timing chart of refresh signals of a ferroelectric memory according to an embodiment of the present application;

Fig. 12 is a flowchart of a method for refreshing a ferroelectric memory according to an embodiment of the present application;

fig. 13 is a flowchart of another method for refreshing a ferroelectric memory according to an embodiment of the present application.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "first," "second," and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. For example, a plurality of processing units refers to two or more processing units.

Furthermore, in the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to the orientation in which the components in the drawings are schematically disposed, and it should be understood that these directional terms may be relative concepts, which are used for descriptive and clarity with respect thereto, and which may be correspondingly varied according to the variation in orientation in which the components in the drawings are disposed. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the dimensional relationships between the parts in the drawings do not reflect actual dimensional relationships.

In embodiments of the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "electrically connected" may be a direct electrical connection or an indirect electrical connection via an intermediary.

In the embodiment of the present application, the term "module" is generally a functional structure divided according to logic, and the "module" may be implemented by pure hardware or a combination of hardware and software. In the embodiment of the present application, "and/or" describes the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may represent: a alone, B alone, and both A and B.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the embodiment of the present application, a metal-oxide-semiconductor field effect transistor (MOSFET) may be used as the transistor, and the transistor is classified into two types of an N (negative) transistor and a P (positive) transistor. The transistor includes a source (source), a drain (drain), and a gate (gate), and can be turned on or off by controlling the level of the gate of the input transistor. When the transistor is turned on, the source electrode and the drain electrode are turned on to generate an on current, and when the grid electrode level of the transistor is different, the magnitude of the on current generated between the source electrode and the drain electrode is also different; when the transistor is turned off, the source electrode and the drain electrode are not turned on, and no current is generated. In an embodiment of the present application, the gate of the transistor is also referred to as a control terminal, the source is referred to as a first terminal, and the drain is referred to as a second terminal; or the gate is called the control terminal, the drain is called the first terminal, and the source is called the second terminal. In addition, the N-type transistor is conducted when the level of the control end is high, the first end and the second end are conducted, and conduction current is generated between the first end and the second end; the N-type transistor is turned off when the level of the control end is low, the first end and the second end are not turned on, and no current is generated. The P-type transistor is conducted when the level of the control end is low, and the first end and the second end are conducted to generate conducting current; the P-type transistor is turned off when the level of the control terminal is high, the first terminal and the second terminal are not turned on, and no current is generated.

The embodiment of the application provides electronic equipment. The electronic device may include electronic products such as a mobile phone (mobile phone), a tablet (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, and the like. The embodiment of the application does not limit the specific form of the electronic device.

Fig. 1 is a schematic architecture diagram of an electronic device according to an exemplary embodiment of the present application. As shown in fig. 1, the electronic device 100 includes: memory 110, processor 120, input device 130, output device 140, and the like. Those skilled in the art will appreciate that the configuration of the electronic device shown in fig. 1 does not constitute a limitation of the electronic device 100, and the electronic device 100 may include more or fewer components than those shown in fig. 1, or may combine some of the components shown in fig. 1, or may be arranged differently than the components shown in fig. 1.

The memory 110 is used to store software programs and modules. The memory 110 mainly includes a storage program area and a storage data area, wherein the storage program area can store an operating system, application programs (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data created according to the use of the electronic device (such as audio data, image data, phonebook, etc.), and the like.

The processor 120 is a control center of the electronic device 100, connects various parts of the entire electronic device 100 using various interfaces and lines, and performs various functions of the electronic device 100 and processes data by running or executing software programs and/or modules stored in the memory 110 and calling data stored in the memory 110, thereby performing overall monitoring of the electronic device 100. Optionally, the processor 120 may include one or more processing units. For example, the processor 120 may include a central processing unit (central processing unit, CPU), an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor, a digital signal processor (DIGITAL SIGNAL processor), a neural network processor, other application-specific integrated circuits (ASICs), and the like. In fig. 1, the processor 120 is taken as an example of a CPU, and the CPU may include an operator 121 and a controller 122. The arithmetic unit 121 acquires data stored in the internal memory 112, processes the data stored in the internal memory 112, and normally returns the processed result to the internal memory 112. The controller 122 may control the operator 121 to process the data, and the controller 122 may also control the external memory 111 and the internal memory 112 to store the data or read the data.

The input device 130 is used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the electronic device 100. By way of example, the input device 130 may include a touch screen, as well as other input devices. Touch screens, also known as touch panels, collect touch operations by a user on or near the touch screen (e.g., operations by a user on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection device according to a predetermined program. Alternatively, the touch screen may comprise two parts, a touch detection device and a touch controller. The touch detection device detects the touch azimuth of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, and sends the touch point coordinates to the processor 120, and can receive and execute commands sent from the processor 120. In addition, the touch screen may be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, power switch keys, etc.), a trackball, mouse, joystick, etc. The controller 122 in the processor 120 may also control the input device 130 to receive an input signal or not. In addition, entered numeric or character information received by the input device 130, as well as key signal inputs generated in connection with user settings and function controls of the electronic device, may be stored in the internal memory 112.

The output device 140 is used for outputting signals corresponding to the data input by the input device 130 and stored in the internal memory 112. For example, the output device 140 outputs a sound signal or a video signal. The controller 122 in the processor 120 may also control the output device 140 to output a signal or not.

The thick arrow in fig. 1 is used to indicate the transmission of data, and the direction of the thick arrow indicates the direction of data transmission. For example, a single arrow between the input device 130 and the internal memory 112 indicates that data received by the input device 130 is transferred to the internal memory 112. For another example, double-headed arrows between the operator 121 and the internal memory 112 indicate that data stored in the internal memory 112 may be transferred to the operator 121, and data processed by the operator 121 may be transferred to the internal memory 112. Thin arrows in fig. 1 represent components that can be controlled by the controller 122. By way of example, the controller 122 may control the external memory 111, the internal memory 112, the operator 121, the input device 130, the output device 140, and the like.

Optionally, the electronic device 100 as shown in fig. 1 may also include various sensors. Such as gyroscopic sensors, hygrometric sensors, infrared sensors, magnetometer sensors, etc., are not described in detail herein. Optionally, the electronic device may further include a wireless fidelity (WIRELESS FIDELITY, wiFi) module, a bluetooth module, etc., which will not be described in detail herein.

It will be appreciated that in embodiments of the present application, an electronic device (e.g., the electronic device shown in fig. 1 described above) may perform some or all of the steps in embodiments of the present application, which are merely examples, and embodiments of the present application may also perform other operations or variations of the various operations. Furthermore, the various steps may be performed in a different order presented in accordance with embodiments of the application, and it is possible that not all of the operations in the embodiments of the application may be performed. The embodiments of the present application may be implemented alone or in any combination, and the present application is not limited thereto.

In the electronic device shown in fig. 1, the memory 110 includes an external memory 111 and an internal memory 112. The data stored in the external memory 111 and the internal memory 112 can be transferred to each other. The external memory 111 includes, for example, a hard disk, a usb disk, a floppy disk, and the like. The internal memory 112 is, for example, a random access memory, a read only memory, or the like, wherein the random access memory may include a ferroelectric random access memory, abbreviated as a ferroelectric memory.

Ferroelectric memories store data by taking advantage of the characteristic that ferroelectric materials can undergo spontaneous polarization and the polarization state can be reoriented with the action of an external electric field. As shown in fig. 2, fig. 2 shows a schematic diagram of a hysteresis loop of a ferroelectric material. When an electric field is applied to a ferroelectric crystal, the central atom stays at a low energy state position I along the electric field, whereas when an electric field flip is applied to the same ferroelectric crystal, the central atom moves in the crystal along the direction of the electric field and stays at another low energy state position II. A large number of central atoms are mobile-coupled in a crystal unit cell to form ferroelectric domains that form polarized charges (also called flipped charges) under the action of an electric field. In order to ensure that the applied electric field is capable of reversing the polarization state of the ferroelectric material, the electric field strength should be greater than the coercive field strength Ec of the ferroelectric material, which refers to the reverse electric field strength required for the remanent polarization of the ferroelectric material to return to zero. For example, from position I in FIG. 2 to position II in FIG. 2, an electric field greater than-Ec needs to be applied to the ferroelectric material, and from position II in FIG. 2 to position I in FIG. 2, an electric field greater than +ec needs to be applied to the ferroelectric material.

The ferroelectric domain has higher inversion charge (shown as Q1 in fig. 2) when it is inverted under an electric field, and the ferroelectric domain has lower inversion charge (shown as Q0 in fig. 2) when it is not inverted under an electric field, and this binary stable state of the ferroelectric material enables the ferroelectric material to be used as a memory, and the two binary states of data 0 and 1 can be stored by applying the electric field in the same direction with the difference of the remnant polarization intensity directions. When an electric field is applied to the ferroelectric material crystal, the central atoms move in the crystal along the direction of the electric field, and when the atoms move, the atoms pass through an energy barrier, so that charge breakdown is caused, after the electric field is removed, the central atoms can keep unchanged positions, and the polarization state can be kept, so that the ferroelectric material has the characteristic of non-volatility when used as a memory.

Illustratively, as shown in FIG. 2, assuming one polarization state (as represented by position I in FIG. 2) is a "0" state, the other polarization state (as represented by position II in FIG. 2) is a "1" state. Taking a ferroelectric material capacitor (hereinafter referred to simply as a ferroelectric capacitor) as an example, the ferroelectric capacitor refers to a capacitor using a ferroelectric material as a medium, so that the ferroelectric capacitor may have different polarization states, for example, a "0" state or a "1" state, an electric field applied to the ferroelectric capacitor in the "0" state may generate a charge Q0, an electric field applied to the ferroelectric capacitor in the "1" state may generate a charge Q1, the charge Q0 or the charge Q1 may be accumulated and converted into a read voltage, and data stored in the ferroelectric capacitor may be identified according to the difference of the read voltage.

The smallest cell in the ferroelectric memory for storing data is called a Memory Cell (MC), and the Memory Cell (MC) of the ferroelectric memory includes a 2T2C, 1T1C, and the like. A memory cell refers to the smallest structure of a memory used to access information or data, and is called "2T2C" if it contains two transistors (transistors) and two capacitors (capacitors); if one transistor (transmitter) and two capacitors (capacitor) are included, then the transistor is called as '1T 2C'; if a transistor (transmitter) and a capacitor (capacitor) are included, it is called "1T1C". The fewer devices of the memory cell, the simpler the structure, the smaller the occupied area, and the higher the memory density per unit area.

Fig. 3 shows a schematic diagram of a ferroelectric memory of a 1T1C memory structure, each memory cell MC includes an access transistor and a ferroelectric capacitor, the memory cell MC shown in fig. 3 includes an access transistor T and a ferroelectric capacitor C, a control terminal of the access transistor T is connected to a word line WL1, a first terminal of the access transistor T is connected to a bit line BL1, a second terminal of the access transistor T is connected to a first plate of the ferroelectric capacitor C, a second plate of the ferroelectric capacitor C is connected to a plate line PL1, and data can be written into a selected memory cell or data stored therein can be read through the word line, the bit line and the plate line. Illustratively, the word line WL1 is used to enable the access transistor T of the memory cell MC, control the access transistor T to be turned on, and the bit line BL1 and the plate line PL1 are used to charge the ferroelectric capacitor C of the memory cell MC, so that the ferroelectric capacitor C is in different polarization states (polarization states as shown in fig. 2), and thus the data "0" and "1" can be represented by using the different polarization states of the ferroelectric capacitor C.

Typically, the memory cells in the memory 110 are arranged and distributed in a matrix, which is referred to as a memory array (array), and referring to fig. 4, the memory 110 may include a command decoder 115, a control logic 116, a memory array 113, and an input/output circuit 114, which are not limited thereto and may include a smaller or larger number of constituent elements in a specific embodiment. The command decoder 115 may receive a command CMD (CMD) from the memory controller and may decode the received command CMD. Such as write commands (WRs), read commands (RDs), etc., the memory controller can be positioned to any one of the memory cells in the bank, i.e., to any bit of data, by corresponding address line (word line, bit line, and plate line) decoders.

Since the memory and the processor are usually located on different chips (die), the memory units need to be packaged and combined before being connected with the processor, and the memory units from the processor to the ferroelectric memory are from large to small according to the level: channel, rank, bank, array, row, or column.

As shown in fig. 5, a schematic diagram of a memory 110 is shown, where a channel (channel) is an independently accessible storage space that may include one or more storage columns (ranks). Typically, a channel includes a volume of memory space, and hardware circuitry for accessing the memory space, which may include control logic and associated circuitry such as interfaces. The channel may consist of a rank (rank) that refers to a memory granule (chip) connected to the same chip select (CHIP SELECT) signal, also called chip; since these chips are connected to the same chip select signal, the memory controller can write to the chips in the same memory column, and the chips in the same memory column share the same control signal. Each storage column may include one or more storage libraries (banks), for example, a storage column may include 4 banks, or may also include 8 banks. The bank of the random access memory includes one or more memory arrays (array), each of which includes a plurality of memory cells (memory cells) distributed in rows (columns), and the memory arrays can read and write data through input/output ports (IOs).

The read-write principle of the ferroelectric memory will be described below based on the memory cell MC shown in fig. 3. The word line WL1 is used to enable the access transistor T of the memory cell MC, control the access transistor T to be turned on, and the bit line BL1 and the plate line PL1 are used to charge the ferroelectric capacitor C of the memory cell MC, so that the ferroelectric capacitor C is in different polarization states (polarization states as shown in fig. 2), and thus the data "0" and "1" can be represented by using the different polarization states of the ferroelectric capacitor C.

When the data stored in the memory cell MC is read, the access transistor T of the memory cell MC is turned on by the word line WL1, then an excitation voltage VW (which is greater than the coercive field strength Ec of the ferroelectric material and is sufficient to invert the polarization state of the ferroelectric capacitor) is applied to the ferroelectric capacitor C in the memory cell MC by the plate line PL1, the ferroelectric capacitor C generates an inversion charge under the effect of the excitation voltage VW, the read data is determined according to the amount of the inversion charge, the inversion charge is accumulated on the bit line BL1 to form a read voltage, when the bit line BL1 is at a low level, the inversion charge is small, and when the bit line BL1 is at a high level, the inversion charge is large. For example, it may be used to indicate that the data stored in the memory cell MC is "1" when more inversion charges are generated, and to indicate that the stored data is "0" when the inversion charges are less. In another case, the data stored may be indicated as "0" when the flipped charge is greater, and "1" when the flipped charge is less. When a read operation is performed, the voltage of the word line WL1 is raised to turn on the access transistor T of the memory cell MC, then the excitation voltage VW is output to the plate line PL1, after the excitation voltage VW is applied to the second plate of the ferroelectric capacitor C, the generated flipped charge is distributed to the parasitic capacitance of the bit line BL1 to form a read voltage on the bit line BL1, and if the data stored in the ferroelectric capacitor C is "1", as shown in fig. 2, the flipped charge "Q1" forms a read voltage on the bit line BL1 during the read; if the ferroelectric capacitor C stores data of "0", the charge "Q0" is inverted to form a read voltage on the bit line BL1 during reading.

Since the excitation voltage VW is applied to the second plate of the ferroelectric capacitor C during the reading process, if the voltage of the second plate of the ferroelectric capacitor C is different from the excitation voltage, the difference refers to that the excitation voltage VW is different from the voltage state of the second plate, for example, the excitation voltage is at a high level, and the second plate of the ferroelectric capacitor C is at a low level, as in the foregoing embodiment, for example, the data stored in the memory cell MC is at a first logic value, the first plate of the ferroelectric capacitor C is at a first voltage (high level), and the second plate of the ferroelectric capacitor C is at a second voltage (low level), in this case, the application of the excitation voltage VW to the second plate of the ferroelectric capacitor C rewrites the voltage of the second plate to a high level, resulting in that the data stored in the memory cell is rewritten from the first logic value to the second logic value.

High density, high performance, and low power consumption have been the goal of memory development. In recent years, with the demands of emerging application scenarios such as artificial intelligence, edge computing and the like, certain challenges are presented to the capacity, power consumption and speed of conventional memories, and the development of novel memories is promoted continuously. The ferroelectric memory is used as a novel memory and has the advantages of non-volatility, high read-write speed, low power consumption and the like. The memory density of the ferroelectric memory with the 1T1C structure still needs to be improved, and therefore, the embodiment of the application provides the ferroelectric memory with the 1TnC structure.

Referring to fig. 6 and 7, fig. 6 shows a schematic circuit diagram of a ferroelectric memory according to an embodiment of the present application, and fig. 7 shows a schematic structure diagram of a ferroelectric memory according to an embodiment of the present application. The memory includes one or more memory arrays 20, only one of which is shown in fig. 6 and 7, and the memory array 20 includes a plurality of bit lines 21 in a first direction, which may be an X direction of an XYZ coordinate system shown in fig. 7, and a plurality of word lines 22 in a second direction, which may be a Y direction of the drawing, and a plurality of plate lines 23 stacked in a third direction, which may be a Z direction of the drawing, where the first direction crosses the second direction, for example, the first direction is orthogonal to the second direction, and the third direction is orthogonal to the first direction and the second direction, for example.

The ferroelectric memory includes a plurality of memory cells, referring to fig. 8, which shows a schematic diagram of one of the memory cells, the memory cell includes an access transistor 24 and a plurality of ferroelectric capacitors 25, wherein the access transistor 24 is disposed at an intersection of the word line 22 and the bit line 21, a gate of the access transistor 24 is connected to the word line 22, a first end of the access transistor 24 is connected to the bit line 21, a second end of the access transistor 24 is connected to a first plate of the plurality of ferroelectric capacitors 25, a second plate of the ferroelectric capacitors 25 is connected to the plate line 23, an exemplary first plate of the first ferroelectric capacitors is connected to the first plate line, a second plate of the second ferroelectric capacitors is connected to the second plate line, a second plate of the third ferroelectric capacitors is connected to the third plate line … …, e.g., as shown in fig. 8, a first plate of the ferroelectric capacitors 251 is connected to the second end of the access transistor 22, a second plate connection plate line 231 of the ferroelectric capacitors 251, a second plate connection plate 232 of the ferroelectric capacitors 252, a second plate connection plate 233 of the ferroelectric capacitors 25n, and a second plate connection plate 23n of the ferroelectric capacitors.

For example, where a plurality of plate lines 23 may be stacked along a third direction, and a plurality of ferroelectric capacitors 25 may be stacked along the third direction of the access transistors 24 to which they are connected to form a three-dimensional memory array, for example, fig. 7 may continue to refer to fig. 7, where fig. 7 illustrates a schematic structure of a ferroelectric memory provided by an embodiment of the present application, by stacking the plate lines 23, the ferroelectric capacitors 25, etc. along the third direction, where a first ferroelectric capacitor is located on the same layer as the first plate line, a second ferroelectric capacitor is located on the same layer … … as the second plate line, and by stacking the ferroelectric capacitors, the memory density of the memory is increased, for example, in connection with fig. 7, the ferroelectric capacitors 251, 252, 253, 254, 255 are stacked along the third direction of the access transistors 24, where the ferroelectric capacitors 251 are located on the same layer as the plate lines 232, the ferroelectric capacitors 255 are located on the same layer … …, and each access transistor 24 in the memory array illustrated in fig. 7 is connected to 5 ferroelectric capacitors 25, and in addition, the number of ferroelectric capacitors 25 may be further or less in each embodiment, connected to the access transistors 24.

Illustratively, the ferroelectric capacitors 25 provided by embodiments of the present application may be used as storage data, each ferroelectric capacitor 25 may store 1 bit data, such as "0" or "1", and the access transistor 24 is used as an access device for controlling reading and writing of the ferroelectric capacitor 25. When the access transistor 24 is controlled to be turned on by the word line 22, a first plate of the ferroelectric capacitor 25 is turned on with the bit line 21, and a second plate of the ferroelectric capacitor 25 is connected with the plate line 23, so that data can be written to the ferroelectric capacitor 25 by controlling voltages applied to the bit line 21 and the plate line 23, or data stored in the ferroelectric capacitor 25 can be read by sensing a read voltage on the bit line 21.

For example, in connection with fig. 7, the plate line may be a conductive metal plate, instead of a single metal line, the plate line may be provided with a plurality of through holes, each of which is aligned with a position of one of the access transistors, the ferroelectric capacitor may be formed at the through hole, the plurality of plate lines may be stacked in the third direction, and adjacent two plate lines may be separated by an insulating material. The second terminal of the access transistor may be connected to a conductive post 26 (pilar) through a via hole through the plurality of plate lines, with a first plate of the ferroelectric capacitor connected to the conductive post and a second plate of the ferroelectric capacitor connected to the plate line.

A plurality of ferroelectric capacitors connected to the same access transistor are aligned with the access transistor and stacked in a third direction of the access transistor, and illustratively, a conductive pillar is formed through a first plate line, a second plate line … …, an n-th plate line, a first ferroelectric capacitor is formed at a via of the first plate line through which the conductive pillar passes, a second ferroelectric capacitor is formed at a via of the second plate line through which the conductive pillar passes, and an n-th ferroelectric capacitor is formed at a via of the n-th plate line through which the conductive pillar passes. Thus, a specific access transistor can be selected by a bit line and a word line, and a specific ferroelectric capacitor can be selected by a selection plate line.

By way of example, each connecting ferroelectric capacitor may be marked with three coordinates of a specific word line number, a specific bit line number, and a specific plate line number. For example, in fig. 6, two ferroelectric capacitors are shown with tags (1, 4) corresponding to word line 221, bit line 211, and plate line 234; and tags (1, 4) corresponding to word line 221, bit line 214, and plate line 234.

The three-dimensional ferroelectric memory with each access transistor connected with a plurality of ferroelectric capacitors can have a storage density 5-10 times greater than that of the ferroelectric memory with the traditional 1T1C structure, because each access transistor of the traditional ferroelectric memory is usually connected with only one ferroelectric capacitor and can only store 1 bit of data, while each access transistor of the memory provided by the embodiment of the application can be connected with a plurality of ferroelectric capacitors and can store multidimensional data, and the plurality of ferroelectric capacitors can be stacked above the access transistor, so that the three-dimensional ferroelectric memory has higher storage density, lower cost and smaller area per bit.

The read-write principle of the ferroelectric memory with the 1TnC structure is basically the same as that of the ferroelectric memory with the 1T1C structure, wherein a word line is used for enabling an access transistor of a memory cell, controlling the access transistor to be conducted, and a bit line and a plate line are used for charging ferroelectric capacitors in the memory cell, so that the ferroelectric capacitors are in different polarization states (such as the polarization states shown in fig. 2), and the difference of the polarization states of the ferroelectric capacitors can be used for representing data 0 and 1.

When the data stored in the ferroelectric capacitor is read, the access transistor of the memory cell is enabled by the word line, the access transistor is controlled to be conducted, so that the first polar plate of the ferroelectric capacitor is communicated with the bit line, then an excitation voltage VW (the excitation voltage VW is larger than the coercive field strength Ec of the ferroelectric material and is enough to enable the polarization state of the ferroelectric capacitor to be overturned) is applied to the selected ferroelectric capacitor through the polar plate line, the ferroelectric capacitor 25 generates overturned charges under the action of the excitation voltage VW, the read data is determined according to the quantity of the overturned charges, the overturned charges are accumulated on the bit line to form a read voltage, when the bit line is at a low level, less overturned charges are represented, the data can be used for indicating that the read data is 0, and when the bit line is at a high level, more overturned charges are represented, the read data can be used for indicating that the read data is 1. In another case, the data used for indicating reading is "0" when the flipped charge is large, and "1" when the flipped charge is small.

However, in the ferroelectric memory with the 1TnC structure, when the second terminal of the access transistor is connected to the first plates of the plurality of ferroelectric capacitors, when the access transistor is turned on and the flipped charge of any one ferroelectric capacitor accumulates on the bit line to form a read voltage, the second terminal of the access transistor is connected to the first plates of the plurality of ferroelectric capacitors, which may cause the other ferroelectric capacitors connected to the access transistor to be disturbed (disturb) by the read voltage on the bit line, and the ferroelectric capacitors are limited by the material performance, so that the number of times of the disturbance that can be tolerated is limited, each time of the disturbance can cause the polarization state of the ferroelectric capacitors to change slightly, and when the number of times of the disturbance is excessive, the polarization state of the ferroelectric capacitors may be flipped, resulting in the failure of stored data, such as flipping from the storage "0" to the storage "1" or flipping from the storage "1" to the storage 0 ". The number of disturbances that can be tolerated is generally referred to herein as the performance index of the ferroelectric material, for example 10000 times, which means that the ferroelectric capacitor will fail after 10000 times of disturbances, and in order to avoid such a situation, the ferroelectric memory needs to refresh the memory cell, or the data stored in the ferroelectric capacitor.

Refreshing refers to reading the data stored by the ferroelectric capacitor and then rewriting it to ensure that the data stored by the ferroelectric capacitor is valid. One possible way of refreshing is when the number of accesses (reads) to the entire memory bank (bank) of the ferroelectric memory reaches the performance index of the ferroelectric material (e.g. 10000 times as mentioned in the previous example), the entire memory bank is refreshed.

Typically, a memory bank includes one or more memory arrays, where the memory array includes a plurality of word lines, and when refreshing in units of memory banks, the number of accesses experienced by most ferroelectric capacitors does not reach an indicator, for example, if 1 memory bank includes 2 ¹⁰ word lines, 10000 accesses may be distributed over 2 ¹⁰ word lines, memory cells on some word lines have more accesses, and memory cells on some word lines have fewer accesses, for example, some memory cells have only hundreds of accesses, and refreshing is performed, so it can be seen that performing a refresh at the memory bank level results in a higher number of refreshes and lower refresh efficiency.

In order to reduce the number of refreshing times and improve the refreshing efficiency, the embodiment of the application provides a new refreshing scheme, the refreshing is not performed by taking a memory bank as a unit, word lines in the memory bank are divided into a plurality of groups, the total access times of each group of word lines are counted, and after the counted result reaches the performance index of ferroelectric materials, the memory cells connected with the group of word lines are refreshed.

Referring to fig. 9, fig. 9 shows a schematic diagram of a ferroelectric memory according to an embodiment of the present application, including a main memory array 20 and a counting circuit 50, where the main memory array 20 includes a plurality of word lines 22, the counting circuit 50 is connected to the plurality of word lines 22 and is configured to count the number of accesses to the plurality of word lines 22, and when the result of the number of accesses to the plurality of word lines 22 reaches a preset number, the memory cells connected to the plurality of word lines 22 are refreshed.

Referring to fig. 6 or 7 in combination, the main memory array 20 includes a plurality of word lines 22 extending along a first direction, a plurality of bit lines 21 extending along a second direction, and a plurality of plate lines 23 stacked along a third direction, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to the first direction and the second direction.

The main memory array 20 includes a plurality of memory cells, the memory cells include an access transistor 24 and a plurality of ferroelectric capacitors 25, wherein the access transistor 24 is disposed at an intersection of the word line 22 and the bit line 21, a gate of the access transistor 24 is connected to the word line 22, a first end of the access transistor 24 is connected to the bit line 21, a second end of the access transistor 24 is connected to a first plate of the plurality of ferroelectric capacitors 25, second plates of the plurality of ferroelectric capacitors 25 are respectively connected to one plate line 23, for example, a second plate of a first ferroelectric capacitor is connected to the first plate line, a second plate of a second ferroelectric capacitor is connected to the second plate line, and a second plate of a third ferroelectric capacitor is connected to the third plate line.

The counting circuit 50 includes a mirror memory array 30 and a plurality of multiplexers 40. The mirror memory array 30 is the same structure as the main memory array 20 but of smaller scale. The mirror memory array 30 also includes a plurality of word lines 32 extending along a first direction, a plurality of bit lines 31 extending along a second direction, and a plurality of plate lines 33 stacked along a third direction, the mirror memory array 30 includes a plurality of memory cells including an access transistor 34 and a plurality of ferroelectric capacitors 35, wherein the access transistor 34 is disposed at an intersection of the word line 32 and the bit line 31, a gate of the access transistor 34 is connected to the word line 32, a first end of the access transistor 34 is connected to the bit line 31, a second end of the access transistor 34 is connected to a first plate of the plurality of ferroelectric capacitors 35, a second plate of the plurality of ferroelectric capacitors 35 is respectively connected to one plate line 33, for example, a second plate of the first ferroelectric capacitor is connected to the first plate line, a second plate of the second ferroelectric capacitor is connected to the second plate line, a second plate of the third ferroelectric capacitor is connected to the third plate line, and so on.

It should be noted that the main memory array 20 and the mirror memory array 30 are two independent memory arrays, and their structures may be referred to as the memory structures shown in fig. 6 and 7, where the main memory array 20 is configured to store data, and thus referred to as a main memory array, and the mirror memory array 30 is configured to count the number of accesses to the plurality of word lines 22 in the main memory array 20, and thus referred to as a mirror memory array, and the word lines, bit lines, and plate lines of both the main memory array 20 and the mirror memory array 30 are independent of each other, and the number of accesses to the plurality of word lines 22 in the main memory array 20 associated with the mirror memory array 30 is mapped to one bit line 31 in the mirror memory array 30 by the multiplexer 40 or other circuits having similar functions.

Illustratively, the word line 32 of the mirrored memory array 30 is configured in a first level state and the access transistor in the mirrored memory array 30 is configured in an on state when the word line in the mirrored memory array 30 is configured in the first level state such that the ferroelectric capacitors in the mirrored memory array 30 are all in communication with the bit line.

The word lines 22 in the main memory array 20 may be divided into a plurality of groups, each group including a plurality of word lines 2. The sets of word lines 22 are in one-to-one correspondence with bit lines 31 in the mirrored memory array 30. For example, a first set of word lines in the main memory array 20 corresponds to a first bit line in the mirror memory array 30, and a second set of word lines in the main memory array 20 corresponds to a second bit line … in the mirror memory array 30

The plurality of word lines 22 in the main memory array 20 are connected to the counting circuit 50, and the counting circuit 50 includes the mirror memory array 30 and the plurality of multiplexers 40, for example, the word lines 22 of the main memory array 20 may be divided into a plurality of groups, each group including the plurality of word lines 22, the first group of word lines being connected to a first bit line of the mirror memory array 30 through the first multiplexer, such that when any one of the first group of word lines of the main memory array 20 is accessed, a signal is applied to the first bit line of the mirror memory array 30, and because the access transistors of the mirror memory array 30 are configured to be in an on state, when a signal is applied to the first bit line of the mirror memory array 30, all ferroelectric capacitors equivalent to the first bit line connection of the mirror memory array 30 undergo a disturbance, based on the performance characteristics of the ferroelectric material, equivalent to mapping the number of accesses of a group of word lines in the main memory array 20 to one bit line of the mirror memory array 30, and using the ferroelectric capacitors connected to the one bit line performs a fuzzy operation, and the number of times of the ferroelectric capacitors connected to the group of the ferroelectric capacitors when the number of times of accesses of the word lines in the mirror memory array is subjected to the performance index of the ferroelectric memory array is reached when the number of times of the performance index of the flip of the memory array is reached.

Exemplary, referring to fig. 10, a refresh scheme of the ferroelectric memory according to an embodiment of the present application will be described in detail with reference to fig. 10. The main memory array 20 and a portion of the mirror memory array 30 are shown in fig. 10, with a plurality of word lines 22 in the main memory array 20 being grouped together and connected to one bit line 31 in the mirror memory array 30 through a multiplexer 40. For example, word line 221, word line 222, and word line 223 in main memory array 20 are grouped together and connected to bit line 311 in mirror memory array 30 via multiplexer 40. Since the word line 321 in the mirror memory array 30 is configured in the first level state, the access transistor 34 in the mirror memory array 30 is configured in the conductive state, for example, so that in the mirror memory array 30, the bit line is conductive to each ferroelectric capacitor, for example, the first plates of the ferroelectric capacitors 351-35 m in the mirror memory array 30 are conductive to the bit line 311.

When the word line 221, the word line 222, and the word line 223 in the main memory array 20 are connected to 331 in the mirror memory array 30 through the multiplexer 40, a signal is first applied to the word line (e.g., any one of the word line 221 to the word line 223) to set the access transistor in an on state, and when the signal is applied to the word line of the main memory array 20, for example, to any one of the word line 221, the word line 222, and the word line 223, the signal is applied to the bit line 311 of the mirror memory array 30 through the multiplexer 40, and the ferroelectric capacitors (e.g., the ferroelectric capacitors 351 to 35m shown in fig. 10) corresponding to all the memory cells connected to the bit line 311 in the mirror memory array 30 are subjected to the interference of one access. For example, when accessing data stored in a ferroelectric capacitor selected by the word line 221, the access is mapped to the bit line 311 of the mirror memory array 30, resulting in that all ferroelectric capacitors connected to the bit line 311 are subjected to a disturbance, when accessing data stored in a ferroelectric capacitor selected by the word line 222, the access is mapped to the bit line 311 of the mirror memory array 30, resulting in that all ferroelectric capacitors connected to the bit line 311 are subjected to a disturbance, that is, when accessing any one of a plurality of word lines in the main memory array 20 corresponding to the bit line 311 of the mirror memory array 30, the access is mapped to the bit line 311, resulting in that all ferroelectric capacitors connected to the bit line 311 are subjected to a disturbance, which is equivalent to counting the number of accesses to the plurality of word lines in the main memory array 20, but the count is not precisely counted, but is fuzzy, the count can only distinguish whether the total number of accesses to the plurality of word lines reaches the performance index of ferroelectric material, when the total number of accesses to the plurality of word lines reaches the performance index of ferroelectric material, that the total number of accesses to the ferroelectric material reaches the performance index of the first, i.e. the threshold value of "if the ferroelectric capacitor corresponding to the bit line 30 is reversed to the first logic memory array 30" the first threshold value of "35" is reached, "and if the number of accesses to the first bit line of the ferroelectric capacitor corresponding to the bit line 30 reaches the first threshold value of" 35 "the logic memory value of the first logic memory array is reached" if the value of the first threshold value of "is reached" 35 ",35", a refresh needs to be performed.

In the embodiment of the application, a fuzzy counter is constructed through the mirror image memory array 30 to count the access times of a plurality of word lines in the main memory array 20, wherein all ferroelectric capacitors in the mirror image memory array 30 are prestored with 0 (or with 1), after the access times of the main memory array 20 reach the set times, the data stored in the ferroelectric capacitors in the mirror image memory array 30 are read, if 0 (1 is prestored, then 1 is read), the total access times of the plurality of word lines in the main memory array 20 do not reach the performance index of the ferroelectric materials, no refreshing is needed, and if the data stored in the ferroelectric capacitors in the mirror image memory array 30 are overturned, and when 1 is prestored, then 0 is read, then the total access times of the plurality of word lines in the main memory array 20 reach the performance index of the ferroelectric materials, and the memory cells connected with the plurality of word lines in the main memory array 20 need to be refreshed.

In the case of refreshing memory cells connected to a plurality of word lines (for example, word lines 221 to 223) of the main memory array 20, it is necessary to refresh all memory cells on the bit lines 311 in the mirror memory array 30 corresponding to the word lines 221 to 223 of the main memory array 20, so that the number of times of access to the word lines 221 to 223 of the main memory array 20 after the refresh can be counted again.

In the mirror image memory array 30, the memory cells connected to the same bit line are consistent in the degree of interference of their ferroelectric capacitors, because an exciting voltage is applied when the data stored in the ferroelectric capacitors are read, the original polarization state of the ferroelectric capacitors is broken, and each ferroelectric capacitor can only be read once, when the data stored in the ferroelectric capacitors in the mirror image memory array 30 are read, the data stored in the first ferroelectric capacitor are read first, and when the data stored in the first ferroelectric capacitor are read, the data stored in the second ferroelectric capacitor are read next, so that the data stored in the ferroelectric capacitors are read by switching the plate lines first and then the word lines, and the data stored in the ferroelectric capacitors are switched bit by bit until the data stored in the ferroelectric capacitors are read, and the access times of a plurality of word lines in the main memory array 20 are confirmed to reach the performance index of the ferroelectric materials, so that the memory cells connected by the group of word lines in the main memory array 20 can be refreshed.

For example, in the mirror memory array 30, the data stored in the ferroelectric capacitors selected by the bit line 311, the word line 321, and the plate line 331 are read first, and in the next reading, the data stored in the ferroelectric capacitors selected by the bit line 311, the word line 321, and the plate line 332 are read, and after all the ferroelectric capacitors in the memory cells selected by the bit line 311 and the word line 321 are read, the data stored in the ferroelectric capacitors selected by the bit line 311, the word line 322, and the plate line 331 are read, and so on until all the data stored in the ferroelectric capacitors are traversed.

In addition, since the plurality of word lines in the main memory array 20 are in one-to-one correspondence with the bit lines in the mirror memory array 30, the memory cells connected to the same bit line in the mirror memory array 30 have the same degree of disturbance, and therefore, if the access condition of all the word lines in the main memory array 20 is to be known, the ferroelectric capacitor on each word line needs to be read when the data in the mirror memory array 30 is read. For example, in the first reading, the data stored by the x ferroelectric capacitors selected by the bit lines 311 to 31x, the word lines 321 and the plate line 331 are read, wherein the data stored by the ferroelectric capacitors selected by the bit lines 311 to 321 and the plate line 331 is the total access times of the first group of word lines in the main memory array 20, the data stored by the ferroelectric capacitors selected by the bit lines 312 to 321 and the plate line 331 is the total access times of the second group of word lines in the main memory array 20, and the data stored by the ferroelectric capacitors selected by the bit lines 31x to 321 and the plate line 331 is the access times of the x group of word lines in the main memory array 20.

Therefore, when the data stored in the mirror memory array 30 is read, each reading will read the data stored in a plurality of ferroelectric capacitors, and whether the data stored in each ferroelectric capacitor is flipped or not is used to indicate whether the access times of a corresponding group of word lines reach the performance index of the ferroelectric material, if the data stored in a certain ferroelectric capacitor is flipped, the memory cells connected to a group of word lines in the main memory array 20 corresponding to the ferroelectric capacitor are refreshed.

The interval of reading may be determined according to the number of accesses to the main memory array 20, for example, when the total number of accesses to the main memory array 20 reaches the index of the performance of the ferroelectric material, the data in the mirror image memory array 30 is read once, and it is determined whether the number of accesses to a certain group of word lines reaches the index of the performance of the ferroelectric material, and if so, the memory cells connected to the group of word lines are refreshed.

The data stored by the ferroelectric capacitors of the mirror memory array 30 is read bit by bit, and after traversing all of the ferroelectric capacitors of the mirror memory array 30, it is no longer possible to count, at which time a global refresh may be performed on the main memory array 20 and the mirror memory array 30 initialized.

For example, if the main memory array 20 includes x sets of word lines, then at least x bit lines are required to be set in the mirror memory array 30, if the mirror memory array 30 includes m word lines and p stripe lines, when the data stored in the ferroelectric capacitors of the mirror memory array 30 are read, the data stored in the x ferroelectric capacitors are read each time, corresponding to the number of accesses of the x sets of word lines in the main memory array 20, after m×p times of reads, all the data stored in the ferroelectric capacitors of the mirror memory array 30 can be traversed, after traversing is completed, global refreshing is performed on the main memory array 20, and the mirror memory array 30 is initialized, and all the ferroelectric capacitors in the mirror memory array 30 are written with "0" or "1".

Next, in connection with fig. 11, signal states of word lines, bit lines and plate lines in the mirror memory array 30 in the ferroelectric memory refresh process according to the embodiment of the present application will be described.

In the initialization (refresh) phase, all word lines are set at 2.5V, all bit lines are set at 2V, all plate lines are set at 0V, all ferroelectric capacitors in the mirror memory array are written with "1", when the word lines are set at 2.5V, the access transistor is turned on, the bit lines are set at 2V, the plate lines are set at 0V, i.e., the first plate voltage of the ferroelectric capacitors is 2V, the second plate voltage is 0V, and the ferroelectric capacitors are written with "1".

A preparation (standby) stage: all word lines in the mirror image memory array are set at 2.5V, and all access transistors in the mirror image memory array are controlled to be conducted, and all plate lines and bit lines are set at 1V.

When the data of the main memory array is read, all word lines in the mirror memory array are set at 2.5V, all access transistors in the mirror memory array are controlled to be conducted, when the word lines on the main memory array are accessed, the word line addresses on the main memory array are mapped to bit lines in the mirror memory array, the bit lines of the mapped mirror memory array are configured at 2V, and all ferroelectric capacitors corresponding to the bit lines of the mirror memory array bear one disturbance.

Read (stage): after the main memory array is accessed a set number of times, the operation of reading the mirror memory array is performed once (the set number of times is a performance index of the ferroelectric material, for example 10000 times).

And in the pre-charging stage, all the plate lines are set at 1V, the selected word line is set at 2.5V, the unselected word line is set at 0V, and all the bit lines are set at 0V.

And in the excitation stage, selecting a middle plate line set 2 as excitation, selecting an unselected middle plate line set 1V, setting all word lines to 0V, and setting all bit lines Vref (reference voltage).

And in the electric sharing stage, all the plate lines are set at 1V, the selected word line is set at 2.5V, the unselected word line is set at 0V, and the overturning charge generated by the selected ferroelectric capacitor is shared with the bit line.

The sensing stage is that charge sharing is completed, the sense amplifier works to pull the voltage on the bit line to Vw (read 1)/0V (read 0), and the read operation is completed.

And in the write-back stage, the selected word line is set at 2.5V, the unselected word line is set at 0V, the selected plate line is set at 0V, the unselected plate line is set at 1V, and all bit lines are set at 2V, so that write-back operation is completed.

If the read value of the bit line of the mirror image memory array is 1, refreshing the memory cells on a plurality of word lines in the main memory array corresponding to the bit line, and simultaneously refreshing the memory cells on the bit line of the mirror image memory array, and switching the read address of the mirror image memory array (switching the plate line first and then the word line).

If the bit line read value of the mirror memory array is "0", the read address of the mirror memory array is switched (the plate line is switched first, and then the word line is switched).

The memory provided by the embodiment of the application is provided with the mirror image memory array as a counting circuit, the access times of a plurality of word lines in the main memory array are counted, a fuzzy counter is constructed by utilizing the characteristics of ferroelectric materials, the access frequency of ferroelectric capacitors in a periodic memory bank is inaccurately recorded, and only row addresses with access times reaching an access threshold value are refreshed in one operation period. After one memory bank is counted, the mirror image memory array completes one period counting, and the whole memory bank and the mirror image memory array of the main memory array are refreshed.

In addition, the ferroelectric memory provided by the embodiment of the application utilizes the mirror image memory array to construct the fuzzy counter, and the mirror image memory array and the main memory array are both used for storing data by the ferroelectric capacitor and are consistent in influence of temperature, so that the fuzzy counter constructed by the mirror image memory array is used for counting the access positions of word lines in the main memory array more accurately, and the refresh frequency does not need to be adjusted according to the temperature.

Based on the ferroelectric memory provided in the foregoing embodiment, the embodiment of the present application further provides a method for refreshing the ferroelectric memory.

Referring to fig. 12, the refresh method includes:

s602, the counting circuit counts the number of accesses to the plurality of word lines in the main memory array.

S605, when the result of the count of the access times of the plurality of word lines in the main memory array reaches the preset times, refreshing the memory cells connected with the plurality of word lines in the main memory array.

Exemplary, in connection with fig. 13, before S602, the method for refreshing a ferroelectric memory according to the embodiment of the present application further includes:

S601: initializing the mirror memory array, and writing a first logic value into all ferroelectric capacitors of the mirror memory array.

Wherein the first logical value may be "0", or "1".

During the process that the main storage array is accessed, each access can be mapped into the mirror storage array through the mapping circuit, and the access count of the plurality of word lines of the main storage array is further included after S602 and before S605:

s603, after the main memory array is accessed for set times, reading the data stored by one word line and all ferroelectric capacitors on one strip line in the mirror image memory array.

The setting number can be set according to the performance index of the ferroelectric material, for example, 10000 times, where after the main memory array reads the setting number, the data stored in the ferroelectric capacitors in the mirror memory array is read to determine, so as to avoid that when the data in the main memory array is read, all the reads access to the same ferroelectric capacitor, for example, 10000 times of the main memory array is read, and in order to avoid that the 10000 times of the read access to the same ferroelectric capacitor causes the stored data to fail (of course, the probability of occurrence of the situation is extremely low), therefore, the data stored in one word line and all the ferroelectric capacitors on one strip line in the mirror memory array need to be read, so as to determine whether the access number of a plurality of word lines in all the word lines of the main memory array reaches the performance index of the ferroelectric material.

S604, judging whether the result of the count of the access times of a plurality of word lines in the main memory array reaches the preset times.

And judging whether the access times of the plurality of word lines in the main memory array reach the preset times according to the reading result. If the data stored in the ferroelectric capacitor in the memory cell on one bit line of the mirror image memory array is the second logic value, which indicates that the data stored in the ferroelectric capacitor has reached the performance index of the ferroelectric material due to the interference, the step S605 is executed, and if the number of access times of the plurality of word lines of the main memory array corresponding to the bit line has reached the preset number of access times, the step S607 is executed if the data stored in the ferroelectric capacitor in the memory cells on all the bit lines of the mirror image memory array is the first logic value, which indicates that the number of access times count of the plurality of word lines in the main memory array corresponding to all the bit lines of the mirror image memory array has not reached the preset number of access times.

And refreshing the memory cells connected with the plurality of word lines in the main memory array when the result of the access times counting of the plurality of word lines in the main memory array reaches the preset times.

If the read result of the ferroelectric capacitor on the bit line in the mirror image memory array is a second logic value, the data stored by the ferroelectric capacitor reaches the performance index of the ferroelectric material because of the interference, the access times of the plurality of word lines in the main memory array corresponding to the bit line reach the preset times, the memory cells on the plurality of word lines in the main memory array corresponding to the bit line in the mirror image memory array are refreshed, and the data stored by the memory cells on the bit line in the mirror image memory array are refreshed.

If the first logic value is "0", the second logic value may be "1", if the first logic value is "1", the second logic value is "0", and if the read result is the second logic value, that is, the data stored in the ferroelectric capacitor is turned over due to too many times of interference, that is, the total access times of the plurality of word lines in the main memory array corresponding to the one bit line reach the performance index of the ferroelectric material, so that the memory cells on the plurality of word lines in the main memory array need to be refreshed.

After step S605, further includes:

s606, refreshing memory cells on bit lines corresponding to a plurality of word lines with the preset times according to the result of the count of the access times in the main memory array in the mirror image memory array.

When refreshing the memory cells connected with the plurality of word lines of the main memory array, all the memory cells on the bit lines in the mirror image memory array corresponding to the plurality of word lines of the main memory array are required to be refreshed, so that the number of times of accessing the plurality of word lines of the main memory array after the refresh can be counted again.

S607, if all the reading results are the first logic value, the reading address is switched to be read next time.

The switching mode is to switch the plate lines first, and then switch the word lines for reading after traversing all ferroelectric capacitors on one word line and all plate lines.

S608, after traversing the whole mirror image storage array, refreshing the main storage array and initializing the mirror image storage array.

When the data stored in the mirror image storage array is completely read, the data cannot be counted any more, so that the main storage array is globally refreshed, the mirror image storage array is initialized, and the access times of the main storage array are counted again.

The embodiment of the application also provides a memory device, which comprises a controller and the ferroelectric memory provided by the previous embodiment, wherein the controller is coupled with the ferroelectric memory and used for controlling the ferroelectric memory to read and write data.

The steps of a method or algorithm described in connection with the present disclosure may be embodied in hardware, or may be embodied in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in random access memory (random access memory, RAM), flash memory, erasable programmable read-only memory (erasable programmable ROM, EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

Finally, it should be noted that: the foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A ferroelectric memory, characterized in that the ferroelectric memory comprises: the memory device comprises a main memory array and a counting circuit, wherein the main memory array comprises a plurality of word lines and a plurality of memory cells, the word lines extend along a first direction, and the memory cells distributed along the first direction are connected with the same word line;

The memory cell includes an access transistor and a plurality of ferroelectric capacitors, the access transistor is connected with first polar plates of the plurality of ferroelectric capacitors, and the word line is configured to control the conduction state of the access transistor in the memory cell;

The counting circuit is connected with the plurality of word lines and is configured to count the access times of the plurality of word lines;

The main memory array is configured to refresh the memory cells to which the plurality of word lines are connected when the access count of the plurality of word lines reaches a preset count.

2. The ferroelectric memory of claim 1, wherein the counting circuit comprises a mapping circuit and a mirrored memory array, the mirrored memory array comprising: a word line, a bit line, and a plate line, and a plurality of memory cells, the memory cells of the mirrored memory array including an access transistor and a plurality of ferroelectric capacitors, wherein a gate of the access transistor is connected to the word line, a first end of the access transistor is connected to the bit line of the mirrored memory array, a second end of the access transistor is connected to a first plate of the plurality of ferroelectric capacitors, a second plate of the first ferroelectric capacitors is connected to a first plate of the plate line of the mirrored memory array, and a second plate of the second ferroelectric capacitors is connected to a second plate of the plate line of the mirrored memory array;

the ferroelectric capacitor in the mirror memory array is configured to store a first logic value, the word line of the mirror memory array is configured to be in a first level state, so that the access transistor in the mirror memory array is configured to be in a conductive state;

The plurality of word lines of the main memory array are correspondingly connected with one bit line in the mirror image memory array through the mapping circuit.

3. The ferroelectric memory of claim 1, wherein the main memory array further comprises: bit lines and plate lines;

the grid electrode of the access transistor of the main memory array is connected with the word line of the main memory array, the first end of the access transistor is connected with the bit line of the main memory array, and the second end of the access transistor is connected with the first polar plates of the ferroelectric capacitors;

The second polar plate of the first ferroelectric capacitor of the plurality of ferroelectric capacitors is connected with the first plate line of the plate lines of the main memory array, and the second polar plate of the second ferroelectric capacitor of the plurality of ferroelectric capacitors is connected with the second plate line of the plate lines of the main memory array.

4. The ferroelectric memory of claim 2, wherein the main memory array comprises a plurality of sets of word lines, each set of word lines comprising a plurality of word lines, the plurality of sets of word lines of the main memory array corresponding one-to-one to bit lines of the mirror memory array.

5. The ferroelectric memory of claim 4, wherein said mapping circuit comprises a multiplexer through which a set of word lines of said main memory array are connected to bit lines in one of said mirror memory arrays.

6. The ferroelectric memory according to claim 2, wherein the number of accesses to the plurality of word lines in the main memory array to which the bit lines are connected in the mirror memory array is determined to be a preset number when the first logic value stored in the ferroelectric capacitor to which the bit lines are connected in the mirror memory array is changed to the second logic value in the opposite state.

7. A method of refreshing a ferroelectric memory, the ferroelectric memory comprising: the memory device comprises a main memory array and a counting circuit, wherein the main memory array comprises a plurality of word lines and a plurality of memory cells, the word lines extend along a first direction, and the memory cells distributed along the first direction are connected with the same word line; the memory cell includes an access transistor and a plurality of ferroelectric capacitors, the access transistor is connected with a first polar plate of the plurality of ferroelectric capacitors, the word line is configured to control a conduction state of the access transistor in the memory cell, the counting circuit is connected with the plurality of word lines, the method includes:

the counting circuit counts the access times of the plurality of word lines in the main memory array;

And refreshing the memory cells connected with the plurality of word lines in the main memory array when the result of the count of the access times of the plurality of word lines in the main memory array reaches the preset times.

8. The method of claim 7, wherein the counting circuit comprises a mapping circuit and a mirrored memory array, the mirrored memory array comprising: a word line, a bit line, and a plate line, and a plurality of memory cells, the memory cells of the mirrored memory array including an access transistor and a plurality of ferroelectric capacitors, wherein a gate of the access transistor is connected to the word line, a first terminal of the access transistor is connected to the bit line of the mirrored memory array, a second terminal of the access transistor is connected to a first plate of the plurality of ferroelectric capacitors, a second plate of the first ferroelectric capacitor is connected to a first plate of the plate line of the mirrored memory array, a second plate of the second ferroelectric capacitor is connected to a second plate of the plate line of the mirrored memory array, the ferroelectric capacitors of the mirrored memory array are configured to store a first logic value, the word lines of the mirrored memory array are configured to be in a first level state such that the access transistor of the mirrored memory array is configured to be in an on state, the plurality of word lines of the main memory array are connected to a corresponding bit line of the mirrored memory array by the mapping circuit, the method further comprising:

When the ferroelectric capacitor connected with the bit line in the mirror image storage array stores a first logic value which is stored in advance and is turned over to a second logic value with opposite states, determining that the access times of a plurality of word lines in the main storage array corresponding to the bit line in the mirror image storage array reach preset times.

9. The method of claim 8, wherein when the count of the number of accesses to the plurality of word lines in the main memory array reaches a preset number, after refreshing the memory cells connected to the plurality of word lines in the main memory array, the method further comprises:

and refreshing all memory cells connected with the bit lines in the mirror image memory array.

10. A memory device comprising a controller coupled to the ferroelectric memory of any one of claims 1 to 6 for controlling the ferroelectric memory to read and write data.

11. An electronic device comprising a processor and a ferroelectric memory coupled to the processor, wherein the ferroelectric memory is a ferroelectric memory as claimed in any one of claims 1 to 6.