CN118353771A - Detection method, detection device and electronic equipment - Google Patents

Abstract

The application relates to a detection method, a detection device and an electronic device. The method comprises the following steps: the electronic device causing a first device of the electronic device to transmit a test signal to a second device of the electronic device via a communication link; the electronic device causes the second device to determine a received signal associated with the test signal; the electronic device performs an autocorrelation process on the received signal and a test signal generated at the second device; and the electronic device determining an abnormal position in the communication link based on a processing result of the autocorrelation processing. Thereby, detection of an abnormal position in the communication link can be facilitated.

Description

Detection method, detection device and electronic equipment

Technical Field

The present application relates to the field of communications, and more particularly, to a detection method, a detection apparatus, and an electronic device for detecting an abnormal position of a communication link.

Background

In the technology of transmitting high-speed signals by using a high-speed backboard, in order to realize signal connection between different single boards and different chips, the different single boards are usually connected with the backboard through connectors. With the continuous development of communication technology, the baud rate of signals transmitted in a high-speed backboard system is higher and higher, and the problems of error code, broken chain and the like are easily caused by abnormality in a communication link.

There are some methods for detecting abnormal positions of a communication link of a high-speed backboard system at present, for example, in system error code detection, time domain reflectometry (Time domain reflectometry, TDR) detection, positioning by using microwaves and laser ranging, and diagnosis by using bidirectional delay measurement. However, the existing detection method has the defects of low efficiency, high cost and poor feasibility.

Disclosure of Invention

Embodiments of the present disclosure provide an improved detection scheme for detecting communication link anomaly locations.

In a first aspect of the present disclosure, a method of detection is provided. The method comprises the following steps: the electronic device causing the first device of the electronic device to transmit a test signal to the second device of the electronic device via the communication link; the electronic device causes the second device to determine a received signal associated with the test signal; the electronic device performs autocorrelation processing on the received signal and the test signal generated at the second device; and the electronic device determining an abnormal position in the communication link based on a processing result of the autocorrelation processing.

In this way, positioning of the abnormal position of the communication link can be achieved at a low cost without the need for additional components to assist in positioning.

In some embodiments of the first aspect, performing the autocorrelation process comprises: the electronic device performs sampling on a received signal via the communication link to obtain a sampled signal; and the electronic device performs an autocorrelation process on the sampled signal and the test signal.

In this way, the localization of the abnormal position of the communication link can be achieved by performing an autocorrelation analysis with the abnormal communication link itself.

In some embodiments of the first aspect, the communication link is a first communication link, the test signal is a first test signal, the method further comprising: the electronic device causes the first device to transmit a second test signal to the second device via a second communication link adjacent to the first communication link while the first test signal is transmitted, the second test signal being uncorrelated with the first test signal.

In some embodiments of the first aspect, performing the autocorrelation process comprises: the electronic device performing sampling of the received signal via the second communication link to obtain a sampled signal; and the electronic device performs an autocorrelation process on the sampled signal and the first test signal.

In this way, the positioning of the abnormal position of the communication link can be achieved by performing autocorrelation analysis on the interference generated by the adjacent communication link by using the abnormal communication link.

In some embodiments of the first aspect, further comprising: the electronic device stores a line length and a corresponding delay between passive nodes of one or more communication links between the first device and the second device, the one or more communication links comprising the communication link, prior to transmitting the test signal.

In some embodiments of the first aspect, determining the anomaly location comprises: based on the processing results of the autocorrelation process, the electronic device determines a relative delay between a plurality of reflection points in the communication link; and determining, by the electronic device, an anomaly location in the communication link based on the relative delays between the plurality of reflection points and the line lengths and corresponding delays between the plurality of passive nodes of the stored communication link.

In some embodiments of the first aspect, further comprising: before sending the test signal, the electronic device causes the first device to send a handshake signal to the second device via the communication link; if the second device successfully analyzes the handshake signal, the electronic equipment enables the first device to send a test signal; and if the second device does not successfully resolve the handshake signal, the electronic device determines that the communication link is open or shorted.

In this way, it can be determined whether the communication link is normal for low-speed communication, if the low-speed communication is abnormal, it is directly determined that the communication link is open or short, and if the low-speed communication is normal, detection as described in the present disclosure is entered.

In some embodiments of the first aspect, performing sampling comprises: the electronic equipment performs equalization processing and clock data recovery processing on the received signal to obtain a processed received signal; and the electronic device performs high-speed high-resolution analog-to-digital converter ADC sampling on the processed received signal.

In some embodiments of the first aspect, performing sampling further comprises: the electronic device performs high-speed oversampling of the received signal.

In some embodiments of the first aspect, the test signal is one of a plurality of test signals at a plurality of test frequencies, the processing result is one of a plurality of processing results corresponding to the plurality of test frequencies, and determining the anomaly location in the communication link comprises: the electronic device determines an abnormality location based on the plurality of processing results.

In this way, the anomaly location can be determined using a multiple test frequency joint test, further improving the accuracy of the test over using a single test frequency.

In some embodiments of the first aspect, further comprising: based on the result of the autocorrelation process, the electronic device determines ratios of reflected noise at a plurality of reflection points in the communication link to the main signal of the received signal; and determining, based on the ratio, that the abnormal location results in a failure of the communication link by the electronic device.

In this way, the effect of reflections from anomalies in the communication link on the link can be evaluated and it can be determined whether the communication link failure was indeed due to anomalies.

In a second aspect of the present disclosure, a detection apparatus is provided. The device comprises: a trigger unit configured to cause the first device of the detection apparatus to transmit a test signal to the second device of the detection apparatus via the communication link; a first determining unit configured to cause the second device to determine a received signal associated with the test signal; a processing unit configured to perform an autocorrelation process on the received signal and a test signal generated at the second device; and a second determination unit configured to determine an abnormal position in the communication link based on a processing result of the autocorrelation processing.

In some embodiments of the second aspect, the processing unit is further configured to: performing sampling on a received signal via a communication link to obtain a sampled signal; and performing an autocorrelation process on the sampled signal and the test signal.

In some embodiments of the second aspect, the communication link is a first communication link, the test signal is a first test signal, and the trigger unit is further configured to: the first device is caused to transmit a second test signal to the second device via a second communication link adjacent to the first communication link while the first test signal is transmitted, the second test signal being uncorrelated with the first test signal.

In some embodiments of the second aspect, the processing unit is further configured to: performing sampling on the received signal via the second communication link to obtain a sampled signal; and performing an autocorrelation process on the sampled signal and the first test signal.

In some embodiments of the second aspect, the apparatus further comprises: and a storage unit configured to store, prior to transmitting the test signal, a line length and a corresponding delay between passive nodes of one or more communication links between the first device and the second device, the one or more communication links comprising a communication link.

In some embodiments of the second aspect, the second determining unit is further configured to: determining a relative delay between a plurality of reflection points in the communication link based on a processing result of the autocorrelation process; and determining an anomaly location in the communication link based on the relative delays between the plurality of reflection points and the line lengths and corresponding delays between the plurality of passive nodes of the stored communication link.

In some embodiments of the second aspect, the trigger unit is further configured to: before sending the test signal, causing the first device to send a handshake signal to the second device via the communication link; if the second device successfully analyzes the handshake signal, the first device sends a test signal; and the second determining unit is further configured to: if the second device does not successfully resolve the handshake signal, it is determined that the communication link is open or shorted.

In some embodiments of the second aspect, the processing unit is further configured to: performing equalization processing and clock data recovery processing on the received signal to obtain a processed received signal; and performing high-speed high-resolution analog-to-digital converter ADC sampling on the processed received signal.

In some embodiments of the second aspect, the processing unit may be further configured to: high-speed oversampling is performed on the received signal.

In some embodiments of the second aspect, the test signal is one of a plurality of test signals at a plurality of test frequencies, the processing result is one of a plurality of processing results corresponding to the plurality of test frequencies, and the second determination unit is further configured to: an anomaly location is determined based on the plurality of processing results.

In some embodiments of the second aspect, the second determining unit is further configured to: determining a ratio of reflected noise at a plurality of reflection points in the communication link to a main signal of the received signal based on a processing result of the autocorrelation processing; and determining, based on the ratio, that the anomaly location results in a failure of the communication link.

In a third aspect of the present disclosure, there is provided an electronic device comprising at least one processor and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions when executed by the at least one processor cause the electronic device to: the electronic device causing the first device of the electronic device to transmit a test signal to the second device of the electronic device via the communication link; the electronic device causes the second device to determine a received signal associated with the test signal; the electronic device performs autocorrelation processing on the received signal and the test signal generated at the second device; and the electronic device determining an abnormal position in the communication link based on a processing result of the autocorrelation processing.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: the electronic device performs sampling on a received signal via the communication link to obtain a sampled signal; and the electronic device performs an autocorrelation process on the sampled signal and the test signal.

In some embodiments of the third aspect, the communication link is a first communication link, the test signal is a first test signal, the instructions, when executed by the at least one processor, cause the electronic device to implement: the electronic device causes the first device to transmit a second test signal to the second device via a second communication link adjacent to the first communication link while the first test signal is transmitted, the second test signal being uncorrelated with the first test signal.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: the electronic device performing sampling of the received signal via the second communication link to obtain a sampled signal; and the electronic device performs an autocorrelation process on the sampled signal and the first test signal.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: the electronic device stores a line length and a corresponding delay between passive nodes of one or more communication links between the first device and the second device, the one or more communication links comprising the communication link, prior to transmitting the test signal.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: based on the processing results of the autocorrelation process, the electronic device determines a relative delay between a plurality of reflection points in the communication link; and determining, by the electronic device, an anomaly location in the communication link based on the relative delays between the plurality of reflection points and the line lengths and corresponding delays between the plurality of passive nodes of the stored communication link.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: before sending the test signal, the electronic device causes the first device to send a handshake signal to the second device via the communication link; if the second device successfully analyzes the handshake signal, the electronic equipment enables the first device to send a test signal; and if the second device does not successfully resolve the handshake signal, the electronic device determines that the communication link is open or shorted.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: the electronic equipment performs equalization processing and clock data recovery processing on the received signal to obtain a processed received signal; and the electronic device performs high-speed high-resolution analog-to-digital converter ADC sampling on the processed received signal.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: the electronic device performs high-speed oversampling of the received signal.

In some embodiments of the third aspect, the test signal is one of a plurality of test signals at a plurality of test frequencies, the processing result is one of a plurality of processing results corresponding to the plurality of test frequencies, the instructions, when executed by the at least one processor, cause the electronic device to implement: the electronic device determines an abnormality location based on the plurality of processing results.

In some embodiments of the third aspect, the instructions, when executed by the at least one processor, cause the electronic device to: based on the result of the autocorrelation process, the electronic device determines ratios of reflected noise at a plurality of reflection points in the communication link to the main signal of the received signal; and determining, based on the ratio, that the abnormal location results in a failure of the communication link by the electronic device.

In a fourth aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement operations according to the method in the first aspect or any embodiment thereof.

In a fifth aspect of the present disclosure, a computer program or computer program product is provided. The computer program or computer program product is tangibly stored on a computer-readable medium and comprises computer-executable instructions which, when executed, implement operations in accordance with the method in the first aspect or any embodiment thereof described above.

In a sixth aspect of the present disclosure, a chip or chip system is provided. The chip or chip system comprises processing circuitry configured to perform operations according to the method of the first aspect or any embodiment thereof described above.

As will be appreciated from the following description of the exemplary embodiments, according to the technical solutions presented herein, positioning of an abnormal position of a communication link may be achieved with lower cost, chip area, and power consumption, and the technical solutions of the present disclosure have higher feasibility.

It should be understood that the description in this summary is not intended to limit key or critical features of the disclosed embodiments, nor is it intended to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

FIG. 1 illustrates a schematic diagram of a high-speed backplane system in which embodiments of the present disclosure may be implemented;

Fig. 2 shows a schematic diagram of a high-speed connector mismatch mating limit stub;

FIG. 3A shows a schematic diagram of a high-speed communication link signal spectrum with reflection;

FIG. 3B shows a schematic diagram of the frequency domain response and the time domain response of the high speed communication link with reflection;

FIG. 4 shows a schematic diagram of error detection of a high-speed serdes communication link;

FIG. 5 shows a schematic diagram of TDR detection for a high-speed serdes communication link;

FIG. 6 shows a high-speed serdes communication link detection schematic using microwave, laser ranging;

FIG. 7 illustrates a simplified flow chart of a detection method suitable for implementing embodiments of the present disclosure;

FIGS. 8A and 8B illustrate a schematic flow chart diagram of a detection method utilizing an abnormal link itself, according to some embodiments of the present disclosure;

fig. 9 illustrates a high-speed communication link topology diagram in accordance with some embodiments of the present disclosure;

FIG. 10 illustrates a schematic diagram of high-speed communication link reflection detection using pseudo-random encoding in accordance with some embodiments of the present disclosure;

FIG. 11 illustrates a schematic diagram of selecting multiple frequency points for detection in accordance with some embodiments of the present disclosure;

FIGS. 12A and 12B illustrate schematic flow diagrams of methods of detecting interference to neighboring links with an anomalous link in accordance with further embodiments of the disclosure;

Fig. 13 illustrates a high-speed communication link topology diagram in accordance with further embodiments of the present disclosure;

FIG. 14 illustrates a schematic block diagram of a detection apparatus according to some embodiments of the present disclosure;

FIG. 15 shows a schematic block diagram of a detection apparatus according to further embodiments of the present disclosure;

FIG. 16 shows a schematic block diagram of a detection apparatus according to further embodiments of the present disclosure;

FIG. 17 shows a schematic block diagram of a detection device according to further embodiments of the present disclosure;

FIG. 18 shows a schematic block diagram of a detection apparatus according to further embodiments of the present disclosure;

FIG. 19 shows a schematic block diagram of a detection apparatus according to further embodiments of the present disclosure;

FIG. 20 illustrates a simplified block diagram of a detection apparatus suitable for implementing embodiments of the present disclosure; and

FIG. 21 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the embodiments of the present disclosure have been illustrated in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". The term "electronic device" may refer to any electronic device, including a computer, a backplane system, a single board, a processor, a chip, a telecommunications network device, a server, or other similar device. Related definitions of other terms will be given in the description below.

It will be understood that, although the terms "first" and "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, likewise, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the listed terms.

Fig. 1 illustrates a schematic diagram of a high-speed backplane system 100 in which embodiments of the present disclosure may be implemented. The high-speed backplane system 100 includes a first board 110, a second board 120, a first connector 130-1, a second connector 130-2, and a backplane 140. The first board 110 has a first chip disposed thereon, and the second board 120 has a second chip disposed thereon. The first board 110 is connected to the back plane 140 through the first connector 130-1, and the second board 120 is connected to the back plane 140 through the second connector 130-2. The first board 110 may serve as a transmitting side, the second board 120 may serve as a receiving side, and the first board 110 and the second board 120 may communicate with each other, for example, via a communication link 150. The high-speed backplane system 100 may also be referred to as an electronic device 100.

It should be understood that the number of individual elements in fig. 1 is merely an example and is not intended to be limited to the number shown in the figures. For example, fig. 1 may naturally also include more boards, more connectors, and more communication links. Furthermore, while illustrative examples of high speed backplane systems are shown herein, it is understood that high speed backplane systems may have other layouts.

As mentioned previously, as the baud rate of signals transmitted in high-speed backplane systems increases, anomalies are likely to occur in the communication link. For example, as shown in fig. 2, the high-speed connector 130 includes at least two mating reeds 130-1 and 130-2, the mating reeds 130-1 and 130-2 are snapped together, and the right end of the mating reed 130-1 extends a distance relative to the snap-fit point, which is the mismatch mating limit length stub of the high-speed connector 130. Due to stub, the waveform will reflect during propagation.

Assuming that the mismatch mating limit length stub of the high-speed connector 130 is X, the delay is τ ₀, and the signal wave speed is v, there isAs shown in fig. 3, the signal spectrum is lowest in amplitude at the frequency ω= (2n+1) pi/τ ₀ (n is an integer) because the main useful signal is attenuated due to resonance caused by stub reflection. Selecting the 1 st resonance point frequencyConsidering the signal wavelength as lambda, thenX= (1/4) λ was derived. In other words, when stub length X of high-speed connector 130 is 1/4 of signal wavelength λ, a reflective resonance point occurs, resulting in a deep selective attenuation of the useful signal. Therefore, in order to reduce or eliminate the reflection effect, it is required that stub length X must satisfy the following condition:

X < - (1/4) lambda > (equation 1)

When the stub length of the high-speed connector does not satisfy equation 1, reflection introduced by the stub may cause degradation of signal quality of the high-speed communication link, as shown in fig. 3A, reflection may cause degradation of signal spectrum amplitude, as shown in fig. 3B, reflection may cause degradation of insertion loss and generate interference response, and these problems may cause problems of communication link error, link breakage, and the like.

In practical applications, there are many events that the mismatch mating limit length stub of the high-speed connector does not meet the formula 1 and causes abnormal links, such as feeding of the high-speed connector, problems caused by transportation, micro-deformation of system structural dimensions, abnormal high-speed connectors in the production, processing and manufacturing processes, and misplaced on-site application veneers. These problems can lead to high speed backplane communication link errors, broken links, etc. Once the similar problems appear, because the current abnormal positioning means are limited, operators are sometimes required to go to the site to perform positioning operation, and the extreme means need to plug and unplug the problem single board, which can cause service interruption and low positioning efficiency.

There are some solutions or ideas currently existing to detect abnormal locations of communication links of high-speed backplane systems. As an example, consider locating a communication link anomaly through error detection at system traffic, as shown in fig. 4. With the scheme, because the number of trigger factors related to the error code is large, and the trigger factors are not necessarily caused by abnormal links, the fault point can not be accurately and timely positioned easily, the positioning efficiency is low, and sometimes the error positioning can exist.

As another example, as shown in fig. 5, it is considered to determine a reflection position, reflection impedance, and the like by measuring a reflection echo using the TDR technique. However, if the scheme needs high positioning precision, the bandwidth requirement on the required TDR signal is extremely high, the implementation difficulty is extremely high, and the feasibility is poor. In addition, in order to satisfy the capability of transmitting signal waves and receiving echoes, the method requires that each channel inside the serdes at the transmitting and receiving ends of the high-speed communication link is compatible with the transmitting and receiving functions, which leads to a significant increase in chip area and power consumption, and finally leads to a significant increase in implementation cost.

As yet another example, as shown in fig. 6, using microwave, laser ranging, the communication link anomalies are located by measuring the distance and distance changes between a flexible board and a fixed board or an electrical interconnect backplane. Firstly, under the condition of no error code, the distance range between the flexible single board and the fixed single board or the electric interconnection backboard is measured, and then under the condition of error code, the distance between the flexible single board and the fixed single board or the electric interconnection backboard is measured. And comparing the results of the two measurements, confirming whether the distance threshold is exceeded, and confirming that the distance range between the flexible single board and the fixed single board or the electric interconnection backboard is the root cause of the error code based on whether the error code exists in the high-speed communication link. However, for laser ranging, the mirror surface of the laser device is generally exposed to the outside and is easily affected by dust, and for microwave ranging, there is an electromagnetic compatibility (EMC) interference problem. The scheme requires high distance measurement accuracy, otherwise, the abnormal position cannot be accurately positioned, and laser or microwave transmitting and detecting equipment is additionally added, so that equipment cost is increased.

As yet another example, consider the use of a bi-directional delay measurement diagnostic technique to locate a communication link anomaly. However, this solution requires very high end-to-end jitter requirements for the system, and in order to meet the jitter requirements, the signal communication problem at a board of several hundred GHZ needs to be solved, which is practically difficult to achieve.

It can be seen that the existing detection scheme or idea has the defects of low efficiency, high cost, poor feasibility and the like. There is a need for communication link anomaly localization at a lower cost.

To solve the above-mentioned problems and other problems that are potentially addressed, embodiments of the present disclosure provide a solution for detecting anomalies in a communication link, which aims to achieve positioning of anomalies in a communication link with lower cost, lower chip area, lower power consumption, without the need for additional devices to aid in positioning, and which is easy to implement in existing high-speed backplane systems, and which can improve the efficiency of positioning of field problems.

Different examples of detection methods according to embodiments of the present disclosure are described below in connection with fig. 7 to 13. It should be understood that the detection methods in these embodiments may include other additional steps not shown, or some steps shown may be omitted, and the order of the steps is for illustrative purposes only, and the scope of the present disclosure is not limited in this respect. In one embodiment, the detection method may be performed by a computer, and more particularly, by a processor. Alternatively, the detection method may be performed by other electronic devices having a calculation function, which is not limited by the present disclosure.

Fig. 7 illustrates a simplified flow chart of a detection method 700 suitable for implementing embodiments of the present disclosure. For convenience, fig. 7 will be described herein in connection with the example of fig. 1. The process 700 may involve the electronic device 100, the first board 110, the second board 120, the communication link 150.

In step 710, the electronic device 100 causes a first device of the electronic device 100 (e.g., the first board 110) to transmit a test signal to a second device of the electronic device 100 (e.g., the second board 120) via the communication link 150. In some embodiments, the test signal may be a pseudo-randomly encoded signal. The first device and the second device are not limited to a single board, but may be chips, or any other single board assembly.

In step 720, the electronic device 100 causes the second device 120 to determine a received signal associated with the test signal.

In step 730, the electronic device 100 performs an autocorrelation process on the received signal and the test signal generated at the second component 120. The test signal generated at the second device 120 is generated using the same pseudo-random generation code as the test signal transmitted by the first device 110. The autocorrelation reflects the correlation between the instantaneous value of the signal at 1 time and the instantaneous value at the other 1 time.

In step 740, the electronic device 100 determines an abnormal position in the communication link 150 based on the processing result of the autocorrelation processing.

In some embodiments, during the execution of the autocorrelation process by electronic device 100, electronic device 100 may perform sampling of the received signal via communication link 150 to obtain a sampled signal. The electronic device 100 may then perform an autocorrelation process on the sampled signal and the test signal.

Alternatively or additionally, in some embodiments, the communication link 150 is a first communication link and the test signal is a first test signal. While the first test signal is being transmitted, the electronic device 100 causes the first device 110 to transmit a second test signal to the second device 120 via a second communication link adjacent to the first communication link 150, the second test signal being uncorrelated with the first test signal. In some embodiments, to perform the autocorrelation process, the electronic device 100 may perform sampling of the received signal via the second communication link to obtain a sampled signal. The electronic device 100 may then perform an autocorrelation process on the sampled signal and the first test signal.

In some embodiments, prior to transmitting the test signal, electronic device 100 stores a line length and a corresponding delay between passive nodes of one or more communication links between first device 110 and second device 120, including communication link 150.

In some embodiments, in determining the location of the anomaly, the electronic device 100 may determine a relative delay between a plurality of reflection points in the communication link based on the processing results of the autocorrelation process. Thereafter, based on the relative delays between the plurality of reflection points and the line lengths and corresponding delays between the plurality of passive nodes of the stored communication link, electronic device 100 may determine the location of the anomaly in communication link 150.

In some embodiments, electronic device 100 causes first device 110 to send handshake signals to second device 120 via communication link 150 prior to sending the test signals. If the second device 120 successfully parses the handshake signal, the electronic device 100 causes the first device 110 to send a test signal. If the second device 120 does not successfully resolve the handshake signal, the electronic device 100 determines that the communication link 150 is open or shorted.

In some embodiments, during the process of the electronic device 100 performing sampling, the electronic device 100 performs an equalization process and a clock data recovery process on the received signal to obtain a processed received signal. Then, the electronic device 100 performs high-speed high-resolution ADC sampling on the processed reception signal. Alternatively or additionally, the electronic device 100 performing sampling includes: the electronic device 100 performs high-speed oversampling of the received signal. In some embodiments, oversampling means sampling at a sampling frequency that is more than twice the signal rate.

In some embodiments, the test signal is one of a plurality of test signals at a plurality of test frequencies and the processing result is one of a plurality of processing results corresponding to the plurality of test frequencies. In the process of the electronic device 100 determining the abnormal position in the communication link 150, the electronic device 100 determines the abnormal position based on a plurality of processing results.

In some embodiments, based on the results of the autocorrelation process, electronic device 100 determines the ratio of reflected noise at a plurality of reflection points in communication link 150 to the primary signal of the received signal. Then, based on the ratio, the electronic device 100 determines that the abnormal position causes a failure of the communication link 150.

Fig. 8A and 8B illustrate a schematic flow chart diagram of a detection method 800 utilizing an abnormal link itself, according to some embodiments of the present disclosure. In this embodiment, the localization of the abnormal position of the communication link is achieved by performing an autocorrelation analysis using the abnormal communication link itself. Fig. 8A and 8B correspond to an example implementation of the detection method shown in fig. 7.

In step 810, since the topology lengths of the traces between passive nodes (e.g., high-speed connectors, link pads, ball grid array package (BGA) pads, etc.) in the middle of the high-speed communication link are known, based on the known topology lengths, the relative delay td _i between the passive nodes may be obtained, and the electronic device 100 records and stores these topology lengths and corresponding relative delay td _i data via the system database for subsequent anomaly detection. As shown in fig. 9, topology lengths L1, L2, L3 and their corresponding relative delays may be recorded into a system database.

In step 820, the electronic device 100 initiates link detection when the high-speed communication link initially establishes a link, the high-speed communication link is abnormal (e.g., code detection is abnormal, there is an error code or a broken link), the high-speed communication link has a cyclic redundancy check (Cyclic redundancy check, CRC) error, and an attempt is made to reestablish the link.

In step 830, the electronic device 100 detects whether the high-speed communication link is capable of normal low-speed communication using the low-speed baud rate handshake signal to determine whether the link is completely unusable due to an open circuit or short circuit. The transmitting side of the electronic device 100 sends a low-speed baud rate handshake signal to the receiving side, the receiving side presets the coding and format of the handshake signal, and if the receiving side can normally analyze the received low-speed handshake signal, it indicates that the link low-speed communication is normal, and step 840 is entered. If the receiving side cannot normally parse the received low-speed handshake signal, the process proceeds to step 832, where the link is considered to be completely unavailable due to an open circuit or a short circuit, or the system is considered to have no anomaly detection capability, and the process is then ended.

In step 840, the electronic device 100 determines whether the test frequency points have all been detected. As shown in fig. 11, the test bins may select one or more bins as indicated by the arrows. If it is determined that all the test frequency points are not used up, step 850 is performed, where the electronic device 100 selects 1 test frequency point and configures the same test frequency point for the servers on both sides.

In step 860, the transmitting side of the electronic device 100 transmits a pseudo-random (PN) code signal at the test frequency point to the receiving side. For example, the signal on the transmitting side is s ₁(t)＝A₁ c (T), where a ₁ is the amplitude, c (T) is the pseudo-random code corresponding to the test frequency point, the pseudo-random code period P is greater than 2 times the round trip flight time T of the high-speed communication link, i.e., P >2T, t= 2*L/v, where L is the total length of the high-speed communication link, and v is the wave velocity. Referring to fig. 10, the channel impulse response h (t) = Σh _i(t),h_i (t) is the impulse response caused by reflection of a certain passive node in the communication link as well as the impulse response of the main signal. Thus, the incident signal reaching the receiving sideWhere η _i is the reflectivity and τ _i is the reflection delay caused by the reflection of a certain passive node.

In step 870, the receiving side of the electronic device 100 samples the channel pseudorandom encoded signal using a high-speed high-resolution analog-to-digital converter (ADC) and buffers the sampled data into Random Access Memory (RAM) for subsequent processing, the sampled data length covering at least 1 pseudorandom encoding period length.

In some embodiments, ADC sampling may be performed in a synchronous manner, with equalization algorithm convergence at the receiving side, sampling after locking by a clock data recovery (Clock data recovery, CDR) unit. The received data may be sampled directly or the equalized received data may be sampled. In some embodiments, for high-speed communication links that are Non-return to zero (NRZ) (PAM 2) encoded, the high-order high-resolution ADC is used for sampling during detection, and the 1-order 1-bit ADC is used for sampling in the Non-detection mode (i.e., normal mode). In other embodiments, for PAM4 encoded high speed communication links, high order high resolution ADCs are used throughout for sampling to facilitate subsequent full digital equalization processing. The equalized eye pattern data can be sampled by a high-order high-resolution ADC for any high-speed communication link of any coding scheme.

Alternatively or additionally, in some embodiments, ADC sampling may be performed in an asynchronous manner, directly using high-speed oversampling to sample the data, without the data having to be directly sampled after equalization convergence or CDR locking by the receiving side. In some embodiments, oversampling means sampling at a sampling frequency that is more than twice the signal rate.

The sub-flow of step 880 then proceeds to as shown in fig. 8B. In step 881, the receiving side of the electronic device 100 generates a local pseudo-random code using the same generated code as the transmitting side, and performs an autocorrelation cyclic convolution process on the sampled and buffered pseudo-random encoded signal data and the locally generated pseudo-random code until the local pseudo-random code period is reached, and then stops to obtain a channel response under the convolution condition. For example, the receiving side generates a local pseudorandom code s ₃(t)＝A₂ c (t), where a ₂ is the amplitude and may be the same or different from a ₁, c (t) is a pseudorandom code corresponding to the same test frequency point as the transmitting side, and performs an autocorrelation cyclic convolution process on the sampled and buffered pseudorandom coded signal data s ₂ (t) and the locally generated pseudorandom code s ₃ (t):

Wherein, Representative convolution, R' (τ) is the result of the receive side autocorrelation cyclic convolution processing, and R (τ) is the known ideal PN code normalized autocorrelation function. As shown in fig. 10, R' (τ) is the result of the convolution and linear superposition of the PN code ideal autocorrelation function a ₂A₁η_i R (t) and the channel impulse response h _i (t).

Next, the phase τ of the local pseudo-random code is successively shifted as a start point of the circular convolution, the repeated and sampled data is subjected to an autocorrelation process, and the convolution result R' (i) and the corresponding shift position τ _i of each time are recorded. Alternatively, the different positions of the cached pseudo-random signal sampling data can be selected successively to serve as the start point of the circular convolution, and the sampling data can be circularly used end to end, so that the availability of the completed pseudo-random code period data can be ensured.

In step 882, a plurality of impulse responses R '(τ) of the autocorrelation function R (τ) of the channel are obtained by the autocorrelation process in step 881, and the N data having the largest value of the cyclic convolution result R' (i) are selected. It is readily understood that the main signal corresponds to the maximum value of R' (i). Specifically, at step 883, the decision threshold is followedThe N data with the highest peak of R' (τ) at the top are selected for analysis.

In step 884, peak R ' (i) corresponding to each delay τ _i is obtained through different delays and corresponding peak comparison analysis, relative delay td _i＝|τ_i-τ_j l is calculated through two peaks R ' (i) and R ' (j), and finally all relative delays are obtained, τ _i、τ_j being the positions (expressed in terms of time meaning) of 2 different reflection points.

In step 885, the calculated relative delay td _i is used to analyze the mismatch between the calculated relative delay and the relative delay in the database, i.e. the position of the abnormal reflection point, in combination with the link topology length and the corresponding relative delay data in the database recorded in step 810.

In step 886, the electronic device 100 may also evaluate the effect of the reflection on the communication link based on the N data having the greatest value of the selected cyclic convolution result R' (i). As shown in table 1, assuming that there are 2 reflection points 1 and 2, the symbol occurrence probability is random and average, p '(1) is the symbol 1 reflection influence power, and p' (2) is the symbol 2 reflection influence power, the total average power of the influence of two reflection position symbols 1 and 2 on the main signal symbol 3Similarly, the total average power of more reflection points on the same 1 symbol position

TABLE 1

Assuming that p' (0) is the peak power of the ideal signal to the receiving side, the average power of the ideal signal To calculate the effect of the reflected signal as noise on the main signal link, the ratio L can be defined for use as an effect estimateAccording to the pasmodic theorem, L' is defined:

Where i=1, … N-1, R '(i) is the reflected signal autocorrelation impulse response peak, and R' (0) is the maximum of the N values selected (i.e., the main signal convolution result).

In step 887, it is determined whether the L' value is abnormal, whether the reflection has a negative impact on the link, and whether the channel can be used normally, by a certain decision threshold. If it is determined that the reflection has a negative impact on the link, it is determined that the communication link is indeed faulty due to the abnormal position of the reflection.

Then, returning to step 840, it is continuously determined whether all the test frequency points have been tested. If all the test frequency points have been used up, step 842 is performed to configure the transceiver side as the normal operating frequency point and configure the transceiver side serdes as the normal operating mode. Next, in step 844, the relative delays td _i and the reflected noise ratio values L' of the respective frequency bin analyses are combined, and the reflection point positions and the effect of the reflection on the communication link are analyzed. Then, in step 846, the test results are reported and the test is ended.

Fig. 12A and 12B illustrate schematic flow diagrams of methods of detecting interference to neighboring links with an anomalous link in accordance with further embodiments of the disclosure. In this embodiment, the localization of the abnormal position of the communication link is achieved by indirectly performing autocorrelation analysis on interference generated by the adjacent communication link by using the abnormal communication link. Fig. 12A and 12B correspond to another example implementation of the detection method shown in fig. 7.

As shown in fig. 13, there may be A, B communication links between the board 1 and the board 2, when the a link has reflection due to impedance mismatch of the high-speed connector, the a link generates 1 reflection and interferes with the adjacent link B, the echo of the 1 reflection generated by the a link generates reflection again and 2 interference with the adjacent link B, and finally the a link generates multiple interference to the B link due to the reflection, and the a link generates multiple interference responses to the B link.

In step 1210, since the topology lengths of the traces between passive nodes (e.g., high-speed connectors, link pads, ball grid array package (BGA) pads, etc.) in the middle of the high-speed communication link are known, based on the known topology lengths, the relative delay td _i between the passive nodes may be obtained, and the electronic device 100 records and stores these topology lengths and corresponding relative delay td _i data via the system database for use in subsequent anomaly detection. As shown in fig. 13, topology lengths L1, L2, L3 and their corresponding relative delays may be recorded into a system database.

In step 1220, the electronic device 100 initiates a link detection when the high speed communication link a initially establishes a link, the high speed communication link a has an anomaly (e.g., an encoding detection anomaly, a bit error, or a broken link), the high speed communication link a has a CRC error, and an attempt is made to reestablish a link.

In step 1230, the electronic device 100 detects whether the high-speed communication link a is capable of normal low-speed communication using the low-speed baud rate handshake signal to determine whether the a-link is completely unusable due to an open circuit or a short circuit. The transmitting side of the electronic device 100 transmits the low-speed baud rate handshake signal to the receiving side, the receiving side presets the coding and format of the handshake signal, and if the receiving side can normally analyze the received low-speed handshake signal, it indicates that the link low-speed communication is normal, and step 1240 is entered. If the receiving side cannot normally parse the received low-speed handshake signal, the process proceeds to step 1232, where the a link is considered to be completely unavailable due to an open circuit or a short circuit, or the system is considered to have no anomaly detection capability, and the process is ended.

In step 1240, the electronic device 100 determines whether the test frequency points have all been detected. If it is determined that all the test frequency points have not been used up, step 1250 is entered, where the electronic device 100 selects 1 test frequency point and configures the same test frequency point for the transmitting and receiving sides serdes of the communication links a and B.

In step 1260, the transmitting side of electronic device 100 transmits the uncorrelated pseudo-random (PN) coded signal at the test frequency point to the receiving side on both the A-link and the B-link. The pseudo-random code period P is greater than 2 times the round trip flight time T of the high speed communication link, i.e., P >2T, t= 2*L/v, where L is the total length of the high speed communication link and v is the wave speed. For example, the signal is sent on the a-link as s ₁(t)＝A₁c₁ (t) and on the B-link as s ₂(t)＝A₂c₂ (t), where a ₁、A₂ is the amplitude and c ₁(t)、c₂ (t) is the uncorrelated pseudorandom code corresponding to the test frequency bin. c ₁ (t) and c ₂ (t) may be uncorrelated by selecting different code periods, or may be uncorrelated by selecting the same generated code, different initial phases. If a different initial phase is chosen, e.g., c ₁(t)＝c(t-τ₀)、c₂(t)＝c(t-τ₀ '), the phase delay difference of the pseudo-random encodings c ₁ (t) and c ₂ (t) requires a high speed communication link round trip time of greater than 2 times to ensure that the two subsequent convolutions remain uncorrelated, where |τ ₀-τ₀' | >2*L/v, where L is the longest high speed link length and v is the wave speed.

Channel impulse response h (t) = Σh _i(t),h_i (t) is the impulse response caused by the reflection of a passive node in the a communication link to the B communication link. Thus, the incoming signal arriving at the receiving side of the B link Where τ _i is the reflection delay caused by reflection at some passive node on the a-link and h ₂ (t)' is the impulse response in the B-link.

In step 1270, the B-link receiving side of the electronic device 100 samples the channel pseudorandom encoded signal using a high-speed high-resolution ADC and buffers the sampled data into RAM for subsequent processing, the sampled data length covering at least 1 pseudorandom encoding period length.

In some embodiments, ADC sampling may be performed in a synchronous manner, where the equalization algorithm converges on the receiving side of the B-link, and sampling is performed after locking by the CDR unit. The received data may be sampled directly or the equalized received data may be sampled. In some embodiments, for NRZ (PAM 2) encoded high speed communication links, high order high resolution ADCs are used for sampling during detection and 1 order 1 bit ADCs are used for sampling in non-detection mode (i.e., normal mode). In other embodiments, for PAM4 encoded high speed communication links, high order high resolution ADCs are used throughout for sampling to facilitate subsequent full digital equalization processing. The equalized eye pattern data can be sampled by a high-order high-resolution ADC for any high-speed communication link of any coding scheme.

Alternatively or additionally, in some embodiments, the ADC sampling may be in an asynchronous manner, with the B-link receiving side sampling the data directly with high-speed oversampling, the data not requiring direct sampling after equalization convergence or CDR locking by the receiving side. In some embodiments, oversampling means sampling at a sampling frequency that is more than twice the signal rate.

Then, the sub-flow of step 1280 is entered as shown in fig. 12B. In step 1281, the B-link receiving side of electronic device 100 generates a local pseudorandom code using the same generated code as the a-link transmitting side.

In step 1282, the electronic device 100 performs an autocorrelation cyclic convolution process on the pseudo-random encoded signal data sampled and buffered by the B-link and the locally generated pseudo-random code until the local pseudo-random code period of the B-link is reached, and then stops to obtain a channel response of the B-link interfered by the a-link under the convolution condition. For example, the B-link receiving side generates a local pseudorandom code s ₄(t)＝A₄c₁ (t- τ), where a ₄ is the magnitude, which may be the same or different from a ₁, c ₁ (t- τ) is a pseudorandom code corresponding to the same test frequency point as the a-link transmitting side, τ is a different initial phase. The B link receiving side carries out autocorrelation cyclic convolution processing on the sampled and buffered pseudorandom code signal data s ₃ (t) and the locally generated pseudorandom code s ₄ (t):

Wherein, Representative convolution, τ is a successive cyclic convolution delay, R' (τ) is a result of a convolution processing of a B-link receiving side signal and an a-link pseudo-random code, R (τ) is a known ideal pseudo-random code normalized autocorrelation function, and since c ₁ (t) and c ₂ (t) are uncorrelated, the convolutions of the two are almost 0 and negligible. R' (τ) is the result of the convolution and linear superposition of the PN code ideal autocorrelation function R (t) and the channel impulse response h _i (t).

Then, the phase τ of the local pseudo-random code of the link B is gradually shifted as a start point of the cyclic convolution, the repeated and sampled data is subjected to autocorrelation processing, and the convolution result R' (i) and the corresponding shift position τ _i of each time are recorded. Alternatively, the different positions of the cached pseudo-random signal sampling data can be selected successively to serve as the start point of the circular convolution, and the sampling data can be circularly used end to end, so that the availability of the completed pseudo-random code period data can be ensured.

In step 1283, a plurality of impulse responses R '(τ) of the autocorrelation function R (τ) of the channel in which the B link is interfered with the a link are obtained by the autocorrelation process of the B link in step 1282, and N pieces of data having the largest value of the cyclic convolution result R' (i) are selected. It is readily understood that the main signal corresponds to the maximum value of R' (i). Specifically, in step 1284, N data having the largest peak of the most forward peak of R' (τ) is selected for analysis.

In step 1285, peak R ' (i) corresponding to each delay τ _i is obtained through different delays and corresponding peak comparison analysis, relative delay td _i＝|τ_i-τ_j l is calculated through two peaks R ' (i) and R ' (j), and finally, relative delays of all reflection points of the a link are obtained, and τ _i、τ_j is the positions (expressed in terms of time meaning) of 2 different reflection points.

In step 1286, the calculated relative delay td _i of the link a is used to analyze the mismatch between the calculated relative delay and the relative delay in the database, i.e. the position of the abnormal reflection point of the link a, in combination with the link topology length and the corresponding relative delay data in the database recorded in step 1210.

Then, go back to step 1240 to continue to determine whether all the test frequency points have been tested. If all the test frequency points are used up, step 1242 is entered to configure the transceiving side to be the normal working frequency point and configure the transceiving side to be the normal working mode. Next, in step 1244, the reflection point positions are analyzed by integrating the relative delays td _i of the respective frequency point analysis. Then, in step 1246, the test results are reported and the test is ended.

Different examples of the detection device according to the embodiment of the present disclosure are described below with reference to fig. 14 to 20. It should be understood that the division of the modules or units in these embodiments is illustrative, only one logic function is divided, and there may be another division manner in actual implementation, and in addition, each functional unit in the disclosed embodiments may be integrated in one unit, or may exist alone physically, or two or more units may be integrated into one unit. The integrated units may be implemented in hardware or in software functional units.

Fig. 14 illustrates a schematic block diagram of a detection apparatus 1400 according to some embodiments of the present disclosure. The detection device 1400 includes a board 1/chip 1, a board 2/chip 2, a high-speed connector/high-speed cable, and a diagnostic test control and processing module 3. The single board 1/chip 1 comprises a diagnosis test module 1 and a serdes 1 module, and the single board 2/chip 2 comprises a diagnosis test module 2 and a serdes 2 module.

The diagnostic test module 1 is mainly used for the diagnostic test of the communication link between the high-speed serdes of the single board 1/chip 1 and the high-speed serdes of the single board 2/chip 2, and is mainly responsible for the initiation of test signals, such as the transmission of pseudo random codes.

The diagnostic test module 2 is also mainly used for the diagnostic test of the communication link between the high-speed serdes of the single board 1/chip 1 and the high-speed serdes of the single board 2/chip 2, and is mainly responsible for receiving test signals, sampling at high speed and caching.

The diagnostic test control and processing module 3 is mainly responsible for controlling the diagnostic test module 1 and the diagnostic test module 2, such as starting a test, selecting a frequency point, controlling data acquisition, acquiring data of the diagnostic test module 2 for convolution processing, calculating relative delay according to a convolution result, and calculating a reflection point position according to trace length matching.

Fig. 15 shows a schematic block diagram of a detection apparatus 1500 according to further embodiments of the present disclosure. The detection apparatus 1500 includes a board 1/chip 1, a board 2/chip 2, a high-speed connector/high-speed cable, a clock support system, a processor, and a bus. The single board 1/chip 1 comprises a diagnostic test generator, a serdes 1 module and a clock module 1, and the single board 2/chip 2 comprises a diagnostic test receiver, a serdes 2 module and a clock module 2.

The diagnostic test generator may generate a pseudo-random encoded signal for link testing with a period P of the pseudo-random encoded signal greater than 2 times a high speed communication link round trip time of flight T, t= 2*L/v, where L is the high speed communication link total length and v is the wave velocity.

The diagnostic test receiver may sample and buffer the link test signal. Synchronous sampling, such as equalization convergence at the receiving side and CDR locking, can be adopted for acquisition, or asynchronous sampling can be adopted for direct high-speed oversampling, and the data duration of all the sampling needs to be greater than 1 PN pseudo-random code period length and is cached in a RAM. In synchronous sampling mode, if the link supports NRZ (PAM 2) coding, the ADC module may be implemented by an ADC of the decision feedback equalizer (Decision feedback equalizer, DFE) itself, in test mode, a high-order high-resolution ADC is used, and in normal mode, the high-order high-resolution ADC part circuit may be turned off, changing it to a DFE 1bit ADC, to achieve energy saving. If the link supports PAM4 coding, the ADC may directly implement sampling by the high-order high-precision ADC of the DFE itself, and the test mode and the normal mode may share the same high-speed high-order high-resolution ADC. In the asynchronous sampling mode, the high-speed high-resolution ADC may be directly employed for oversampling. In some embodiments, oversampling means sampling at a sampling frequency that is more than twice the signal rate.

The clock module 1 may generate the clock signals required to support the diagnostic test generator, serdes 1, to perform the test.

The clock module 2 may generate the clock signals required to support the diagnostic test receiver, serdes 2, to perform the test.

The clock support system may generate the clocks required to support the diagnostic test generator, the diagnostic test receiver, the clock module 1, the clock module 2, and the operation of the communication link transceiver terminals, etc.

The processor plays a role in controlling and managing, and realizes the configuration, control, data processing and the like of the modules. For example, clock signal configuration, test coding signal configuration, judging whether the equalization at the receiving side is converged, judging whether the CDR is locked, controlling acquisition of received data, reading the acquired data, performing convolution processing on the acquired data, calculating the relative delay td _i of each reflection point based on the convolution result, performing comprehensive analysis based on the relative delay td _i of each reflection point and the reflection flight time of each passive node of the stored link, calculating the influence of reflection on the communication link based on the convolution result, determining the position of reflection, and the like.

Fig. 16 shows a schematic block diagram of a detection device 1600 according to further embodiments of the present disclosure. Compared with fig. 15, fig. 16 mainly differs in that the diagnostic test generator, the diagnostic test receiver, the clock module 1 and the clock module 2 are implemented by specific modules.

In particular, the diagnostic test generator is embodied as a PN code generator module. The diagnostic test receiver is embodied as a high-speed ADC module and a feed-forward equalizer (Forward feedback equalizer, FFE)/DFE module. The clock module 1 is embodied as a TX code rate selection module and a wideband voltage controlled oscillator (Voltage controlled oscillator, VCO)/phase locked loop (Phase locked loop, PLL) module. The wideband VCO module supports a plurality of resonance frequency points, and the corresponding resonance frequency points are selected and configured through the TX code rate selection module. The clock module 2 is embodied as an RX code rate selection module, a wideband VCO/PLL and a CDR module. The broadband VCO supports a plurality of resonance frequency points, the RX code rate selection module is used for selecting and configuring the corresponding resonance frequency points, and the CDR module is used for finishing the functions of signal data equalization and clock recovery. The clock support system is specifically realized as a clock synthesizer, and the receiving and transmitting sides respectively output two paths of working reference clocks by the clock synthesizer, wherein the two paths of working reference clocks comprise a main reference clock and a standby reference clock. The main reference clock is used under normal operation, and the frequency points of the main reference clock can be independently configured. The standby reference clock is used in a communication link diagnosis test mode, the corresponding problem link serdes module can be selectively configured, and frequency points of the standby reference clock can be independently configured, so that the serdes can select different frequency points for testing.

Fig. 17 shows a schematic block diagram of a detection apparatus 1700 according to further embodiments of the present disclosure. Compared to fig. 16, fig. 17 differs mainly in that in the synchronous sampling mode, the ADC is implemented by a high-speed high-resolution ADC independent of the DFE. In a normal mode, the high-speed high-resolution ADC can be used for balanced back eye diagram data acquisition and real-time acquisition and detection of a link eye diagram. In test mode, the high-speed high-resolution ADC is used for sampling and buffering of link signals.

Fig. 18 shows a schematic block diagram of a detection apparatus 1800 according to further embodiments of the present disclosure. Compared to fig. 16, fig. 18 differs mainly in that the interference of an abnormal link to an adjacent link is used to indirectly locate the reflection position. Fig. 18 illustrates that 2 high-speed links a and B are interfered, the high-speed connector is not matched with the high-speed link a, the high-speed connector is reflected by the high-speed link a for 1 time, interference is generated on an adjacent link B, meanwhile, reflection is generated again by 1 time of reflected echo generated by the high-speed connector, 2 times of interference is generated on the adjacent link B, and finally, multiple interference is generated on the link B by the high-speed connector due to the reflection of the high-speed connector.

The diagnostic test generator may generate a pseudo-random encoded signal for the a/B link test with a period P of the pseudo-random encoded signal greater than 2 times the high speed communication link round trip time of flight T, t= 2*L/v, where L is the high speed communication link total length and v is the wave velocity. A. The pseudo-random code of the B link is uncorrelated, and the pseudo-random code signal of the A, B link is uncorrelated after A, B high-speed link delay. The diagnostic test generator may be embodied as a PN code generator module.

The diagnostic test receiver may sample and buffer the B-link test signal. Synchronous sampling can be adopted, such as equalization convergence of a receiving side of a B link and CDR locking, then acquisition is carried out, or asynchronous sampling can be adopted to directly carry out over-sampling on the B link, and the data duration of all the sampling needs to be greater than 1 PN pseudo-random code period length and is cached in a RAM. In synchronous sampling mode, if the link supports NRZ (PAM 2) coding, the ADC module can be realized by the ADC of the DFE itself, in test mode, the high-order high-resolution ADC is used, and in normal mode, the high-order high-resolution ADC part circuit can be turned off to be changed into the DFE 1bit ADC, so as to realize energy saving. If the link supports PAM4 coding, the ADC may directly implement sampling by the high-order high-precision ADC of the DFE itself, and the test mode and the normal mode may share the same high-speed high-order high-resolution ADC. In the asynchronous sampling mode, the high-speed high-resolution ADC may be directly employed for oversampling. The diagnostic test receiver may be embodied as a high-speed ADC module and an FFE/DFE module. In some embodiments, oversampling means sampling at a sampling frequency that is more than twice the signal rate.

The clock module 1 may generate the clock signals required to support the diagnostic test generator, serdes 1, to perform the test. The clock module 1 may be embodied as a TX code rate selection module and a wideband VCO/PLL module. The wideband VCO module supports a plurality of resonance frequency points, and the corresponding resonance frequency points are selected and configured through the TX code rate selection module.

The clock module 2 may generate the clock signals required to support the diagnostic test receiver, serdes 2, to perform the test. The clock module 2 may be embodied as an RX code rate selection module, a wideband VCO/PLL and a CDR module. The broadband VCO supports a plurality of resonance frequency points, the RX code rate selection module is used for selecting and configuring the corresponding resonance frequency points, and the CDR module is used for finishing the functions of signal data equalization and clock recovery.

The clock support system may generate the clocks required to support the diagnostic test generator, the diagnostic test receiver, the clock module 1, the clock module 2, and the operation of the communication link transceiver terminals, etc. The clock support system can be specifically realized as a clock synthesizer, and the receiving and transmitting sides respectively output two paths of working reference clocks by the clock synthesizer, wherein the two paths of working reference clocks comprise a main reference clock and a standby reference clock. The main reference clock is used under normal operation, and the frequency points of the main reference clock can be independently configured. The standby reference clock is used in a communication link diagnosis test mode, the corresponding problem link serdes module can be selectively configured, and frequency points of the standby reference clock can be independently configured, so that the serdes can select different frequency points for testing.

The processor plays a role in controlling and managing, and realizes the configuration, control, data processing and the like of the modules. For example, clock signal configuration, test coding signal configuration, judging whether equalization at the receiving side is converged, judging whether CDR is locked, controlling acquisition of B-link received data, reading of B-link acquired data, convolution processing of the acquired B-link data and a-link pseudo-random coding, calculation of relative delay td _i of each reflection point of the a-link based on convolution results, comprehensive analysis based on relative delay td _i of each reflection point of the a-link and reflection flight time of each stored passive node of the a-link, and the like, and determination of reflection positions.

Fig. 19 shows a schematic block diagram of a detection apparatus 1900 according to further embodiments of the disclosure. Compared to fig. 18, fig. 19 differs mainly in that in the synchronous sampling mode, the ADC is implemented by a high-speed high-resolution ADC independent of the DFE. In a normal mode, the high-speed high-resolution ADC can be used for balanced back eye diagram data acquisition and real-time acquisition and detection of a link eye diagram. In test mode, the high-speed high-resolution ADC is used for sampling and buffering of link signals.

Fig. 20 shows a simplified block diagram of a detection device 2000 suitable for implementing embodiments of the present disclosure. The apparatus 2000 may be implemented in software, hardware or a combination of both. The apparatus 2000 includes a triggering unit 2010, a first determining unit 2020, a processing unit 2030, and a second determining unit 2040. The triggering unit 2010 is configured to cause the first device of the detection apparatus to send a test signal to the second device of the detection apparatus via the communication link. The first determining unit 2020 is configured to cause the second device to determine a received signal associated with the test signal. The processing unit 2030 is configured to perform autocorrelation processing on the received signal and the test signal generated at the second device. The second determination unit 2040 is configured to determine an abnormal position in the communication link based on a processing result of the autocorrelation processing.

In some embodiments, the processing unit 2030 may be further configured to: performing sampling on a received signal via a communication link to obtain a sampled signal; and performing an autocorrelation process on the sampled signal and the test signal.

In some embodiments, where the communication link is a first communication link, the test signal is a first test signal, the triggering unit 2010 may be further configured to: the first device is caused to transmit a second test signal to the second device via a second communication link adjacent to the first communication link while the first test signal is transmitted, the second test signal being uncorrelated with the first test signal.

In some embodiments, the processing unit 2030 may be further configured to: performing sampling on the received signal via the second communication link to obtain a sampled signal; and performing an autocorrelation process on the sampled signal and the first test signal.

In some embodiments, the apparatus 2000 may further include a storage unit configured to: the method further includes storing a line length and a corresponding delay between passive nodes of one or more communication links between the first device and the second device, the one or more communication links including the communication link, prior to transmitting the test signal.

In some embodiments, the second determining unit 2040 may be further configured to: determining a relative delay between a plurality of reflection points in the communication link based on a processing result of the autocorrelation process; and determining an anomaly location in the communication link based on the relative delays between the plurality of reflection points and the line lengths and corresponding delays between the plurality of passive nodes of the stored communication link.

In some embodiments, the trigger unit 2010 may be further configured to: before sending the test signal, causing the first device to send a handshake signal to the second device via the communication link; if the second device successfully parses the handshake signal, the first device is caused to send a test signal. The second determination unit 2040 may also be configured to: if the second device does not successfully resolve the handshake signal, it is determined that the communication link is open or shorted.

In some embodiments, the processing unit 2030 may be further configured to: performing equalization processing and clock data recovery processing on the received signal to obtain a processed received signal; and performing high-speed high-resolution analog-to-digital converter ADC sampling on the processed received signal.

In some embodiments, the processing unit 2030 may be further configured to: high-speed oversampling is performed on the received signal. In some embodiments, oversampling means sampling at a sampling frequency that is more than twice the signal rate.

In some embodiments, the test signal is one of a plurality of test signals at a plurality of test frequencies, the processing result is one of a plurality of processing results corresponding to the plurality of test frequencies, and the second determining unit 2040 may be further configured to: an anomaly location is determined based on the plurality of processing results.

In some embodiments, the second determining unit 2040 may be further configured to: determining a ratio of reflected noise at a plurality of reflection points in the communication link to a main signal of the received signal based on a processing result of the autocorrelation processing; and determining, based on the ratio, that the anomaly location results in a failure of the communication link.

Fig. 21 shows a schematic block diagram of an example device 2100 that may be used to implement embodiments of the present disclosure.

As shown, the device 2100 includes a central processing unit (Central Processing Unit, CPU) 2101, a Read-Only Memory (ROM) 2102, and a random access Memory (Random Access Memory, RAM) 2103. The CPU 2101 may perform various appropriate actions and processes in accordance with computer program instructions stored in the RAM 2102 and/or the RAM 2103 or computer program instructions loaded from the storage unit 2108 into the ROM 2102 and/or the RAM 2103. Various programs and data required for operation of the device 2100 may also be stored in the ROM 2102 and/or RAM 2103. The CPU 2101 and ROM 2102 and/or RAM 2103 are connected to each other via bus 2104. An Input/Output (I/O) interface 2105 is also connected to bus 2104.

Various components in device 2100 are connected to I/O interface 2105, including: an input unit 2106 such as a keyboard, mouse, etc.; an output unit 2107 such as various types of displays, speakers, and the like; a storage unit 2108 such as a magnetic disk, an optical disk, or the like; and a communication unit 2109, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 2109 allows the device 2100 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks.

The CPU 2101 may be a variety of general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples that may be implemented include, but are not limited to, a graphics processing unit (Graphics Processing Unit, GPU), various dedicated artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DIGITAL SIGNAL processors, DSPs), and any suitable Processor, controller, microcontroller, etc., which may accordingly be referred to as a computing unit. The CPU 2101 performs the respective methods and processes described above. For example, in some embodiments, the various processes described above may be implemented as a computer software program tangibly embodied on a computer-readable medium, such as storage unit 2108. In some embodiments, some or all of the computer programs may be loaded and/or installed onto device 2100 via ROM 2102 and/or RAM 2103 and/or communication unit 2109. When the computer program is loaded into the ROM 2102 and/or RAM 2103 and executed by the CPU 2101, one or more steps of the processes described above may be performed. Alternatively, in other embodiments, CPU 2101 may be configured to perform the various processes described above in any other suitable manner (e.g., by means of firmware).

By way of example, device 2100 in fig. 21 may be implemented as a computing device, or as a chip or chip system in a computing device, as embodiments of the disclosure are not limited in this regard.

Embodiments of the present disclosure also provide a chip that may include an input interface, an output interface, and a processing circuit. In the embodiment of the disclosure, the interaction of the signaling or data can be completed by the input interface and the output interface, and the generation and the processing of the signaling or data information can be completed by the processing circuit.

Embodiments of the present disclosure also provide a chip system including a processor for supporting a computing device to implement the functions referred to in any of the above embodiments. In one possible design, the chip system may further include a memory for storing necessary program instructions and data that, when executed by the processor, cause the apparatus on which the chip system is installed to implement the method referred to in any of the embodiments above. The chip system may be formed from one or more chips, and may include chips and other discrete devices, for example.

Embodiments of the present disclosure also provide a processor for coupling with a memory, the memory storing instructions that, when executed by the processor, cause the processor to perform the methods and functions referred to in any of the embodiments above.

Embodiments of the present disclosure also provide a computer program product containing instructions which, when run on a computer, cause the computer to perform the methods and functions involved in any of the embodiments described above.

Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, cause the processor to perform the methods and functions referred to in any of the embodiments above.

In general, the various embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor or other computing device. While various aspects of the embodiments of the disclosure are illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product comprises computer executable instructions, such as instructions included in program modules, being executed in a device on a real or virtual processor of a target to perform the processes/methods as described above with reference to the figures. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or split between program modules as desired. Machine-executable instructions for program modules may be executed within local or distributed devices. In distributed devices, program modules may be located in both local and remote memory storage media.

Computer program code for carrying out methods of the present disclosure may be written in one or more programming languages. These computer program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the computer or other programmable data processing apparatus, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.

In the context of this disclosure, computer program code or related data may be carried by any suitable carrier to enable an apparatus, device, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like. Examples of signals may include electrical, optical, radio, acoustical or other form of propagated signals, such as carrier waves, infrared signals, etc.

A computer readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a computer-readable storage medium include an electrical connection with one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-Only Memory (ROM), an erasable programmable read-Only Memory (EPROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

Furthermore, although the operations of the methods of the present disclosure are depicted in the drawings in a particular order, this is not required to or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Rather, the steps depicted in the flowcharts may change the order of execution. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform. It should also be noted that features and functions of two or more devices according to the present disclosure may be embodied in one device. Conversely, the features and functions of one device described above may be further divided into multiple devices to be embodied.

The foregoing has described implementations of the present disclosure, and the foregoing description is exemplary, not exhaustive, and not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.

Claims (24)

1. A method of detection comprising:

the electronic device causes a first device of the electronic device to transmit a test signal to a second device of the electronic device via a communication link;

The electronic device causes the second device to determine a received signal associated with the test signal;

the electronic device performs an autocorrelation process on the received signal and the test signal generated at the second device; and

The electronic device determines an abnormal position in the communication link based on a processing result of the autocorrelation processing.

2. The method of claim 1, wherein performing the autocorrelation process comprises:

The electronic device performing sampling of the received signal via the communication link to obtain a sampled signal; and

The electronic device performs the autocorrelation process on the sampled signal and the test signal.

3. The method of claim 1, wherein the communication link is a first communication link, the test signal is a first test signal, the method further comprising:

The electronic device causes the first device to transmit a second test signal to the second device via a second communication link adjacent to the first communication link while the first test signal is transmitted, the second test signal being uncorrelated with the first test signal.

4. The method of claim 3, wherein performing the autocorrelation process comprises:

the electronic device performing sampling of the received signal via the second communication link to obtain a sampled signal; and

The electronic device performs the autocorrelation process on the sampled signal and the first test signal.

5. The method of any of claims 1-4, further comprising:

The electronic device stores a line length and a corresponding delay between passive nodes of one or more communication links between the first device and the second device, the one or more communication links including the communication link, prior to transmitting the test signal.

6. The method of any of claims 1-4, wherein determining the anomaly location comprises:

based on the processing results of the autocorrelation process, the electronic device determines a relative delay between a plurality of reflection points in the communication link; and

Based on the relative delays between the plurality of reflection points and the stored line lengths and corresponding delays between the plurality of passive nodes of the communication link, the electronic device determines the anomaly location in the communication link.

7. The method of any of claims 1-4, further comprising:

Before sending the test signal, the electronic device causes the first device to send a handshake signal to the second device via the communication link;

if the second device successfully analyzes the handshake signal, the electronic equipment enables the first device to send the test signal; and

If the second device does not successfully resolve the handshake signal, the electronic device determines that the communication link is open or shorted.

8. The method of claim 2 or 4, wherein performing the sampling comprises:

The electronic equipment performs equalization processing and clock data recovery processing on the received signal to obtain a processed received signal; and

The electronic device performs high-speed high-resolution analog-to-digital converter (ADC) sampling on the processed received signal.

9. The method of claim 2 or 4, wherein performing the sampling comprises:

the electronic device performs high-speed oversampling on the received signal.

10. The method of any of claims 1-4, wherein the test signal is one of a plurality of test signals at a plurality of test frequencies, the processing result is one of a plurality of processing results corresponding to the plurality of test frequencies, and determining the anomaly location in the communication link comprises:

the electronic device determines the abnormality location based on the plurality of processing results.

11. The method of claim 1 or 2, further comprising:

Based on the results of the autocorrelation process, the electronic device determines ratios of reflected noise at a plurality of reflection points in the communication link to a main signal of the received signal; and

Based on the ratio, the electronic device determines that the anomaly location results in a failure of the communication link.

12. A detection apparatus, comprising:

A trigger unit configured to cause a first device of the detection apparatus to transmit a test signal to a second device of the detection apparatus via a communication link;

A first determining unit configured to cause the second device to determine a received signal associated with the test signal;

a processing unit configured to perform autocorrelation processing on the received signal and the test signal generated at the second device; and

And a second determination unit configured to determine an abnormal position in the communication link based on a processing result of the autocorrelation processing.

13. The apparatus of claim 12, wherein the processing unit is further configured to:

performing sampling on the received signal via the communication link to obtain a sampled signal; and

The autocorrelation process is performed on the sampled signal and the test signal.

14. The apparatus of claim 12, wherein the communication link is a first communication link, the test signal is a first test signal, the trigger unit is further configured to:

The method includes causing the first device to transmit a second test signal to the second device via a second communication link adjacent to the first communication link while the first test signal is transmitted, the second test signal being uncorrelated with the first test signal.

15. The apparatus of claim 14, wherein the processing unit is further configured to:

Performing sampling on the received signal via the second communication link to obtain a sampled signal; and

The autocorrelation process is performed on the sampled signal and the first test signal.

16. The apparatus of any of claims 12-15, further comprising:

A storage unit configured to store, prior to transmitting the test signal, a line length and a corresponding delay between passive nodes of one or more communication links between the first device and the second device, the one or more communication links comprising the communication link.

17. The apparatus according to any of claims 12-15, wherein the second determination unit is further configured to:

Determining a relative delay between a plurality of reflection points in the communication link based on a processing result of the autocorrelation process; and

The anomaly location in the communication link is determined based on the relative delay between the plurality of reflection points and the stored line length and corresponding delay between the plurality of passive nodes of the communication link.

18. The device of any one of claims 12-15, wherein

The trigger unit is further configured to: causing the first device to send handshake signals to the second device via the communication link prior to sending the test signals;

If the second device successfully analyzes the handshake signal, the first device sends the test signal; and

The second determination unit is further configured to: if the second device does not successfully resolve the handshake signal, it is determined that the communication link is open or shorted.

19. The apparatus of claim 13 or 15, wherein the processing unit is further configured to:

performing equalization processing and clock data recovery processing on the received signal to obtain a processed received signal; and

And performing high-speed high-resolution analog-to-digital converter (ADC) sampling on the processed received signal.

20. The apparatus of claim 13 or 15, wherein the processing unit is further configured to:

high-speed oversampling is performed on the received signal.

21. The apparatus according to any of claims 12-15, wherein the test signal is one of a plurality of test signals at a plurality of test frequencies, the processing result is one of a plurality of processing results corresponding to the plurality of test frequencies, and the second determination unit is further configured to:

the anomaly location is determined based on the plurality of processing results.

22. The apparatus according to claim 12 or 13, wherein the second determination unit is further configured to:

Determining a ratio of reflected noise at a plurality of reflection points in the communication link to a main signal of the received signal based on a processing result of the autocorrelation processing; and

Based on the ratio, determining that the anomaly location results in a failure of the communication link.

23. An electronic device, comprising:

At least one processor;

At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, which when executed by the at least one processor, cause the electronic device to perform the method of any one of claims 1-11.

24. A chip comprising processing circuitry configured to perform the method of any one of claims 1 to 11.