CN118353247A - Half-bridge driver circuit, related integrated circuit, half-bridge switching circuit and method - Google Patents

Abstract

The present disclosure provides a half-bridge driver circuit. The circuit includes a detector circuit that generates a signal indicating whether the floating reference voltage is greater than the second supply voltage. The detector circuit includes a first circuit, a second circuit, and a combinational logic circuit. A first comparator circuit of the first circuit monitors a voltage drop at the resistor and sets the first control signal to a first logic level when the monitored voltage drop is less than a first threshold. A second comparator circuit of the second circuit monitors the current provided by the output transistor of the current mirror and sets the second control signal to the first logic level when the monitored current is greater than a second threshold. The combinational logic circuit asserts the signal when the first control signal has a corresponding first logic level or the second control signal has a corresponding first logic level.

Description

Half-bridge driver circuit, related integrated circuit, half-bridge switching circuit and method

Technical Field

Various embodiments of the present disclosure relate to half-bridge driver circuits.

Background

High Voltage (HV) half-bridge switching circuits are well known in the art and may be used in a variety of applications such as motor driver devices, electronic ballasts for fluorescent lamps, and other power supply devices.

Fig. 1 shows an example of a half-bridge switching circuit comprising a half-bridge driver circuit with a conventional high-side bootstrap architecture.

In the example considered, the half-bridge switching circuit 10 comprises a high-side electronic switch HS and a low-side electronic switch LS. In particular, these electronic switches HS and LS form a half bridge, i.e. (the current path of) the high-side electronic switch HS is connected between the switching node 102a and the first terminal 108, and (the current path of) the low-side electronic switch LS is connected between the switching node 102a and the second terminal 102 b. For example, terminal 108 may be connected to a (positive) supply voltage V _BUS and terminal 102b may be connected to a reference voltage, such as ground GND. For example, the supply voltage V _BUS is typically a DC voltage, e.g. provided by a battery or obtained from an AC voltage (such as mains) via a rectifier circuit (such as a bridge rectifier), which optionally also comprises a filter capacitor. Thus, the value of the DC voltage V _BUS may be chosen within a wide range of values, for example between 20V and 1kV, such as between 90V and 200V.

Thus, by driving the control terminals of the high-side electronic switch HS and the low-side electronic switch LS, the switching node 102a, i.e., an intermediate node between the high-side electronic switch HS and the low-side electronic switch LS, can be selectively connected to the power supply voltage V _BUS or the reference voltage/ground GND. For example, in general, the voltage V _OUT between terminal 102a and terminal 102b is used to drive a load L, such as an inductive load. Those skilled in the art will appreciate that the connection of the load L is only one example. For example, the load L may also be connected in parallel with the high-side electronic switch HS, or two half-bridge circuits may also be used to drive the load with a full-bridge arrangement.

In many applications, electronic switches HS and LS are implemented using power transistors, such as Field Effect Transistors (FETs), such as n-channel FETs. For example, transistors HS and LS are typically implemented using Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or Insulated Gate Bipolar Transistors (IGBTs). Further, recently, gallium nitride (GaN) power transistors are increasingly used in such half-bridges to replace conventional power transistors. For example, gaN power transistors may provide lower gate capacitance and higher switching speeds. Note that the high-side transistor HS and the low-side transistor LS may comprise respective drain-body diodes as schematically shown in fig. 1.

For example, when an n-channel FET is used, the drain terminal of the high-side transistor HS is connected (e.g., directly) to the terminal 108 and the source terminal of the high-side transistor HS is connected (e.g., directly) to the terminal 102a. Similarly, the drain terminal of the low-side transistor LS is connected (e.g., directly) to terminal 102a and the source terminal of the low-side transistor LS is connected (e.g., directly) to terminal 102b.

Thus, IN general, the half-bridge circuit 10 further comprises a half-bridge driver circuit HBD configured to drive the gate terminal of the high-side transistor HS IN accordance with the first control signal IN _HS and to drive the gate terminal of the low-side transistor LS IN accordance with the second control signal IN _LS.

For example, to drive the gate terminals 120a and 120b, the half-bridge switching circuit 10 may include two input terminals 100a and 100b configured to receive a DC supply voltage V _CC. In general, the supply voltage V _CC may be provided by any suitable power source PS. For example, the power source PS may be a battery, or the power source PS may be implemented via a voltage source (such as a linear regulator or a switched mode power supply) that receives, for example, a voltage V _BUS at an input. The value of the supply voltage V _CC may be selected from a range of values, for example between 3V and 24V, depending on the particular application. For example, when driving an enhancement mode GaN power transistor, the supply voltage V _CC may be about 5V.

Such driver circuits HBD are well known in the art and are typically provided as Integrated Circuits (ICs). Typically, the half-bridge driver circuit HBD comprises a high-side gate driver circuit 12a providing a drive signal to the gate terminal of the high-side transistor HS at the output terminal 120a, and the half-bridge driver circuit HBD comprises a low-side gate driver circuit 12b providing a drive signal to the gate terminal of the low-side transistor LS at the output terminal 120 b. In general, the integrated circuit of the half-bridge driving circuit HBD may also comprise electronic switches HS and/or LS, and/or a voltage source implementing a power supply PS.

For example, to close an n-channel FET, the gate-source voltage, i.e., the voltage at terminal 120b relative to terminal 102b, should exceed the threshold voltage of the n-channel FET. For example, for this purpose, the low-side gate driver circuit 12b may be configured to open the low-side electronic switch LS by connecting the terminal 120b to the source terminal of the low-side transistor (i.e., terminal 102 b) and to close the low-side electronic switch LS by connecting the terminal 120b to a positive supply voltage (e.g., voltage V _CC received via terminals 100a and 100 b), wherein the low-side gate driver circuit 12b is configured to close the low-side switch LS when the signal IN _LS is asserted (e.g., set high) and to open the low-side switch LS when the signal IN _LS is de-asserted (e.g., set low).

Similarly, the high-side gate driver circuit 12A may be configured to open the high-side electronic switch HS by connecting the terminal 120a to the source terminal of the high-side transistor HS (i.e., terminal 102A) and to close the high-side electronic switch HS by connecting the terminal 120a to the terminal 104 to which the positive supply voltage V _BOOT is applied, wherein the high-side gate driver circuit 12A is configured to close the high-side switch HS when the signal IN _HS is asserted (e.g., set high) and to open the high-side switch HS when the signal IN _HS is de-asserted (e.g., set low).

In general, the driver circuits 12a and/or 12b may also implement slew rate control in which the gate terminals 120a and 120b are not directly connected to the voltages described above, but the respective gate-source capacitances (and possibly other capacitances connected between the respective gates and sources) are charged and discharged via the voltages described above. For example, the gate terminal 120b may be charged via a current from the supply voltage V _CC or discharged via a current to the reference voltage at terminal 102 b. Similarly, gate terminal 120a may be charged via a current from supply voltage V _BOOT or discharged via a current flowing to terminal 102 a.

Thus, the switching node 102a may:

Is connected to a voltage V _BUS when the high-side switch HS is closed and the low-side switch LS is open;

when the high-side switch HS is open and the low-side switch LS is closed, it is connected to the reference voltage/ground GND;

When the high-side switch HS and the low-side switch LS are turned off, they are placed in a high-impedance state.

Thus, the high-side driver 12a is typically powered with different supply voltages, which are typically implemented within the floating segment FS (V _BOOT -V _OUT) between the nodes 104 and 102 a. For this reason, the high-side driver 12a typically has (e.g., includes) an associated level shifter, the level shifter 14 is configured to generate a level shifted version of the signal IN _HS, and the high-side driver 12a generates a gate voltage at the terminal 120a based on the level shifted version of the signal IN _HS, while the low-side driver 12b may directly receive the signal IN _LS. Possible implementations of such level shifters are disclosed, for example, in U.S. patent application No. US2022/0006450 A1, which is incorporated herein by reference.

Fig. 1 also shows a conventional solution for generating the supply voltage V _BOOT at the terminal 104. Specifically, in the example considered, the bootstrap architecture is used to generate a DC voltage supply V _CB between nodes 104 and 102a, wherein the DC voltage supply V _CB is floating relative to the DC low voltage V _CC, wherein V _BOOT＝V_CB+V_OUT, thereby providing the floating section FS of the half-bridge switching circuit 10. Thus, the DC voltage supply V _CB may be derived from the DC low voltage supply V _CC, for example by providing a high voltage diode DB, the anode of which is connected to the positive terminal 100a of the DC low voltage supply V _CC and the cathode is connected to the floating supply voltage node 104.

As illustrated in fig. 1, a bootstrap capacitor C _B (e.g., a capacitor mounted external to the integrated circuit of the half-bridge driver circuit HBD) provided between the (positive) output terminal 102a and the floating supply voltage node 104 may be configured to store charge (during a bootstrap "recharge" phase) to provide a DC voltage supply V _CB to power the high-side gate driver circuit 12a (during the bootstrap "power" phase).

Essentially, when the low-side electronic switch LS is closed (bootstrap recharging phase), the diode DB is closed and the capacitor C _B is charged close to the voltage V _CC (ignoring the voltage drop at the diode DB), i.e. V _OUT＝0V,V_BOOT＝V_CB＝V_CC. Conversely, when the low-side electronic switch LS is turned off, diode DB is turned off and node 104 is at voltage V _BOOT, voltage V _BOOT corresponds to the sum of voltage V _CB and voltage V _OUT at switching node 102a, i.e., V _BOOT＝V_OUT+V_CB.

Thus, voltage V _CB floats with voltage V _OUT and can be used to power driver circuit 12a so that high-side electronic switch HS can be closed. In this aspect, once the high-side electronic switch HS is closed (bootstrap phase), the node 102a is set to the voltage V _BUS, i.e., V _BOOT＝V_BUS+V_CB. Accordingly, the capacitor C _B should be selected to store enough energy during the recharge phase to power the high-side driver 12a during the bootstrap phase. For example, in the case of an enhancement mode GaN power transistor, the voltage V _CB may be between 4V and 6V.

Document US2022/0006450 A1 also discloses in this respect an arrangement for improving the recharging of the bootstrap capacitor C _B, for example to keep the voltage V _CB below the upper threshold V _TH、H. Preferably, the voltage V _CB should also be greater than the lower threshold V _TH、L. For example, in this manner, the voltage V _CB may be maintained within a range of values (e.g., 4V to 6V). For example, a gate voltage higher than the above range may stress the high-side transistor HS, and a gate voltage lower than the above range may lower the system efficiency.

For example, fig. 2 shows an example of a half-bridge switching circuit 10' according to document US2022/0006450 A1.

Specifically, in comparison to fig. 1, a current limiter circuit is added that controls the charging current used to charge the capacitor C _B. For example, the current limiter circuit may include an electronic switch Q1', such as a transistor with a drain-body diode D1', and a corresponding control circuit 62. Furthermore, the diode DB is preferably replaced by an active diode circuit, for example comprising an electronic switch Q3, such as a transistor with a drain-body diode D3, and a corresponding control circuit 60.

Specifically, the current limiter circuit is located in the floating section FS, and the control circuit 62 may be powered and driven in the floating section FS of the half-bridge driving circuit HBD.

As described above, capacitor C _B should charge during the bootstrap recharge phase (when electronic switch HS is open and electronic switch LS is closed), and capacitor C _B should power driver circuit 12a (and possibly other circuits in floating section FS) during the bootstrap power supply phase (at least when electronic switch HS is closed and electronic switch LS is open). Specifically, as previously described, during the recharging phase, the voltage V _BOOT at the floating supply voltage node 104 is typically lower than the voltage V _CC, and the current flowing through the bootstrap diode (DB or D3 and Q3) and the current limiter (e.g., Q1') may charge the bootstrap capacitor C _B. Thus, the value reached by bootstrap voltage V _CB during the recharging phase is related to the amount of current flowing from node 100a through low-side transistor LS during the recharging phase.

As discussed in more detail in document US2022/0006450 A1, the following may occur:

i) If the current recirculation on the low-side transistor LS is negligible, the bootstrap voltage V _CB may rise poorly; in this case, the control circuit 60 may turn on the switch Q3 to increase the current so as to obtain a higher final value of the bootstrap voltage V _CB at the end of the recharging phase; and

Ii) in case of current recirculation on the low-side transistor LS (in particular at high currents), the bootstrap voltage V _CB will exceed the upper threshold V _TH、H (for example equal to 6V); in this case, when the bootstrap voltage V _CB reaches the desired/requested value V _TH、H (e.g., equal to 5.4V), the control circuit 62 may turn off the current limiter circuit (e.g., transistor Q1').

In the example considered, the level shifter may thus be powered by a voltage V _BOOT (node 104) or a voltage VS, preferably at an intermediate node 106 between the diode and the current limiter. In fact, the voltage V _BOOT at node 104 may be lower than the V _CC voltage. Thus, by using diode D3 (and similar DB) of transistor Q3 and diode D1 'of transistor Q1' arranged in a "back-to-back" configuration, voltage V _S is set to the maximum between V _CC and V _BOOT (minus the voltage drop at the respective diodes), such that when electronic switch LS is closed, voltage V _S is approximately set to V _CC, and when electronic switch HS is closed, voltage V _S is approximately set to V _BOOT.

Fig. 3 is a circuit block diagram illustrating a possible implementation of the current limiter circuit and the related control circuit arrangement.

Specifically, as previously described, the current limiter circuit may include a transistor Q1' with a current path connected (e.g., directly connected) between nodes 106 and 104, where transistor Q1' includes a corresponding drain-body diode D1'. In order for the drain-body diode D1 'to be arranged in a desired direction (i.e., the cathode coupled to node 106 and the anode coupled to node 104), the current limiter transistor Q1' may be implemented using a p-channel high voltage FET (such as PMOS) with its source and body terminals connected to node 106. In this exemplary case, the gate-source voltage of the driving transistor Q1' to turn the channel on and off may be lower than the voltage V _S.

Alternatively, the current limiter transistor Q1' may be implemented using an n-channel high voltage FET (such as NMOS) with its source terminal connected to the node 104. In this exemplary case, the gate-source voltage driving such transistors to turn the channel on and off may be higher than the voltage V _BOOT and may be generated by additional circuitry such as a charge pump circuit (not visible in fig. 3).

As illustrated in fig. 4, the voltage V _BOOT at the node 104 may switch from a low value (e.g., near V _CC) during the bootstrap-recharge phase T ₂ to a high value (e.g., much higher than V _CC) during the bootstrap-supply phase T ₁ and then back to the low value. For example, in a typical application, the voltage V _BOOT change at node 104 may occur at a very high rate, e.g., at a rate exceeding 100V/ns (1 ns=10 ^-9 s).

As voltage V _BOOT switches to a high value (into bootstrap phase T1), node 106 can be pulled up to a voltage (almost) equal to V _BOOT by the current flowing through drain-body diode D1 of current limiter transistor Q1' because it is forward biased. During the bootstrap supply phase T ₁, when the voltage V _BOOT is in the high voltage range, the node 106 may still be pulled high by the drain-body diode D1' of the current limiter transistor. Optionally, the control circuit 62 may also close the transistor Q1' during the bootstrap phase T ₁ to reduce the voltage drop between the node 106 and the node 104. This also ensures that the switch Q1' is closed at the beginning of the falling phase (e.g. upon entering the bootstrap recharging phase T ₂).

Furthermore, as voltage V _BOOT switches back to a low value (into bootstrap-recharge phase T ₂), the drain-body diodes D3 and D1' of the active diode circuit and the current limiter circuit may be reverse biased and node 106 may remain floating at a high voltage, potentially overcoming the breakdown voltage of the circuit arrangement connected between node 106 and nodes 104, 102 a. To counteract such an overvoltage event, node 106 may discharge toward node 104 with a current sufficient to limit the voltage difference between nodes 106 and 104 to within the circuit device breakdown voltage. For example, when holding transistor Q1 on at the end of bootstrap phase T ₁, node 106 will discharge through the conductive current path between node 106 and node 104.

Document US2022/0006450 A1 discloses in this respect that an alternative discharge circuit can also be provided, for example if transistor Q1 'is not conducting during phase T ₁ or when the conductivity of transistor Q1' is insufficient to allow the peak current to be high enough to discharge node 106 at a sufficiently fast rate. For example, in fig. 3, the discharge circuit is implemented using a transistor Q2 connected in parallel with a current limiter transistor Q1'. For example, discharge transistor Q2 may be an n-channel FET, such as an NMOS, with its source terminal connected (e.g., directly) to node 104 and its drain terminal connected (e.g., directly) to node 106. The discharge transistor Q2 may include a corresponding drain-body diode D2 connected in parallel with the diode D1'. The control circuit arrangement associated with the gate terminal of the transistor Q2 can be implemented, for example, using the following: a resistive component R4 (e.g., a resistor) connected between (e.g., directly) the source and gate of the transistor Q2, and a capacitive component C4 (e.g., a capacitor) connected between (e.g., directly) the drain and gate of the transistor Q2.

Thus, according to the disclosure of document US2022/0006450 A1, when the voltage VCB is greater than the threshold voltage V _TH, the transistor Q1' is turned off only during part of the bootstrap-recharging phase T ₂. Conversely, transistor Q1' should be turned on as follows:

conducting and during bootstrap supply stage T ₁

When the voltage V _CB is less than the threshold voltage V _TH, it is turned on during part of the bootstrap-recharge phase T ₂.

In particular, to detect the bootstrap recharge phase and the bootstrap supply phase, the control circuitry driving the current limiter transistor Q1' may include a detector circuit DT1 (e.g., a comparator circuit), the detector circuit DT1 being configured to assert the control circuit HBlow, e.g., set the signal HBlow high, in response to determining that the voltage V _OUT is less than the voltage V _CC (which indicates that the half-bridge circuit is in the bootstrap recharge phase T ₂). Conversely, in response to determining that voltage V _OUT is greater than voltage V _CC (which indicates that the half-bridge circuit is in bootstrap phase T ₁), detector circuit DT1 deasserts control circuit HBlow, e.g., sets signal HBlow low. For example, to this end, the comparator circuit DT1 may receive the voltage V _CC at the positive input terminal and the voltage V _OUT at the negative input terminal.

Further, the control circuit may include a second detector circuit DT2, the second detector circuit DT2 being configured to assert the control signal VBOov, e.g., set the signal VBOov high, in response to determining that the voltage V _CB is less than the threshold voltage V _TH (which indicates that the capacitor CB should be charged). Conversely, in response to determining that voltage V _CB is greater than threshold voltage V _TH (which indicates that capacitor C _B has been fully charged), detector circuit DT2 deasserts control signal VBOov, e.g., sets signal VBOov low. For example, in the example considered, the voltage V _CB or its scaled version V _R is applied to the positive input terminal of the comparator DT 2. For example, the scaled voltage V _R may be provided via a voltage divider R1 connected between nodes 104 and 102a (i.e., between voltages V _BOOT and V _OUT). In contrast, a reference voltage V _REF with reference to the voltage V _OUT is applied to the negative input terminal of the comparator DT 2. Specifically, the reference voltage V _REF corresponds to the maximum value of the voltage V _CB or the scaled version V _R. for example, the reference voltage V _REF is generated by a voltage generator VG2 connected between the negative input terminal of the comparator DT2 and the terminal 102 a.

Thus, in the example considered, the control circuit is configured to close the electronic switch Q1 in response to determining that the signal HBlow is deasserted, e.g., set low, or that the signal VBOov is deasserted, e.g., set low. Instead, the control circuit is configured to turn off the electronic switch Q1 in response to determining that the signal HBlow is asserted, e.g., set high, and that the signal VBOov is asserted, e.g., set high.

For example, in the example considered, the control circuit comprises a combinational logic circuit 70, such as an AND gate, for this purpose, the combinational logic circuit 70 being configured to generate the signal Q1off by combining the signals HBlow AND VBOov. For example, in fig. 3, when signal HBlow is asserted and signal VBOov is asserted, signal Q1off is asserted, and therefore switch Q1 should be off when signal Q1off is asserted, e.g., when signal Q1off is set high. Further, in the considered example, the control circuit includes a switching circuit SW configured to drive the gate terminal of the transistor Q1' according to the signal Q1off. For example, the circuit SW may be configured to:

In response to determining that signal Q1off is asserted, for example by connecting the gate terminal of p-channel FET Q1 'to node 106, turning off transistor Q1', and

In response to determining that signal Q1off is deasserted, transistor Q1 'is turned off, for example, by connecting the gate terminal of p-channel FET Q1' to a voltage less than voltage V _S at node 106.

The inventors have observed that the detector circuit DT2 can be implemented using a conventional comparator, since both the input and output terminals are referenced to the same reference voltage (i.e. voltage V _OUT at terminal 102 a), which corresponds to the floating level of the floating section FS.

In contrast, the floating level detector circuit DT1 may require a more complex circuit because the input voltages V _CC and V _OUT are referenced to the reference voltage/ground GND at node 102b, and the output signal HBlow is referenced to the voltage V _OUT at terminal 102 a. In addition, voltage V _OUT may reach a high voltage level (comparable to voltage V _BUS).

IN general, the detector circuit DT1 cannot simply use the signals IN _LS and IN _HS because the voltage state (high or low voltage state) is not determined by the signals IN _LS and IN _HS alone. For example, during an intermediate period between intervals T ₁ and T ₂, electronic switches HS and LS are turned off, and voltage V _OUT is related to load characteristics (such as the current direction of inductive load L). Furthermore, during testing of the driver circuit HBD, a "robustness test" may be performed in which the electronic switches HS and LS are not connected to the half-bridge driver HDB or to the half-bridge driver HDB with an uncorrelated configuration.

For example, in principle, the detector circuit DT1 may be implemented using a differential comparator. However, the inventors have observed that this may put a great stress on the input terminals of the comparators, since the voltage V _OUT is floating and may also reach the voltage V _BUS. For example, classical gate drive comparator solutions may not be feasible because voltages V _CC and V _OUT are separated by a high voltage. For example, the gate terminal of a typical MOS transistor is generally not capable of withstanding such high positive or negative gate-source voltages. One possible solution is a "drain-driven comparator" which requires a bias current at each input. Although this bias current can be minimized, high power consumption is still required because one of the two input terminals is in a high voltage state. In addition, such drain-driven comparators typically have a slower response time.

Alternatively, the comparator may not be placed in the floating section FS, but may be referenced to the reference voltage/ground GND at the node 102 b. In this case, the output signal HBlow may be level-shifted to the voltage level in the floating-level section FS via an additional level shifter (similar to circuit 14). However, the inventors have observed that the detector circuit DT1 preferably operates in the floating section FS, since its output should be available quickly in this domain. In addition to the additional power consumption and noise immunity issues, such level shifters introduce additional delays in detection. In any case, due to the high voltage difference, a drain driven comparator is also required in this case.

Disclosure of Invention

One or more embodiments of the present disclosure thus relate to a more efficient solution for implementing such a floating level detector circuit.

According to one or more embodiments, such objects are achieved by a half-bridge driver circuit having the features set forth in the appended claims. Embodiments are also related to integrated circuits, half-bridge switching circuits, and methods.

As previously described, various embodiments of the present disclosure relate to a half-bridge driver circuit configured to drive a half-bridge. In particular, the half bridge includes a high-side electronic switch and a low-side electronic switch connected between a supply voltage and a reference voltage (such as ground).

In various embodiments, a half-bridge driver circuit includes a first node configured to be connected to an intermediate node between a high-side electronic switch and a low-side electronic switch. Thus, the voltage at the first node, i.e. the voltage at the intermediate node between the high side electronic switch and the low side electronic switch, represents the floating reference voltage. The half-bridge driver circuit further includes positive and negative supply terminals for receiving a further supply voltage, and a second node configured to be connected to the first node via a capacitor. Specifically, the (bootstrap) charging circuit is configured to provide a charging current to the second node when the voltage at the second node is less than the further supply voltage, such that the second node provides a floating supply voltage that floats with the voltage at the first node (i.e., at the intermediate node between the high-side electronic switch and the low-side electronic switch).

Thus, the high-side driver may drive the control terminal of the high-side electronic switch of the half-bridge, wherein the high-side driver is powered by the floating supply voltage, and the low-side driver may drive the control terminal of the low-side electronic switch of the half-bridge, wherein the low-side driver is powered by the further supply voltage.

In accordance with the present disclosure, the half-bridge driver circuit further includes a detector circuit configured to generate a signal indicating whether the floating reference voltage at the first node is greater than a further supply voltage. For example, such a signal may be used to drive a current limiter circuit associated with a charging circuit.

Specifically, according to the present disclosure, a detector circuit includes a first circuit, a second circuit, and a combinational logic circuit.

In various embodiments, the first circuit includes a first diode having an anode connected to the further supply voltage and a cathode connected to the first decoupling node. The first circuit further includes a resistor having a first terminal coupled to the first decoupling node and a second terminal connected to the floating reference voltage. Thus, when the floating reference voltage is small, current flows from the further supply voltage through the resistor. Thus, the first comparator circuit may be configured to monitor the voltage drop at the resistor. Specifically, in response to determining that the monitored voltage drop is less than a first threshold, the first comparator circuit sets the first control signal to a corresponding first logic level. Conversely, in response to determining that the monitored voltage drop is greater than the first threshold, the first comparator circuit sets the first control signal to a corresponding second logic level. For example, the first comparator circuit may include a first inverter configured to set the first control signal high when the monitored voltage drop is less than a first threshold. To protect the first circuit, the first circuit may further include one or more voltage limiter circuits configured to limit a voltage drop at the resistor, such as one or more clamp diodes and/or zener diodes.

To protect the first circuit, the first circuit may further include a first n-channel FET, wherein a drain terminal of the first n-channel FET is connected to the first decoupling node, a source terminal of the first n-channel FET is connected to a first terminal of the resistor, and a gate terminal of the first n-channel FET is coupled to a floating supply voltage at the second node. As will be described in more detail below, the FET may implement cascode. To protect the gate terminal of the FET, the gate terminal of the FET may be connected to the floating supply voltage at the second node via a current limiter resistor and to the first terminal of the resistor via a diode and a further current limiter resistor.

In various embodiments, the first circuit may also implement a comparator with hysteresis. For example, for this purpose, the resistor may comprise a series connection of a first resistor and a second resistor, wherein the first circuit comprises an electronic switch configured to short-circuit the second resistor in response to detecting that the first control signal is set to the first logic level.

The inventors have observed that the detection of the first circuit may be unreliable in the event of a negative transient in the floating reference voltage due to the parasitic capacitance associated with the first diode.

To this end, in various embodiments, the second circuit implements a negative transient detection circuit. To this end, the second circuit comprises a current mirror comprising an input transistor and an output transistor. The input transistor may be associated with a bias circuit connected between the anode of the third diode and the second node. In various embodiments, the second circuit further comprises a second diode, an anode of the second diode being connected to a further supply voltage, and a cathode of the second diode being connected to a second decoupling node; and a third diode having a cathode connected to the second decoupling node and an anode connected to the floating reference voltage via an input transistor of the current mirror. Thus, the second and third diodes also have an associated parasitic capacitance, whereby in the event of a negative transient in the floating reference voltage, current flows through the input transistor of the current mirror.

Thus, in various embodiments, the second comparator circuit may monitor the current provided by the output transistor of the current mirror. Specifically, in response to determining that the monitored current is greater than a second threshold, the second comparator circuit sets the second control signal to a corresponding first logic level. Conversely, in response to determining that the monitored current is less than the second threshold, the second comparator circuit sets the second control signal to a corresponding second logic level. For example, the second comparator circuit may further include an inverter. Furthermore, the second comparator circuit may comprise a current-to-voltage conversion circuit, for example comprising a resistor connected between the output transistor of the current mirror and a further supply voltage at the second node.

Thus, the combinational logic circuit may assert the signal in response to determining that the first control signal has a corresponding first logic level or that the second control signal has a corresponding first logic level. Conversely, the combinational logic circuit may deassert the signal in response to determining that the first control signal has a corresponding second logic level and that the second control signal has a corresponding second logic level.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

Fig. 1 shows an example of a half-bridge switching circuit and related driving circuits including a high-side bootstrap architecture;

Fig. 2 and 3 show examples of various bootstrap architectures for a half-bridge switching circuit;

fig. 4 shows an example of a possible signal waveform in the circuits of fig. 2 and 3;

Fig. 5 shows a first embodiment of a detector circuit adapted for use in the half-bridge switching circuits of fig. 2 and 3;

FIG. 6 shows possible waveforms of signals in the circuit of FIG. 5; and

Fig. 7 shows a second embodiment of a detector circuit adapted for use in the half-bridge switching circuits of fig. 2 and 3.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. Embodiments may be provided without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

References in the framework of the present description to "an embodiment" or "one embodiment" are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment," "in one embodiment," and the like may appear in various points of the description and do not necessarily refer to the same embodiment. Furthermore, the particular conformations, structures, or features may be combined in any suitable manner in one or more embodiments.

The reference numerals used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.

In fig. 5 to 7 described below, the parts, elements or components that have been described with reference to fig. 1 to 4 are designated by the same reference numerals previously used in these figures. The description of these elements has been completed and will not be repeated in detail below in order to not burden the present detailed description.

As previously described, various embodiments of the present disclosure relate to a floating level detector circuit. In particular, such a detector circuit may be used in a half-bridge driver circuit to detect whether the voltage V _OUT at the switching node 102a of the half-bridge circuit is below or above a threshold. In general, the voltage V _OUT at the switching node 102a may be applied via an electronic switch, or via a load impedance when both electronic switches HS and LS are open.

Fig. 5 shows a first embodiment of a detector circuit DT1a according to the present disclosure.

Specifically, in the considered embodiment, the first terminal of the detector circuit DT1a is connected to the terminal 102a and is thus configured to receive the voltage V _OUT. As previously described, in various embodiments, node 102a may be connected to voltage V _BUS or reference voltage/ground GND via a half-bridge arrangement that includes two electronic switches HS and LS. For this purpose, reference is made to the previous description, in particular to the overall architecture shown in fig. 1.

Further, the second terminal is connected to terminal 102a and is thus configured to receive DC supply voltage V _CC. As previously mentioned, the supply voltage V _CC may be provided by any type of power supply PS and has a value typically between 3V and 20V. Specifically, in various embodiments, voltage V _CC is less than voltage V _BUS.

In the embodiment under consideration, the detector circuit DT1a further comprises a third terminal connected to the terminal 104, whereby the third terminal is configured to receive a supply voltage V _BOOT. Specifically, in various embodiments, the detector circuit DT1a is arranged in the floating section FS, i.e. the detector circuit DT1a is powered via a voltage V _CB＝V_BOOT-V_OUT referenced to a voltage V _OUT at the terminal 102a, i.e. the voltage V _BOOT floats with a voltage V _OUT.

In various embodiments, the voltage V _BOOT may be provided via a capacitor C _B connected between the terminals 104 and 102a, with the capacitor C _B being recharged via a bootstrap architecture. For example, in various embodiments, when node 102a is connected to reference voltage/ground GND via electronic switch LS, capacitor C _B is recharged via a charging circuit. Reference may be made to the description above of possible implementations of the charging circuit. For example, as previously described, the charging circuit may include a diode DB or an active diode circuit Q3/D3, and optional current limiter circuits (Q1 ', D1' and 62).

For example, as previously described, the signal generated by the detector circuit DT1a may be used to control the operation of such a current limiter circuit. However, since the signal generated by the detector circuit DT1a indicates whether the voltage V _OUT at the switching node 102a is above or below the voltage V _CC, the signal generated by the detector circuit DT1a may also be used for other purposes and the control of the current limiter transistor Q1' is only an exemplary application. For example, the signal provided by the detector circuit DT1a may be used to activate a low power state of one or more of the circuits in the floating section FS.

In general, due to the rapid variation of the voltage V _OUT, the detector circuit DT1a should be quite fast, e.g. the detection time should introduce only a few nanoseconds of delay. Furthermore, since the switching node 102a varies between the voltage V _BUS and the reference voltage/ground GND, the detector circuit DT1a should avoid stress or over-current in the component. Finally, since the detector circuit DT1a is arranged in the floating section FS, the detector circuit DT1a should have a lower power consumption, especially when the high side switch HS is closed, since in this case the power is typically only provided by the storage capacitor C _B. While these requirements for the comparator circuit are quite demanding, the inventors have observed that the accuracy of the detector circuit DT1a may be quite low, as the voltage V _BUS is typically significantly larger than the voltage V _CC, e.g. the voltage V _BUS is at least twice the voltage V _CC.

Specifically, in various embodiments, the detector circuit DT1a comprises a first circuit 30, the first circuit 30 essentially implementing a comparator, preferably a comparator with hysteresis. Specifically, in various embodiments, terminal 100 a/voltage V _CC is connected (e.g., directly) to node C2D via diode 300. Specifically, the anode of diode 300 is connected (e.g., directly) to voltage V _CC and the cathode of diode 300 is connected (e.g., directly) to node C2D.

In the embodiment considered, node C2C is coupled to a first node D of a resistor, wherein a second node of the resistor is connected to terminal 102a, i.e. voltage VOUT. For example, in various embodiments, the resistance is implemented using a series connection of at least two resistors/resistors 304 and 306, with a first terminal of resistor 304 connected to node D and a second terminal of resistor 304 connected to terminal 102a via resistor 306. For example, as shown in fig. 7, each of the resistors 304 and 306 may be implemented using one or more resistive elements, such as in an integrated circuit including the detector circuit DT1a, and possibly other circuits for implementing an integrated half-bridge driver circuit HBD.

Thus, when voltage V _OUT (plus the threshold voltage of diode 300) is less than voltage V _CC, current flows through resistors 304/306, generating voltage V _D at resistors 304/306 (i.e., between nodes D and 102 a). Since resistors 304/306 are connected to terminal 102 a/voltage V _OUT, voltage V _D is also referenced to voltage V _OUT.

Thus, in the embodiment under consideration, circuit 30 includes a comparison circuit 312 configured to assert a comparison signal DN1 when voltage V _D exceeds a threshold voltage. Specifically, in various embodiments, the comparison circuit is powered by voltage V _CB＝V_BOOT-V_OUT and comparison signal DN1 is referenced to voltage V _OUT.

For example, in the considered embodiment, the comparison circuit 312 is implemented using a (digital) inverter (i.e. NOT gate) powered by the voltage V _CB, i.e. the positive supply terminal of the inverter 312 is connected to the terminal 104/voltage V _BOOT and the negative supply terminal of the inverter 312 is connected to the terminal 102 a/voltage V _OUT. Thus, in this case, when voltage V _D exceeds the input threshold voltage of inverter 312, inverter 312 asserts signal DN1 by setting signal DN1 low. Similarly, when voltage V _D is below the input threshold voltage of inverter 312, inverter 312 deasserts signal DN1 by setting signal DN1 high.

In general, inverter 312 may also be replaced with other logic gates powered by voltage V _CB. For example, in various embodiments, the comparison circuit 312 includes a series connection of two or more inverters. Additionally or alternatively, the comparison circuit 312 may also include other logic gates, such as AND, OR, NAND or NOR gates.

For example, fig. 7 illustrates an embodiment in which the comparison circuit 312 includes a first inverter 420, the first inverter 420 being configured to set the signal DN low when the voltage V _D exceeds the input threshold voltage of the inverter 420. Similarly, inverter 420 sets signal DN high when voltage V _D falls below the input threshold voltage of inverter 312.

In various embodiments, the comparison circuit 312 includes or is associated with a logic gate 422, the logic gate 422 being configured to generate a signal to selectively enable the comparison circuit 312 by combining the signal DN with a signal RST_N (such as a reset signal). Thus, in the contemplated embodiment, the signal rst_n may be used to disable or enable the comparison circuit 312. For example, logic gate 422 may be an AND gate that directly provides signal DN1. Alternatively, logic gate 422 may be a NAND gate, and an additional inverter 424 may be used to generate signal DN1 by reversing the signal at the NAND 422 output.

In various embodiments, the comparison circuit 312 is also associated with (e.g., includes) an amplifier stage 310 configured to generate a voltage V _D' by amplifying the voltage V _D. Specifically, in the embodiment under consideration, the amplifier stage 310 is also powered by a voltage V _CB and the voltage V _D' is referenced to a voltage V _OUT. For example, in this case, inverter 312 may receive voltage V _D' (instead of voltage V _D) at an input.

In various embodiments, to implement a comparator with hysteresis, the value of resistance 304/306 may vary according to signal DN1, particularly decreasing resistance when signal DN1 is deasserted (when voltage V _D is less than a threshold) and increasing resistance when signal DN1 is asserted (when voltage V _D is less than a threshold). For example, when a series connection of at least two resistors 304 and 306 is used, the circuit 30 may include an electronic switch 308, the electronic switch 308 configured to short one of the resistors 304 and 306 when the signal DN1 is deasserted. More specifically, in the embodiment shown in fig. 5 and 7, electronic switch 308 is implemented using an n-channel FET, wherein the source terminal of FET 308 is connected (e.g., directly) to terminal 102 a/voltage V _OUT, the drain terminal of FET 308 is connected (e.g., directly) to an intermediate node between resistors 304 and 306 (where resistor 306 is connected between resistor 304 and terminal 102 a), and the gate terminal of FET 308 is connected to signal DN1, i.e., the output of comparison circuit 312. Thus, in the contemplated embodiment, the electronic switch 308 is configured to:

In response to determining that signal DN1 is deasserted (e.g., set high), electronic switch 308 is closed (shorting resistor 306); and

In response to determining that signal DN1 is asserted (e.g., set low), electronic switch 308 is opened (without shorting resistor 306).

Thus, in the embodiment under consideration, resistors 304 and 306 and electronic switch 308 implement a variable resistance, wherein the variable resistance has a first value when signal DN1 is asserted (e.g., set low) and a second value when signal DN1 is de-asserted (e.g., set high), wherein the second value is less than the first value.

In various embodiments, the circuit 30 includes a FET 302, wherein the current path of the electronic switch 302 is connected between the diode 300 and the resistor 304/306. For example, in the contemplated embodiment, electronic switch 302 is an n-channel FET, wherein the drain terminal of FET 302 is connected (e.g., directly) to node C2D and the source terminal of FET 302 is connected (e.g., directly) to node D. Specifically, in the embodiment under consideration, the gate terminal of FET 302 is connected (e.g., directly) to terminal 104/voltage V _BOOT.

Specifically, in the embodiment under consideration, transistor 302 implements cascode and pull-up. Specifically, transistor 302 belongs to the High Voltage (HV) category, allowing for maintaining integrity and functionality with high drain-source and drain-gate voltages. In fact, during the recirculation portion of the recharging phase (i.e., the initial portion of T ₂ in fig. 4), voltage V _OUT at node 102a is expected to drop below 0V. Thus, without transistor 302, node C2D would be connected to node D and voltage V _D could be generated at node D, which could be destructive due to the low threshold and low impedance of direct drive diode 300.

Thus, as shown in fig. 6, once electronic switch LS is open and electronic switch HS is closed, voltage V _OUT increases and voltage V _D decreases. (in absolute value, i.e., the voltage difference between nodes D and 102a decreases). In this regard, once voltage V _OUT exceeds a given threshold vtrig_hv, comparator circuit 312 triggers signal DN1 and deasserts it, e.g., inverter 312 sets signal DN1 high. As previously described, signal DN1 can also be used to change the value of resistors 304/306.

As shown in fig. 5, in practice, node C2D is coupled to node 100 a/voltage V _CC via a first capacitance CP1 (connected in parallel with diode 300) and to node 106/voltage V _BOOT via a second capacitance CP2 (connected between the drain terminal and the gate terminal of FET 302). In particular, in various embodiments, the capacitance is given only by the (parasitic) capacitance associated with the semiconductor component, as the additional oxide-based capacitor may not be able to maintain HV at its electrode. Thus, the capacitor represented by the dashed line in fig. 5 may refer to the junction capacitance associated with the component.

In this respect, the inventors have observed that circuit 30 is able to quickly detect the transition from the LV phase (T ₁) to the HV phase (T ₂) after the rising edge of voltage V _OUT, since node C2D represents a "decoupling node" that is capacitively coupled to a fixed voltage V _CC, fixed voltage V _CC representing "conceptual", allowing voltage V _D to be pulled down in parallel with resistor 304/306.

However, the inventors have observed that once electronic switch HS is opened and electronic switch LS is closed, circuit 30 may not always be able to properly signal HV phase (T ₂) during the falling edge of voltage VOUT. In fact, in this case, the capacitive coupling at node C2D now operates, rather than the pull-up of voltage V _D, so that voltage V _D increases in advance and comparator circuit 312 triggers and asserts signal DN1, e.g., inverter 312 sets signal DN1 low. Thus, if voltage V _OUT has a rapid negative change in high rate dV _OUT/dt, circuit 30 may signal a false HV off phase.

Thus, in various embodiments, the detector circuit DT1a includes a second circuit 32, the second circuit 32 being configured to detect a negative transition of the voltage V _OUT.

For example, in the embodiment considered, the circuit 32 comprises two diodes 320 and 322 connected in series. Specifically, the anode of diode 320 is connected (e.g., directly) to terminal 100 a/voltage V _CC, the cathode of diode 320 is connected (e.g., directly) to node C2C, the anode of diode 322 is connected (e.g., directly) to node DH, and the cathode of diode 322 is connected (e.g., directly) to node C2C. For example, as shown in fig. 7, at an example of diode 322, the diode may also be implemented using a FET, such as an n-channel FET.

Thus, also in this case, diode 320 is associated with a capacitance C _P3 connected between the cathode and anode of diode 320, and diode 322 is associated with a capacitance C _P4 connected between the cathode and anode of diode 322. Typically, these capacitances are parasitic capacitances of the diodes. For example, diodes 320 and 322 may be large to create larger parasitic capacitances C _P3 and C _P4.

In the embodiment under consideration, node DH is coupled to terminal 102 a/voltage V _OUT. Thus, in the embodiment considered, in case of a negative transition of the voltage V _OUT, i.e. a decrease of the voltage V _OUT, the capacitive coupling at the node C2C injects a current in the node DH.

For example, in the embodiment considered, the circuit 32 is configured to measure this current injected in the node DH. For example, to this end, the node DH is coupled to the terminal 102a via an input transistor of a current mirror. For example, in the embodiment considered, the current mirror is implemented using an input FET 326 and an output FET 328. For example, when an n-channel FET is used, the source terminal of FET 326 and the source terminal of FET 328 are connected (e.g., directly) to terminal 102 a/voltage V _OUT, the gate terminal of FET 326 is connected (e.g., directly) to the drain terminal of FET 326, and the gate terminal of FET 328 is connected (e.g., directly) to the gate terminal of FET 326. Thus, in the contemplated embodiment, the drain terminal of FET 326 is coupled (e.g., directly connected) to node DH.

In various embodiments, the input transistor 326 of the current mirror may also have an associated bias circuit 324. For example, in the embodiment shown in FIG. 5, the bias circuit 234 is implemented using a resistor connected (e.g., directly connected) between the terminal 104/voltage V _BOOT and the node DH. Resistor 324 may also be replaced by a current source in general. For example, in fig. 7, a FET 324 is used, such as a p-channel FET, wherein the current path of the FET 324 is connected between the node 104 and DH and the gate terminal may be disconnected, thus basically realizing a resistor, because the FET 324 operates in the triode region, or may be connected to an appropriate gate-source voltage as a (leakage) current source.

In contrast, in the embodiment shown in FIG. 7, the bias circuit 234 is implemented using a FET (such as a p-channel FET) with a current path connected between the terminal 104/voltage V _BOOT and the node DH.

Thus, in the embodiment under consideration, the output transistor 328 of the current mirror provides a current I _M, current I _M indicating that in the event of a negative transition in voltage V _OUT, node C2C injects charge into node DH via capacitors CP3 and CP 4.

Thus, in the considered embodiment, the current I _M provided by the output transistor 328 of the current mirror may be fed to a comparison circuit 330 configured to generate a binary signal DH1, wherein the comparison circuit 330 asserts the signal DH1, e.g., sets the signal DH1 high, when the current I _M is greater than a given threshold value; and deasserting the signal DH1 when the current I _M is less than a given threshold, e.g., when the signal DH1 is set low. Specifically, in the embodiment under consideration, the comparison circuit 330 is powered by a voltage V _CB＝V_BOOT-V_OUT, and the signal DH1 is referenced to a voltage V _OUT.

For example, for this purpose, the comparison circuit 330 may associate (e.g., may include) a current-to-voltage conversion circuit configured to generate a voltage indicative of (and preferably proportional to) the value of the current I _M. For example, in the embodiment shown in fig. 7, the current-to-voltage conversion is implemented using a resistive element 444, wherein the circuit 330 is configured such that a current I _M flows through the resistive element 444. For example, in the contemplated embodiment, the resistive element 444 is connected between the drain terminal of the FET 328 (also denoted as node DHN in the following figures) and the terminal 104/voltage V _BOOT. Thus, in the embodiment under consideration, as the current I _M increases, the voltage drop at the resistive element 444 also increases. For example, in the embodiment considered, this means that the voltage between the drain and source terminals of FET 328 decreases.

Thus, in various embodiments, the comparator circuit 330 may be configured to monitor the voltage at the resistive element 444 or the voltage drop between the drain and source terminals of the FET 328, i.e., the voltage at the node DHN. For example, similar to circuit 30, in the embodiment considered, comparison circuit 330 is implemented using an inverter having an input connected to node DHN.

Fig. 7 also shows a possible implementation of such an inverter, which may be used for any of the inverters mentioned previously. Specifically, in the embodiment under consideration, the input terminal of the inverter, i.e., node DHN, is connected to the gate terminal of p-channel FET 448 and the gate terminal of n-channel FET 450, the source terminal of p-channel FET 448 is connected to voltage V _BOOT, the source terminal of n-channel FET 450 is connected to voltage V _OUT and the drain terminals of p-channel FET 448 and n-channel FET 450 are connected to the output terminal of the inverter.

As shown in fig. 6, charge is injected into node DH only during the transition of voltage V _OUT. In contrast, when the voltage V _OUT remains stable, no charge is injected. In various embodiments, the circuit 32 may be configured to monitor only negative transitions of the voltage V _OUT, which may be ensured, for example, when using a current mirror 326/328 with an n-channel FET.

Thus, in the contemplated embodiment, the circuit 32 is configured to assert the signal DH1 in response to detecting a negative change/transition in the voltage V _OUT. Thus, as shown in fig. 6, to properly detect the HV phase (T ₁), the detector circuit DT1a may be configured to generate a signal OUT2HV, the signal OUT2HV being asserted when at least one of the signals DN1 or DH1 is asserted. For example, as shown in fig. 5, in various embodiments, the detector circuit DT1a comprises a logic gate, such as an OR gate, configured to:

In response to determining that signal DN1 is asserted or signal DH1 is asserted, signal OUT2HV is asserted; and

In response to determining that signal DN1 is deasserted and signal DH1 is deasserted, signal OUT2HV is deasserted.

Fig. 7 shows an alternative embodiment in this regard, in which the OR gate 34 has been replaced with a NAND gate 484 and two inverters 480 and 482.

Fig. 7 shows a further possible modification of the basic circuit shown in fig. 5. In general, these improvements are only optional and may be used alone or in combination.

Specifically, according to the first aspect, each of the nodes C2C and C2C may be connected to the voltage V _OUT via a respective diode 400 and 440. For example, the cathode of diode 400 may be connected to node C2D and the anode of diode 400 may be connected to voltage V _OUT. Similarly, the cathode of diode 440 may be connected to node C2C and the anode of diode 440 may be connected to voltage V _OUT. Such a diode allows limiting the voltage stress at the nodes C2C and C2D. Specifically, diodes 400 and 440 operate during the rising phase of voltage V _OUT, at which time high currents may drain from nodes D and DH, creating possible voltage stresses. In contrast, diodes 400 and 440 maintain the voltages at nodes C2D and C2C near voltage V _OUT.

According to the second aspect, the input node D of the comparison circuit 312, i.e., the voltage V _D, may be associated with one or more voltage stress limiter circuits 410 and/or 404.

Specifically, in various embodiments, the voltage stress limiter circuit 410 includes a diode 402, wherein a cathode of the diode 402 is connected to the input node D of the comparison circuit 312, and an anode of the diode 402 is connected to the voltage V _OUT.

In various embodiments, the input node D of the comparison circuit 312 may also be coupled to the voltage V _BOOT via a diode 412. Specifically, in various embodiments, the anode of diode 412 is connected to voltage V _BOOT and the cathode of diode 412 is connected to the input terminal of comparison circuit 312 via resistor 416. In general, diodes 412 and 402 may also be implemented using a series connection of multiple diodes (as schematically illustrated via diode 414). Further, one or more of diodes 402, 412, and 414 may be implemented using FETs.

Further, rather than directly connecting the gate terminal of FET 302 and the anode of diode 412 to voltage V _BOOT, stress limiter circuit 410 includes a resistor 418 connected between the anode of diode 412 and terminal 104, and the gate terminal of FET 302 may be connected to the anode of diode 412.

In essence, voltage limiter circuit 410 is configured to limit voltage V _D in the event that the transitions of voltage V _OUT and voltage V _D are less than voltage V _OUT, i.e., in the event of a positive transition of voltage V _OUT. Further, components 412 (and 414) and 416 (and 418) provide current only when voltage V _D is near or below voltage V _OUT, limiting the voltage at the gate terminal of FET 302 by draining current from the voltage supply provided to the gate terminal.

Conversely, the voltage stress limiter circuit 404 may include a zener diode 406 connected between the node D/voltage V _D and the voltage V _OUT, where the cathode of the diode 406 is connected to the input terminal D of the comparison circuit 312 and the anode of the diode 406 is connected to the terminal 102a. In essence, voltage limiter circuit 404 is configured to limit voltage V _D in the event that voltage V _D overcomes voltage V _OUT by the breakdown voltage of zener diode 406, particularly in the event of a negative transition in voltage V _OUT. Specifically, the size of the zener diode 406 should be such that the threshold voltage is greater than the voltage V _{trig_hv}, so when the voltage V _D is (far) above the threshold V _{trig_hv}, the zener diode draws current.

In addition to or as an alternative to the zener diode 406, the voltage V _D may also be limited via a current limiter FET 408. For example, in the embodiment considered, the current limiter 408 is implemented using a p-channel FET (such as PMOS), which is connected (its current path) between terminal D and terminal 102a, wherein the gate terminal of the p-channel FET 408 is driven by an inverted version of the signal DH 1. Thus, in the embodiment under consideration, when the signal DH1 is low, i.e., when no negative transition is detected and the gate terminal of FET 408 is set high, FET 408 turns off when the gate-source voltage of FET 408 exceeds a given threshold, so that FET 408 drains current, limiting voltage V _D with respect to the voltage at the gate terminal of FET 408. Thus, FET 408 allows limiting the dynamics of voltage V _D in the event of a negative transition of voltage V _OUT.

According to a third aspect, the comparison circuit 330 may further comprise a limiter circuit for the inverter 448/450. Specifically, in the contemplated embodiment, an n-channel FET 446 (such as an NMOS) (its current path) is connected between the node 104 and DHN, and the gate terminal of the FET 446 is connected to the node DH1. Specifically, the FET 446 allows the voltage at node DHN (the input terminal of inverter 448/450) to be maintained close to the "trigger point" of the inverter, thereby reducing the time response of the comparison circuit. Specifically, without FET 446, the voltage at node DHN may be very close to voltage V _OUT during the detection of a negative transition of voltage V _OUT. This is due to the high gain of the current to voltage conversion stage 328/444. But the falling transient of voltage V _OUT should respond quickly to the bootstrap path once it has ended to avoid any overshoot of voltage VCB. In this regard, because FET 446 is turned on only when signal DH1 has "triggered high", FET 446 acts as a limiter of the voltage "drop" at node DHN (i.e., the input of inverter 448/450) without interfering with the operation of inverter 448/450.

Finally, according to the fourth aspect, the circuit 32 may also be reset or enabled according to the signal rst_n. For example, in the embodiment under consideration, circuit 32 comprises an electronic switch 442, such as an N-channel FET, electronic switch 442 (its current path) being connected between node DH and terminal 102a, wherein the control terminal of electronic switch 442 is driven via signal rst_n.

Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary greatly with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the disclosure as defined by the annexed claims.

A half-bridge driver circuit (HBD) configured to drive a half-bridge comprising a high-side electronic switch (HS) and a low-side electronic switch (LS) connected between a supply voltage (V _BUS) and a reference voltage (GND), wherein the half-bridge driver circuit (HBD) may be summarized as comprising: -a first node (102 a) configured to be connected to an intermediate node between the high-side electronic switch (HS) and the low-side electronic switch (LS), the voltage at the first node representing a floating reference voltage (V _OUT); -a second node (104) configured to be connected to the first node (102 a) via a Capacitor (CB); a positive power supply terminal (100A) and a negative power supply terminal (100 b, 102 b) for receiving a further power supply voltage (V _CC); a charging circuit (DB; d3, Q3, Q1', D1') configured to provide a charging current to the second node (104) when the voltage (V _BOOT) at the second node (104) is less than the further supply voltage (V _CC), whereby the second node (104) provides a floating supply voltage (V _CB), A floating supply voltage (V _CB) is floated with the floating reference voltage (V _OUT) at the first node (102 a); A high-side driver (12A) configured to drive a control terminal of the high-side electronic switch (HS) of the half-bridge, wherein the high-side driver (12A) is powered by the floating supply voltage (V _CB); -a low-side driver (12 b) configured to drive a control terminal of the low-side electronic switch (LS) of the half-bridge, wherein the low-side driver (12 b) is powered by the further supply voltage (V _CC); A detector circuit (DT 1; DT1 a) configured to generate a signal (HBlow; OUT2 HV) indicating whether the floating reference voltage (V _OUT) at the first node (102 a) is greater than the further supply voltage (V _CC); wherein the detector circuit (DT 1 a) may be summarized as comprising: a) -a first circuit (30), the first circuit (30) comprising a first diode (300) having an anode connected to said further supply voltage (V _CC) and a cathode connected to a first decoupling node (C2D), wherein a first parasitic capacitance (CP 1) is associated with said first diode (300); A resistor (304, 306) having a first terminal coupled to the first decoupling node (C2D) and a second terminal connected to the floating reference voltage (V _OUT); -a first comparator circuit (312) configured to monitor a voltage drop (V _D) at the resistor (304; 306), wherein: in response to determining that the monitored voltage drop (V _D) is less than a first threshold, setting a first control signal (DN 1) to a corresponding first logic level; And in response to determining that the monitored voltage drop (V _D) is greater than the first threshold, setting the first control signal (DN 1) to a respective second logic level; b) A second circuit (32) comprising a current mirror comprising an input transistor (326) and an output transistor (328); -a second diode (320) having an anode connected to the further supply voltage (V _CC) and a cathode connected to a second decoupling node (C2C), wherein a second parasitic capacitance (CP 3) is associated with the second diode (320); A third diode (322) having a cathode connected to the second decoupling node (C2C) and an anode (DH) connected to the floating reference voltage (V _OUT) via an input transistor (326) of the current mirror, wherein a third parasitic capacitance (CP 4) is associated with the third diode (322); a second comparator circuit (330) configured to monitor a current (I _M) provided by an output transistor (328) of the current mirror, wherein in response to determining that the monitored current (I _M) is greater than a second threshold, a second control signal (DH 1) is set to a corresponding first logic level, and in response to determining that the monitored current (I _M) is less than the second threshold, Setting the second control signal (DH 1) to a respective second logic level; And c) combinational logic circuitry (34) configured to: in response to determining that the first control signal (DN 1) has a corresponding first logic level or that the second control signal (DH 1) has a corresponding first logic level, asserting the signal (HBlow; OUT2 HV); and in response to determining that the first control signal (DN 1) has a corresponding second logic level and that the second control signal (DH 1) has a corresponding second logic level, deasserting the signal (HBlow; OUT2 HV).

The resistor (304, 306) may be switched between a first resistance value (304, 306) and a second resistance value (304), wherein the second resistance value (304) may be smaller than the first resistance value (304, 306), and wherein the first circuit (30) is configured to: -activating a second resistance value (304) of the resistor in response to detecting that the first control signal (DN 1) is set to the first logic level; and in response to detecting that the first control signal (DN 1) is set to the second logic level, activating the first resistance value (304, 306) of the resistor.

The resistors (304, 306) may comprise a series connection of a first resistor (304) and a second resistor (306), wherein the first circuit (30) may comprise an electronic switch (308), the electronic switch (308) being configured to short-circuit the second resistor (306) in response to detecting that the first control signal (DN 1) may be set to the first logic level.

The first circuit (30) may include a first n-channel FET (302), wherein a drain terminal of the first n-channel FET (302) may be connected to the first decoupling node (C2D), a source terminal of the first n-channel FET (302) may be connected to the first terminal (D) of the resistor (304, 306) and a gate terminal of the first n-channel FET (302) may be coupled to the second node (104).

The gate terminal of the first n-channel FET (302) may be connected to the second node (104) via a first current limiter resistor (418), and wherein the gate terminal (302) of the first n-channel FET may be connected to the first terminal (D) of the resistor (304, 306) via a fourth diode (412, 414) and a second current limiter resistor (416).

The half-bridge driver circuit (HBD) may include at least one of: -a first clamping diode (402), wherein an anode of the first clamping diode (402) is connected to the floating reference voltage (V _OUT) and a cathode of the first clamping diode (402) is connected to the first terminal (D) of the resistor (304, 306); -a second clamping diode (400), wherein an anode of the second clamping diode (400) is connected to the floating reference voltage (V _OUT) and a cathode of the second clamping diode (400) is connected to the first decoupling node (C2D); and a third clamp diode (440), wherein an anode of the third clamp diode (440) is connected to the floating reference voltage (V _OUT) and a cathode of the second clamp diode (440) is connected to the second decoupling node (C2C).

The first comparator circuit (312) may include a first inverter (420) configured to: setting the first control signal (DN 1) high in response to determining that the monitored voltage drop (V _D) is less than the first threshold, and setting the first control signal (DN 1) low in response to determining that the monitored voltage drop (V _D) is greater than the first threshold; wherein the second comparator circuit (330) comprises a second inverter (448, 450) configured to: the second control signal (DH 1) is set high in response to determining that the monitored current (I _M) is greater than the second threshold, and the second control signal (DH 1) is set low in response to determining that the monitored current (I _M) is less than the second threshold.

The second comparator circuit (330) may include a current-to-voltage conversion circuit (444), the current-to-voltage conversion circuit (444) including a current-to-voltage conversion resistor (444) connected between the output transistor (328) of the current mirror and the second node (104).

The half-bridge driver circuit (HBD) may comprise a zener diode (406), wherein an anode of the zener diode (406) is connected to the floating reference voltage (V _OUT) and a cathode of the zener diode (406) is connected to the first terminal (D) of the resistor (304, 306); and/or a voltage limiter FET (408), wherein the voltage limiter FET (408) is a p-channel FET having a drain terminal connected to the floating reference voltage (V _OUT), a source terminal connected to the first terminal (D) of the resistor (304, 306), and a gate terminal connected to an inverted version of the second control signal (DH 1).

The second circuit (32) may include a bias circuit (324), the bias circuit (324) being connected between an anode (DH) of the third diode (322) and the second node (104).

The integrated circuit may include a half-bridge driver circuit (HBD).

The half-bridge switching circuit may be summarized as including: half-bridge driver circuit (HBD) according to any one of the preceding claims; a high-side electronic switch (HS) and a low-side electronic switch (LS) connected between a supply voltage (V _BUS) and a reference voltage (GND), wherein a first node (102 a) of the half-bridge driver circuit (HBD) is connected to an intermediate node between the high-side electronic switch (HS) and the low-side electronic switch (LS); and a capacitor (C _B) connected between a first node (102 a) of the half-bridge driver circuit (HBD) and a second node (104) of the half-bridge driver circuit (HBD).

The method of operating a half-bridge switching circuit may be summarized as including: -applying a supply voltage (V _BUS) to the high-side electronic switch (HS) and the low-side electronic switch (LS), and-applying a further supply voltage (V _CC) to the half-bridge driver circuit (HBD); when the voltage (V _BOOT) at the second node (104) of the half-bridge driver circuit (HBD) is smaller than the further supply voltage (V _CC), a charging current is supplied to the second node (104) via a charging circuit (DB; D3, Q1', D1') of the half-bridge driver circuit (HBD), whereby the second node (104) of the half-bridge driver circuit (HBD) provides a floating supply voltage (V _CB), the floating supply voltage (V _CB) being floating with a floating reference voltage (V _OUT), the floating reference voltage (V _OUT) being located at an intermediate node between the high-side electronic switch (HS) and the low-side electronic switch (LS); -driving a control terminal of the high-side electronic switch (HS) via a high-side driver (12 a) of the half-bridge driver circuit (HBD); -driving a control terminal of the low-side electronic switch (LS) via a low-side driver (12 b) of the half-bridge driver circuit (HBD); and generating a signal (HBlow; OUT2 HV) via a detector circuit (DT 1; DT1 a) of the half-bridge driver circuit (HBD), the signal (HBlow; OUT2 HV) indicating whether a floating reference voltage (V _OUT) at an intermediate node between the high-side electronic switch (HS) and the low-side electronic switch (LS) is greater than the further supply voltage (V _CC).

The various embodiments described above may be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims (22)

1. A half-bridge driver circuit comprising:

A first node configured to be coupled to an intermediate node between a high-side electronic switch and a low-side electronic switch of a half-bridge driven by the half-bridge driver circuit, the high-side electronic switch and the low-side electronic switch being coupled between a first supply voltage and a reference voltage, a voltage at the first node representing a floating reference voltage;

a second node configured to be coupled to the first node via a capacitor;

a positive power supply terminal and a negative power supply terminal for receiving a second power supply voltage;

a charging circuit configured to provide a charging current to the second node in response to a voltage at the second node being less than the second power supply voltage, wherein the second node provides a floating power supply voltage that floats with a floating reference voltage at the first node;

a high-side driver configured to drive a control terminal of the high-side electronic switch, wherein the high-side driver is powered by the floating power supply voltage;

a low-side driver configured to drive a control terminal of the low-side electronic switch, wherein the low-side driver is powered by the second power supply voltage; and

A detector circuit configured to generate a signal indicating whether the floating reference voltage at the first node is greater than the second supply voltage.

2. The half-bridge driver circuit of claim 1, wherein the detector circuit comprises:

a first circuit, comprising:

A first diode having an anode coupled to the second supply voltage and a cathode coupled to a first decoupling node, wherein a first parasitic capacitance is associated with the first diode;

a resistor having a first terminal coupled to the first decoupling node and a second terminal coupled to the floating reference voltage; and

A first comparator circuit configured to monitor a voltage drop at the resistor, wherein the first comparator circuit is configured to:

In response to determining that the monitored voltage drop is less than the first threshold, setting the first control signal to a corresponding first logic level, and

In response to determining that the monitored voltage drop is greater than the first threshold, the first control signal is set to a corresponding second logic level.

3. The half-bridge driver circuit of claim 2, wherein the detector circuit comprises:

Combinational logic circuitry configured to:

in response to determining that the first control signal has the respective first logic level, asserting the signal; and

In response to determining that the first control signal has the respective second logic level and that the second control signal has the respective second logic level, the signal is deasserted.

4. The half-bridge driver circuit of claim 1, wherein the detector circuit comprises:

A second circuit comprising:

a current mirror including an input transistor and an output transistor;

A second diode having an anode coupled to the second supply voltage and a cathode coupled to a second decoupling node, wherein a second parasitic capacitance is associated with the second diode;

A third diode having a cathode coupled to the second decoupling node and an anode coupled to the floating reference voltage via the input transistor of the current mirror, wherein a third parasitic capacitance is associated with the third diode; and

A second comparator circuit configured to:

Monitoring a current provided by the output transistor of the current mirror;

In response to determining that the monitored current is greater than a second threshold, setting the second control signal to a corresponding first logic level; and

In response to determining that the monitored current is less than the second threshold, the second control signal is set to a corresponding second logic level.

5. The half-bridge driver circuit of claim 4, wherein the detector circuit comprises:

Combinational logic circuitry configured to:

In response to determining that the second control signal has the respective first logic level, asserting the signal; and

In response to determining that a first control signal has a respective second logic level and that the second control signal has the respective second logic level, the signal is deasserted.

6. The half-bridge driver circuit of claim 2, wherein the resistance is switchable between a first resistance value and a second resistance value, wherein the second resistance value is less than the first resistance value, and wherein the first circuit is configured to:

Activating the second resistance value of the resistor in response to detecting that the first control signal is set to the first logic level; and

The first resistance value of the resistor is activated in response to detecting that the first control signal is set to the second logic level.

7. The half-bridge driver circuit of claim 2, wherein the resistor comprises a series connection of a first resistor and a second resistor, wherein the first circuit comprises an electronic switch configured to short the second resistor in response to detecting that the first control signal is set to the first logic level.

8. The half-bridge driver circuit of claim 2, wherein the first circuit comprises a first n-channel field effect transistor FET, wherein a drain terminal of the first n-channel FET is coupled to the first decoupling node, a source terminal of the first n-channel FET is coupled to the first terminal of the resistor, and a gate terminal of the first n-channel FET is coupled to the second node.

9. The half-bridge driver circuit of claim 8, wherein the gate terminal of the first n-channel FET is coupled to the second node via a first current limiter resistor, and wherein the gate terminal of the first n-channel FET is coupled to the first terminal of the resistor via a fourth diode and a second current limiter resistor.

10. The half-bridge driver circuit of claim 2, comprising at least one clamp diode selected from a list of clamp diodes, the list of clamp diodes comprising:

a first clamp diode, wherein an anode of the first clamp diode is coupled to the floating reference voltage and a cathode of the first clamp diode is coupled to the first terminal of the resistor;

a second clamp diode, wherein an anode of the second clamp diode is coupled to the floating reference voltage and a cathode of the second clamp diode is coupled to the first decoupling node; and

A third clamp diode, wherein an anode of the third clamp diode is coupled to the floating reference voltage and a cathode of the third clamp diode is coupled to a second decoupling node.

11. The half-bridge driver circuit of claim 2, wherein the first comparator circuit comprises a first inverter configured to:

In response to determining that the monitored voltage drop is less than the first threshold, setting the first control signal high; and

The first control signal is set low in response to determining that the monitored voltage drop is greater than the first threshold.

12. The half-bridge driver circuit of claim 4, wherein the second comparator circuit comprises a second inverter configured to:

In response to determining that the monitored current is greater than the second threshold, setting the second control signal high; and

The second control signal is set low in response to determining that the monitored current is less than the second threshold.

13. The half-bridge driver circuit of claim 4, wherein the second comparator circuit comprises a current-to-voltage conversion circuit comprising a current-to-voltage conversion resistor coupled between the output transistor of the current mirror and the second node.

14. The half-bridge driver circuit of claim 2, comprising:

a zener diode, wherein an anode of the zener diode is coupled to the floating reference voltage and a cathode of the zener diode is coupled to the first terminal of the resistor; or alternatively

A voltage limiter FET, wherein the voltage limiter FET is a p-channel FET having a drain terminal coupled to the floating reference voltage, a source terminal coupled to the first terminal of the resistor, and a gate terminal coupled to an inverted version of a second control signal.

15. The half-bridge driver circuit of claim 4, wherein the second circuit comprises a bias circuit coupled between the anode of the third diode and a second node.

16. A half-bridge switching circuit comprising:

a high-side electronic switch and a low-side electronic switch coupled between a first supply voltage and a reference voltage, wherein an intermediate node is coupled to the high-side electronic switch and the low-side electronic switch;

A capacitor; and

A half-bridge driver circuit comprising:

A first node configured to be coupled to the intermediate node, the voltage at the first node representing a floating reference voltage;

A second node configured to be coupled to the first node via the capacitor;

a positive power supply terminal and a negative power supply terminal for receiving a second power supply voltage;

a charging circuit configured to provide a charging current to the second node in response to a voltage at the second node being less than the second power supply voltage, wherein the second node provides a floating power supply voltage that floats with the floating reference voltage at the first node;

a high-side driver configured to drive a control terminal of the high-side electronic switch, wherein the high-side driver is powered by the floating power supply voltage;

a low-side driver configured to drive a control terminal of the low-side electronic switch, wherein the low-side driver is powered by the second power supply voltage; and

A detector circuit configured to generate a signal indicating whether the floating reference voltage at the first node is greater than the second supply voltage.

17. The half-bridge switching circuit of claim 16, wherein the detector circuit comprises:

a first circuit, comprising:

A first diode having an anode coupled to the second supply voltage and a cathode coupled to a first decoupling node, wherein a first parasitic capacitance is associated with the first diode;

a resistor having a first terminal coupled to the first decoupling node and a second terminal coupled to the floating reference voltage; and

A first comparator circuit configured to:

monitoring the voltage drop at the resistor;

In response to determining that the monitored voltage drop is less than the first threshold, setting the first control signal to a corresponding first logic level, and

In response to determining that the monitored voltage drop is greater than the first threshold, the first control signal is set to a corresponding second logic level.

18. The half-bridge switching circuit of claim 17, wherein the detector circuit comprises:

A second circuit comprising:

a current mirror including an input transistor and an output transistor;

A second diode having an anode coupled to the second supply voltage and a cathode coupled to a second decoupling node, wherein a second parasitic capacitance is associated with the second diode;

A third diode having a cathode coupled to the second decoupling node and an anode coupled to the floating reference voltage via the input transistor of the current mirror, wherein a third parasitic capacitance is associated with the third diode; and

A second comparator circuit configured to:

Monitoring a current provided by the output transistor of the current mirror;

In response to determining that the monitored current is greater than a second threshold, setting the second control signal to a corresponding first logic level; and

In response to determining that the monitored current is less than the second threshold, the second control signal is set to a corresponding second logic level.

19. The half-bridge switching circuit of claim 18, wherein the detector circuit comprises:

Combinational logic circuitry configured to:

In response to determining that the first control signal has the respective first logic level or the second control signal has the respective first logic level, asserting the signal; and

In response to determining that the first control signal has the respective second logic level and the second control signal has the respective second logic level, the signal is deasserted.

20. A method of operating a half-bridge switching circuit, comprising:

Applying a first power supply voltage to the high-side electronic switch and the low-side electronic switch;

applying a second supply voltage to the half-bridge driver circuit;

Providing, by a charging circuit of the half-bridge driver circuit, a charging current to a second node when a voltage at the second node of the half-bridge driver circuit is less than the second power supply voltage, wherein the second node of the half-bridge driver circuit provides a floating power supply voltage that floats with a floating reference voltage at an intermediate node between the high-side electronic switch and the low-side electronic switch;

driving a control terminal of the high-side electronic switch by a high-side driver of the half-bridge driver circuit;

driving a control terminal of the low-side electronic switch by a low-side driver of the half-bridge driver circuit; and

A signal is generated by a detector circuit of the half-bridge driver circuit, the signal indicating whether the floating reference voltage at the intermediate node between the high-side electronic switch and the low-side electronic switch is greater than the second supply voltage.

21. The method of claim 20, comprising:

Monitoring the voltage drop at the resistor;

In response to determining that the monitored voltage drop is less than a first threshold, setting the first control signal to a corresponding first logic level; and

In response to determining that the monitored voltage drop is greater than the first threshold, the first control signal is set to a corresponding second logic level.

22. The method of claim 20, comprising:

monitoring the current provided by the output transistor of the current mirror;

In response to determining that the monitored current is greater than a second threshold, setting the second control signal to a corresponding first logic level; and

In response to determining that the monitored current is less than the second threshold, the second control signal is set to a corresponding second logic level.