CN118352357A

CN118352357A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN118352357A
Application number: CN202410321626.6A
Authority: CN
Inventors: 赖蓓盈; 陈昱璇; 陈彦甫; 许嘉芸; 侯承浩; 李达元; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-03-21
Filing date: 2024-03-20
Publication date: 2024-07-16

Abstract

Embodiments of the present application provide a semiconductor device in which a first n-type transistor includes a first channel element, an undoped first gate dielectric layer disposed over the first channel element, and a first gate electrode disposed over the undoped first gate dielectric layer. The second n-type transistor includes a second channel element and a doped second gate dielectric layer disposed over the second channel element. The second gate dielectric layer is doped with a p-type dipole material. The second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. An aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode. Embodiments of the present application also provide methods of manufacturing semiconductor devices.

Description

Semiconductor device and method for manufacturing the same

Technical Field

Embodiments of the present application relate to a semiconductor device and a method of manufacturing the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in integrated circuit materials and design have resulted in several generations of integrated circuits, each generation having smaller, more complex circuitry than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. Such a scaling down process generally provides benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs. For example, as device dimensions shrink, undesirable diffusion of elements between adjacent device components may more readily occur and undesirable negative effects may be more pronounced. In some cases, unintended aluminum diffusion between the gate dielectric layer and the metal gate electrode may interfere with proper tuning of the threshold voltage. Thus, device performance may not be optimal.

Thus, while conventional methods of fabricating semiconductor devices are generally adequate, they are not satisfactory in all respects.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a semiconductor device including: a first n-type transistor, the first n-type transistor comprising: a first channel assembly; a first gate dielectric layer disposed over the first channel element, wherein the first gate dielectric layer is undoped; and a first gate electrode disposed over the first gate dielectric layer; and a second n-type transistor including: a second channel assembly; a second gate dielectric layer disposed over the second channel element, wherein the second gate dielectric layer is doped with a p-type dipole material; and a second gate electrode disposed over the second gate dielectric layer; wherein at least one of the first n-type transistor or the second n-type transistor further comprises an aluminum-free conductive layer, and wherein the aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.

According to another aspect of an embodiment of the present application, there is provided a semiconductor device including: a first vertical stack of transistors, wherein the first vertical stack of transistors comprises a first n-type transistor and a first p-type transistor; a second vertical stack of transistors, wherein the second vertical stack of transistors comprises a second n-type transistor and a second p-type transistor; wherein: the first n-type transistor and the first p-type transistor include undoped gate dielectric layers; the second n-type transistor and the second p-type transistor include doped gate dielectric layers; at least one of the first n-type transistor or the second n-type transistor is circumferentially surrounded by a conductive layer that is free of dipole material; and an n-type metal gate electrode circumferentially surrounding the conductive layer.

According to still another aspect of an embodiment of the present application, there is provided a method of manufacturing a semiconductor device, including: forming a first gate dielectric layer over the first channel element and forming a second gate dielectric layer over the second channel element; wherein the first gate dielectric layer and the second gate dielectric layer are each undoped; forming a p-dipole dopant source over the second gate dielectric layer; performing a dipole driving process, wherein atoms of the p-dipole dopant source layer are driven into the second gate dielectric layer by the dipole driving process such that the second gate dielectric layer is doped; removing the p-dipole dopant source after the dipole driving process has been performed; and depositing an aluminum-free conductive layer over at least one of the first gate dielectric layer or the second gate dielectric layer after removing the p-dipole dopant source.

Drawings

The various aspects of the disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a perspective view of an IC device in the form of a FinFET in accordance with various aspects of the present disclosure.

Fig. 1B is a top plan view of an IC device in the form of a FinFET in accordance with various aspects of the present disclosure.

Fig. 1C is a perspective view of an IC device in the form of a GAA device in accordance with aspects of the present disclosure.

Fig. 2-27 are cross-sectional side views illustrating various process flows for forming an IC device in accordance with aspects of the present disclosure.

Fig. 28 is a block diagram of a manufacturing system in accordance with various aspects of the present disclosure.

Fig. 29 is a flowchart illustrating a method of manufacturing a semiconductor device according to aspects of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the present disclosure below, the formation of a component on, connected to, and/or coupled to another component may include embodiments in which the components are formed in direct contact, and may also include embodiments in which additional components may be formed to insert particular components such that the components may not be in direct contact. Further, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "upward" and "downward," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," and the like) are used to simplify the relationship of one component of the disclosure to another. Spatially relative terms are intended to cover different orientations of a device comprising the components. Still further, when a number or range of numbers is described by "about," "approximately," etc., the term is intended to include numbers within a reasonable range including the number described, e.g., within +/-10% of the number described or other values as understood by one of skill in the art. For example, the term "about 5nm" includes the size range from 4.5nm to 5.5 nm.

The present disclosure relates generally to semiconductor devices, and more particularly to Field Effect Transistors (FETs), such as three-dimensional fin FETs (finfets) or full gate-all-around (GAA) devices. In this regard, the FinFET device is a fin field effect transistor device, while the GAA device is a multi-channel field effect transistor device. FinFET devices and GAA devices have become increasingly popular in the semiconductor industry recently because they have several advantages over conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices (e.g., a "planar" transistor device). These advantages may include better chip area efficiency, improved carrier mobility, and manufacturing processes compatible with those of planar devices. Accordingly, it may be desirable to design a portion of an Integrated Circuit (IC) chip or the entire IC chip using FinFET devices or GAA devices.

However, despite the advantages of FinFET devices and/or GAA devices, certain challenges may still exist in IC applications implementing FinFET or GAA devices. For example, conventional threshold voltage (Vt) tuning may be accomplished at least in part by a dipole-driving method, wherein the gate dielectric layer is dipole-driven doped. For some IC applications, dipole driving may allow the transistor to achieve a different threshold voltage than a transistor that does not perform the dipole driving process. The transistors for which the dipole-driving process is performed may be referred to as dipole-driving transistors and the other transistors for which the dipole-driving is not performed may be referred to as corresponding transistors, and their differently tuned threshold voltages are specifically configured to facilitate their intended function in different circuit applications.

However, in some cases, dipole-driven dopants (e.g., aluminum) may be present in a metal gate electrode formed on the gate dielectric layer (assuming undoped) of the corresponding transistor. When the gate dielectric is in direct contact with the metal electrode, atoms of the dipole driven dopant (e.g., aluminum atoms) may diffuse from the metal gate electrode into the gate dielectric layer, causing the gate dielectric layer of the corresponding transistor to become partially doped, which is not desirable. For example, the dipole-driving process may use aluminum oxide (AlO _x), titanium aluminum nitride (Ti _xAl_yN_z), or aluminum nitride (AlN _x) as the dopant source. Aluminum from these materials may diffuse into the gate dielectric layer. Such unintentional diffusion may reduce the threshold voltage difference between the dipole-driven transistor and the corresponding transistor, which is undesirable because it may adversely interfere with the intended function of the counterpart transistor and/or the dipole-driven transistor in its circuit application.

To address the above problems, the present disclosure implements an aluminum-free conductive layer between the gate dielectric layer and the metal gate electrode. Such a layer may block (or at least reduce) the undesired diffusion of the above-mentioned aluminum, which helps the dipole drive-in transistor and the corresponding transistor to maintain their intended threshold voltage difference. Since such a layer is also conductive, its implementation does not excessively increase parasitic resistance. Thus, device performance may be optimized. Various aspects of the disclosure will now be discussed in more detail below.

Fig. 1A-1C will describe the basic structure of an example FinFET and GAA device. Referring now to fig. 1A and 1B, a three-dimensional perspective view and a top view of a portion of an Integrated Circuit (IC) device 90 are shown, respectively. IC device 90 may be an intermediate device fabricated during processing of the IC or a portion thereof, which may include Static Random Access Memory (SRAM) and/or other logic circuitry, passive components such as resistors, capacitors, and inductors, such as p-type FETs (PFETs), n-type FETs (NFETs), finfets, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other memory cells. The present disclosure is not limited to any particular number of devices or device regions, or any particular device configuration, unless otherwise required. For example, although the IC device 90 is shown as a three-dimensional FinFET device, the concepts of the present disclosure may also be applied to planar FET devices or GAA devices.

Referring to fig. 1a, an ic device 90 includes a substrate 110. The substrate 110 may include an elemental semiconductor such as silicon, germanium, and/or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; alloy semiconductors such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP and/or other suitable materials. The substrate 110 may be a single layer of material having a uniform composition. Alternatively, the substrate 110 may include multiple material layers having similar or different compositions suitable for use in IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source/drain regions, may be formed in the substrate 110 or on the substrate 110. The doped region may be doped with an n-type dopant (such as phosphorus or arsenic) and/or a p-type dopant (such as boron) depending on design requirements. The doped regions may be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a double-well structure, or using raised structures. The doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

A three-dimensional active region 120 is formed on the substrate 110. Active region 120 is an elongated fin structure protruding upward from substrate 110. As such, the active region 120 may be interchangeably referred to hereinafter as the fin structure 120. Fin structure 120 may be fabricated using suitable processes including photolithography and etching processes. The photolithography process may include forming a photoresist layer on the substrate 110, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element (not shown) including the photoresist. A recess is then etched into the substrate 110 using the mask element, leaving a fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive Ion Etching (RIE), and/or other suitable processes. In some embodiments, fin structure 120 may be formed by a double patterning or multiple patterning process. Typically, a double patterning or multiple patterning process combines lithography and a self-aligned process, allowing creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithography process. For example, a layer may be formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned layer using a self-aligned process. The layer is then removed and the remaining spacers or mandrels may then be used to pattern fin structure 120.

IC device 90 also includes source/drain features 122 formed over fin structure 120. Source/drain features 122 may include an epitaxial layer epitaxially grown over fin structure 120. IC device 90 also includes an isolation structure 130 formed over substrate 110. The isolation structures 130 electrically separate the various components of the IC device 90. Isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), low-k dielectric materials, and/or other suitable materials. In some embodiments, the isolation structure 130 may include Shallow Trench Isolation (STI) features. In one embodiment, isolation structures 130 are formed by etching trenches into substrate 110 during formation of fin structures 120. The trenches may then be filled with the isolation material described above, followed by a Chemical Mechanical Planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures may also be implemented as isolation structure 130. Alternatively, the isolation structure 130 may comprise a multi-layer structure, for example, with one or more thermal oxide liner layers.

The IC device 90 further includes a gate structure 140, the gate structure 140 being formed on three sides of the channel region of each fin 120 and engaging the fin structure 120. Gate structures 140 may be dummy gate structures (e.g., comprising an oxide gate dielectric and a polysilicon gate electrode), or they may be HKMG structures comprising a high-k gate dielectric and a metal gate electrode, wherein the HKMG structures are formed by replacing the dummy gate structures. Although not depicted herein, the gate structure 140 may include additional layers of material, such as an interfacial layer, a capping layer, other suitable layers, or a combination thereof, over the fin structure 120.

Referring to fig. 1B, the plurality of fin structures 120 are oriented longitudinally in the X-direction and the plurality of gate structures 140 are oriented longitudinally in the Y-direction (i.e., generally perpendicular to the fin structures 120). In many embodiments, IC device 90 includes additional components such as gate spacers disposed along sidewalls of gate structure 140, a hard mask layer disposed over gate structure 140, and many other components.

It should also be appreciated that the various aspects of the present disclosure discussed below may be applied to multi-channel devices, such as full-gate-all-around (GAA) devices. Fig. 1C shows a three-dimensional perspective view of an example GAA device 150. For reasons of consistency and clarity, similar components in fig. 1C and 1A-1B will be labeled the same. For example, an active region such as fin structure 120 rises vertically upward in the Z-direction from substrate 110. Isolation structures 130 provide electrical separation between fin structures 120. Gate structure 140 is located over fin structure 120 and over isolation structure 130. A mask 155 is located over the gate structure 140 and gate spacers 160 are located on sidewalls of the gate structure. A capping layer 165 is formed over the fin structure 120 to protect the fin structure 120 from oxidation during formation of the isolation structure 130.

A plurality of nanostructures 170 are disposed over each fin structure 120. The nanostructures 170 may comprise nanoplates, nanotubes or nanowires, or some other type of nanostructure that extends horizontally in the X-direction. The portion of the nanostructure 170 under the gate structure 140 may serve as a channel for the GAA device 150. Dielectric internal spacers 175 may be disposed between nanostructures 170. Furthermore, although not shown for simplicity, each nanostructure 170 may be surrounded by a gate dielectric and a gate electrode wrap. In the illustrated embodiment, the portion of the nanostructure 170 that is external to the gate structure 140 may serve as the source/drain feature of the GAA device 150. However, in some embodiments, successive source/drain features may be epitaxially grown over portions of fin structure 120 outside of gate structure 140. Regardless, conductive source/drain contacts 180 may be formed over the source/drain features to provide electrical connection thereto. An interlayer dielectric (ILD) 185 is formed over the isolation structure 130 and surrounding the gate structure 140 and the source/drain contacts 180.

It should be appreciated that whether the transistors of the IC are implemented as finfets of fig. 1A-1B or GAA devices of fig. 1C, they may benefit from the concepts of the present disclosure, as discussed in more detail below.

Fig. 2-22 are a series of schematic partial cross-sectional side views illustrating a process flow for fabricating an example IC device 200 according to various embodiments of the disclosure. Specifically, fig. 2 to 8 show a process flow corresponding to the first embodiment of the present disclosure, fig. 9 to 15 show a process flow corresponding to the second embodiment of the present disclosure, and fig. 15 to 22 show a process flow corresponding to the third embodiment of the present disclosure.

Referring now to fig. 2, an ic device 200 includes vertical stacks of multiple transistors, such as vertical stack 210 and vertical stack 211. Each of the vertical stacks 210-211 of transistors may be associated with a different threshold voltage (Vt) and/or may be configured or used for different circuit applications. In the illustrated embodiment, vertical stack 210 is the portion of a Complementary Field Effect Transistor (CFET) that does not have (or will not have) a dipole drive-in, and vertical stack 211 is the portion of a CFET that has (or will have) a dipole drive-in. As such, the transistors in vertical stack 210 may also be referred to as CFET corresponding devices, and the transistors in vertical stack 211 may also be referred to as CFET drive-in devices.

Vertical stacks 210 and 211 each include one or more n-type transistors (e.g., NFETs) and one or more p-type transistors (e.g., PFETs). For example, vertical stack 210 includes NFETs and PFETs disposed vertically above the NFETs. NFETs may include multiple channel elements 120A-120b and pfets may include multiple channel elements 120C-120D. Channel elements 120A-120D are part of the active region. Channel components 120A-120D may be patterned into nanostructured channels, such as nanoplatelets, nanotubes, nanowires, nanorods, and the like. Each of the channel components 120 to 120D may include a semiconductor material, for example, a silicon (Si) material, a silicon germanium (SiGe) material, or a group III-V compound (e.g., a compound including an element from group III of the periodic table and an element from group V of the periodic table).

Similar to vertical stack 210, vertical stack 211 also includes NFETs and PFETs disposed over the NFETs. The NFETs of the vertical stack 211 may include a plurality of channel elements 120E-120F, and the PFETs in the vertical stack 211 may include a plurality of channel elements 120G-120H, wherein each of the channel elements may be patterned into nanostructured channels comprising semiconductor material, such as nanoplates, nanotubes, nanowires, nanorods, and the like.

It is understood that each of the NFETs and PFETs of the vertical stacks 210 and 211 may optionally include more than two channel elements. For example, NFETs of the vertical stack 210 may optionally include additional channel components between the channel components 120A and 120B, and PFETs in the vertical stack 210 may optionally include additional channel components between the channel components 120C and 120D, and so on for NFETs and PFETs in the vertical stack 211. For simplicity, these optional additional channel elements are represented conceptually in fig. 2 as a plurality of vertical points. It should also be appreciated that while fig. 2 shows the PFET disposed above the NFET in the two vertical stacks 210-211 in this embodiment, the situation may be reversed in other embodiments. For example, in alternative embodiments, NFETs may be disposed over PFETs in one or both of the vertical stacks 210-211.

Channel elements 120A-120H are surrounded (e.g., 360 degrees) by gate dielectric layers 230A-230H, respectively. Gate dielectric layers 230A-230H comprise a high-k dielectric material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. In some embodiments, gate dielectric layers 230A-230H include hafnium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or combinations thereof.

Still referring to fig. 2, a dipole layer forming process 240 is performed on the IC device 200. The dipole layer forming process 240 may utilize one or more deposition processes, such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or combinations thereof, to deposit a p-dipole dopant source layer over the gate dielectric layers 230E-230H of the vertical stack 211. For example, p-dipole dopant source layers 250E, 250F, 250G, and 250H are deposited over gate dielectric layers 230E-230H, respectively. In the cross-sectional side view of fig. 2, p-dipole dopant source layers 250E-250H circumferentially (e.g., at 360 degrees) surround the top, bottom, left side, and right side surfaces, respectively, of their respective gate dielectric layers 230E-230H. In some embodiments, the p-dipole dopant source layers 250E-250H comprise aluminum-based p-dipoles. For example, the p-dipole dopant source layers 250E-250H may include aluminum oxide (AlOx), titanium aluminum nitride (TixAlyNz), aluminum nitride (AlNx), or a combination thereof (where x, y, and z are positive integers). Note that no p-dipole dopant source is formed over the gate dielectric layers 230A-230D of the vertical stack 210 because the transistors in the vertical stack 210 are the corresponding devices (as opposed to the dipole driver devices).

Referring now to fig. 3, a dipole driving-in process 260 is performed to drive atoms of the p-dipole dopant source layers 250E-250H into the gate dielectric layers 230E-230H. In some embodiments, the dipole driving process 260 includes one or more thermal annealing processes. The thermal annealing process helps to facilitate movement of atoms (e.g., aluminum atoms or other suitable atoms) from the p-dipole dopant source layers 250E-250H into the underlying surrounding respective gate dielectric layers 230E-230H. As a result, after the dipole driving process 260 has been performed, the gate dielectric layers 230E-230H of the vertical stack 211 become doped gate dielectric layers 230E-230H. In some embodiments, the gate dielectric layers 230E-230H of the vertical stack 211 become doped with aluminum. In other embodiments, the gate dielectric layers 230E-230H of the vertical stack 211 are dipole materials other than doped aluminum. In contrast, the gate dielectric layers 230A-230D of the vertical stack 210 remain undoped.

Referring now to fig. 4, a removal process 270 is performed on the IC device 200 to remove the remaining portions of the p-dipole dopant source layers 250E-250H. In some embodiments, the removal process 270 may include one or more etching processes that etch away the p-dipole dopant source layers 250E-250H without substantially affecting the remaining components of the IC device 200. For example, one or more etching processes may be configured to have a sufficient amount of etch selectivity between p-dipole dopant source layers 250E-250H and gate dielectric layers 230A-230H. In this way, the p-dipole dopant source layers 250E-250H may be etched away at a much greater rate (e.g., five or ten times) than the gate dielectric layers 230A-230H. As a result, the p-dipole dopant source layers 250E-250H may be completely removed while the gate dielectric layers 230A-230H remain.

Referring now to fig. 5, a deposition process 280 is performed on IC device 200 to form an aluminum-free conductive layer over each gate dielectric layer 230A-230D of vertical stack 210 and each gate dielectric layer 230E-230H of vertical stack 211. For example, in the cross-sectional side view of fig. 5, aluminum-free conductive layers 300A, 300B, 300C, 300D are formed to circumferentially (e.g., 360 degrees) surround gate dielectric layers 230A-230D, respectively, and aluminum-free conductive layers 300E, 300F, 300G, 300H are formed to circumferentially (e.g., 360 degrees) surround gate dielectric layers 230E-230H, respectively. The aluminum-free conductive layers 300A-300H each include a conductive material that is free of aluminum. In some embodiments, aluminum-free conductive layers 300A-300H do not contain any type of p-type material. In some embodiments, aluminum-free conductive layers 300A-300D are titanium nitride (TiN) layers. Note that although in the above embodiments the conductive layers 300A-300H are formed to be aluminum-free, in other embodiments they may be free of other types of P-type dipole materials.

In some embodiments, the deposition process 280 may include ALD, CVD, PVD or a combination thereof. The parameters of the deposition process 280 may be carefully configured to precisely control the thickness 310 of each of the aluminum-free conductive layers 300A-300H. In some embodiments, thickness 310 is in a range between about 0.3 nanometers and about 2.5 nanometers. Thickness 310 is also related to the thickness of one or more other components of IC device 200. For example, each of the gate dielectric layers 300A-300H may have a thickness 320, and each of the gate dielectric layers 230E-230H may have a thickness 321 that is directly related to the thickness 310 of the aluminum-free conductive layers 300A-300D. In some embodiments, the ratio between thickness 310 and thickness 320 is in a range between about 0.1:1 and about 5:1, and the ratio between thickness 310 and thickness 321 is between about 0.1:1 and about 5:1.

The above ranges are not randomly selected, but are specifically configured to optimize the performance of the IC device 200. For example, as will be discussed in more detail below, aluminum-free conductive layers 300A-300H are implemented to prevent or reduce unwanted diffusion (e.g., of aluminum) between gate dielectric layers 230A-230H and metal gate electrodes that will be formed in a subsequent process. If the aluminum-free conductive layers 300A-300H are too thin, they may not sufficiently achieve the intended purpose of blocking unwanted aluminum diffusion. On the other hand, if the aluminum-free conductive layers 300A-300H are too thick, they may consume excessive chip space, which is valuable as device dimensions continue to shrink. Furthermore, if aluminum-free conductive layers 300A-300H are too thick, they may also adversely interfere with the threshold voltage tuning of their respective transistors. Here, the above ranges ensure that the aluminum-free conductive layers 300A-300H are thick enough to sufficiently block unwanted diffusion, while being thin enough to save chip space and not interfere with tuning of the threshold voltage.

Referring now to fig. 6, a gate formation process 340 is performed on the IC device 200 to form a metal gate electrode layer 350 over each aluminum-free conductive layer 300A-300H. For example, the metal gate electrode layer 350 is formed by one or more deposition processes, such as ALD, CVD, or PVD, and in the cross-sectional side view of fig. 6, the metal gate electrode layer 350 circumferentially (e.g., 360 degrees) surrounds each of the aluminum-free conductive layers 300A-300H. Note that in some embodiments, the metal gate electrode layer 350 formed over the vertical stack 210 may be electrically and/or physically separated from the metal gate electrode layer 350 formed over the vertical stack 211.

The metal gate electrode layer 350 comprises an n-type work function metal layer to tune the threshold voltages of the NFETs of the vertical stack 210 and the NFETs of the vertical stack 211. In some embodiments, the n-type workfunction metal layer comprises an aluminum-containing metal, such as titanium aluminum carbide (TixAlyCz). A fill metal layer is formed over the workfunction metal layer and may serve as the main conductive portion of the gate electrode. In some embodiments, the filler metal layer may include titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), cobalt (Co), and the like.

As described above, the gate dielectric layers 230E-230H of the vertical stack 211 are doped with aluminum, but the gate dielectric layers 230A-230D are undoped, due to the performance of the dipole driving process 260 (see fig. 3). If the aluminum-free conductive layers 300A-300H are not formed, undesirable aluminum diffusion may occur between the gate dielectric layers 230E-230H and the work function metal layer of the metal gate electrode layer 350. Such undesired diffusion may result in a lower (and possibly insufficient) difference in aluminum content between the NFETs of vertical stack 210 (i.e., corresponding NFETs) and the NFETs of vertical stack 211 (i.e., drive-in NFETs). In turn, this may result in a lower difference between the expected threshold voltages that should be achieved by the NFETs of vertical stack 210 and the NFETs of vertical stack 211, which would degrade device performance. The aluminum-free conductive layers 300A-300H herein prevent such undesired diffusion, so that differences in aluminum content (and expected threshold voltage) may still be maintained.

Referring now to fig. 7, an etch back process 360 is performed on the IC device 200. The etch back process 360 etches back the metal gate electrode layer 350 for the PFET while portions of the metal gate electrode layer 350 remain over the aluminum-free conductive layers 300A, 300B, 300E, and 300F of the NFET. The etchback process 360 also etches away portions of the aluminum-free conductive layers 300C, 300D, 300G, and 300H of the PFET, exposing the gate dielectric layers 230C, 230D, 230G, and 230H.

Referring now to fig. 8, a gate formation process 370 is performed on IC device 200 to form a metal gate electrode layer 380 for the PFET in vertical stacks 210 and 211. For example, metal gate electrode layer 380 is formed by one or more deposition processes (e.g., ALD, CVD, or PVD), and metal gate electrode layer 380 circumferentially (e.g., 360 degrees) surrounds each of gate dielectric layers 230C, 230D, 230G, and 230H. The metal gate electrode layer 380 includes a p-type work function metal layer to tune the threshold voltages of the PFET of the vertical stack 210 and the PFET of the vertical stack 211. A fill metal layer is also formed over the workfunction metal layer and may serve as the main conductive portion of the gate electrode. In some embodiments, the filler metal layer may include titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), cobalt (Co), and the like.

At this stage of fabrication, the following transistors are formed: corresponding NFETs (NFETs of vertical stack 210), corresponding PFETs (PFETs of vertical stack 210), drive-in NFETs (NFETs of vertical stack 211), and drive-in PFETs (PFETs of vertical stack 211). The threshold voltage of the corresponding NFET is tuned by a combination of the following components: an n-type work function metal layer of metal gate electrode layer 350A, undoped gate dielectric layers 230A and 230B, and aluminum-free conductive layers 300A and 300B. The threshold voltage of the drive-in NFET is tuned by a combination of the following components: an n-type work function metal layer of metal gate electrode layer 350E, p-type doped gate dielectric layers 230E and 230F, and aluminum-free conductive layers 300E and 300F. The threshold voltage of the corresponding PFET is tuned by a combination of: a p-type work function metal layer of metal gate electrode layer 380C, and undoped gate dielectric layers 230C and 230D. The threshold voltage driving the PFET is tuned by a combination of the following components: a p-type work function metal layer of metal gate electrode layer 380G, and p-type doped gate dielectric layers 230G and 230H.

The formation of these transistors (and the different structural arrangements of their respective components) is an inherent result of the fabrication process of fig. 2-8 herein. For example, the deposition of aluminum-free conductive layers 300A-300B and 300E-300F between metal gate electrode layers 350A/350B and gate dielectric layers 120A-120B and 120E-120F is an inherent result of performing deposition process 280 (see FIG. 5 for forming aluminum-free conductive layers 300A-300B and 300E-300F), followed by gate formation process 340 (see FIG. 6) and etch-back process 360 (removing aluminum-free conductive layers 300C-300D and 300G-300H from the PFET).

Note that although aluminum is used herein as an example p-type dipole material, it is not limiting unless otherwise required. In other embodiments where the p-type dipole material is a further element other than aluminum, then the layers 300A-300H may also be implemented as conductive layers that do not contain the further non-aluminum element.

Fig. 2-8 correspond to the process flow of the first embodiment of the present disclosure. Fig. 9-15 correspond to a process flow of a second embodiment of the present disclosure. For simplicity, similar processes and/or components will be labeled the same in fig. 2-15.

Referring now to fig. 9, gate dielectric layers 230A-230H are formed around channel elements 120A-120H of vertical stacks 210 and 211, respectively. The dipole layer forming process 240 is performed to form p dipole dopant source layers 250E-250H to encapsulate the gate dielectric layers 230E-230H, respectively.

Referring now to fig. 10, a dipole-driving process 260 is performed on the IC device 200 to drive atoms (e.g., aluminum atoms) from the p-dipole dopant source layers 250E-250H into the gate dielectric layers 230E-230H, respectively. The gate dielectric layers 230E-230H thus become p-doped (e.g., aluminum doped) gate dielectric layers as a result of performing the dipole driving process 260.

Referring now to fig. 11, a removal process 270 is performed on the IC device 200 to remove the remaining portions of the p-dipole dopant source layers 250E-250H. The manufacturing process performed by the second embodiment so far is substantially the same as the manufacturing process performed by the first embodiment of the present disclosure.

Referring now to fig. 12, a deposition process 280 is performed on the IC device to form an aluminum-free conductive layer. However, unlike the first embodiment, the deposition process 280 only deposits aluminum-free conductive layers 300A-300D for NFETs and PFETs of the vertical stack 210 (i.e., the corresponding device), but does not deposit aluminum-free conductive layers for NFETs or PFETs of the vertical stack 211. In other words, aluminum-free conductive layers 300A-300D are formed circumferentially around gate dielectric layers 230A-230D, respectively, while gate dielectric layers 230E-230H remain exposed after deposition process 280 is performed.

Referring now to fig. 13, a gate formation process 340 is performed on the IC device 200 to form a gate electrode layer 350. Unlike the first embodiment, the gate formation process 340 forms metal gate electrode layers 350A and 350E over only NFETs of both the corresponding device and the drive-in device, respectively, but not over PFETs of the corresponding device or PFETs of the drive-in device. As described above, the metal gate electrode layers 350A and 350E (which may not be in direct contact with each other) may each include an n-type work function metal layer configured to tune the threshold voltages of the NFETs of the corresponding device and the drive-in device.

Referring now to fig. 14, an etching process 390 is performed to remove aluminum-free conductive layers 300C and 300D of the PFET. Etch process 390 is configured to have etch selectivity between the material of aluminum-free conductive layers 300C-300D and the material of gate dielectric layers 230C-230D and 230G-230H or the material of gate electrode layers 350A-350E. For example, aluminum-free conductive layers 300C-300D are etched away at a much faster rate than the material of gate dielectric layers 230C-230D and 230G-230H or gate electrode layers 350A-350E. As a result, gate dielectric layers 230C-230D and 230G-230H and gate electrode layers 350A-350E remain (and are exposed) after etch process 390 is performed.

Referring now to fig. 15, a gate formation process 370 is performed on the IC device 200 to form a gate electrode layer 380. As in the case of the first embodiment, the gate formation process 370 forms gate electrode layers 380C and 380G only over PFETs of both the corresponding device and the driver device. As described above, metal gate electrode layers 380C and 380G (which may not be in direct contact with each other) may each include a p-type work function metal layer configured to tune the threshold voltages of PFETs of the corresponding devices and the drive-in devices.

At this stage of fabrication, the following transistors are formed: corresponding NFETs (NFETs of vertical stack 210), corresponding PFETs (PFETs of vertical stack 210), drive-in NFETs (NFETs of vertical stack 211), and drive-in PFETs (PFETs of vertical stack 211). The threshold voltage of the corresponding NFET is tuned by a combination of the following components: an n-type work function metal layer of metal gate electrode layer 350A, undoped gate dielectric layers 230A and 230B, and aluminum-free conductive layers 300A and 300B. The threshold voltage of the drive-in NFET is tuned by a combination of the following components: an n-type work function metal layer of metal gate electrode layer 350E, and p-type doped gate dielectric layers 230E and 230F. Note that unlike the first embodiment shown in fig. 8, in the second embodiment, the threshold voltage of the drive-in NFETs is tuned without the aluminum-free conductive layers 300E and 300F. Meanwhile, the threshold voltage of the corresponding PFET is tuned by a combination of: a p-type work function metal layer of metal gate electrode layer 380C, and undoped gate dielectric layers 230C and 230D. The threshold voltage driving the PFET is tuned by a combination of the following components: a p-type work function metal layer of metal gate electrode layer 380G, and p-type doped gate dielectric layers 230G and 230H.

The formation of these transistors (and the different structural arrangements of their respective components) is an inherent result of the fabrication process of fig. 9-15 performed herein. For example, the deposition of aluminum-free conductive layers 300A-300B between gate electrode layer 350A and gate dielectric layers 120A-120B is an inherent result of performing deposition process 280 (see FIG. 12 for forming aluminum-free conductive layers 300A-300A and 300C-300D), followed by gate formation process 340 (see FIG. 13) and etching process 390 (see FIG. 14 for removing aluminum-free conductive layers 300C-300D from the PFET).

As described above, fig. 2 to 8 and fig. 9 to 15 correspond to the process flows of the first and second embodiments of the present disclosure, respectively. Fig. 16-22 correspond to a process flow of a third embodiment of the present disclosure. For simplicity, similar processes and/or components will be labeled the same in fig. 2-22.

Referring now to fig. 16, gate dielectric layers 230A-230H are formed around channel elements 120A-120H of vertical stacks 210 and 211, respectively. Dipole layer forming process 240 is performed to form p-dipole dopant source layers 250E-250H to encapsulate gate dielectric layers 230E-230H, respectively.

Referring now to fig. 17, a dipole-driving process 260 is performed on IC device 200 to drive atoms (e.g., aluminum atoms) from p-dipole dopant source layers 250E-250H into gate dielectric layers 230E-230H, respectively. The gate dielectric layers 230E-230H thus become p-doped (e.g., aluminum doped) gate dielectric layers as a result of performing the dipole driving process 260.

Referring now to fig. 18, a removal process 270 is performed on the IC device 200 to remove the remaining portions of the p-dipole dopant source layers 250E-250H. The manufacturing process performed by the third embodiment so far is substantially the same as the manufacturing process performed by the first and second embodiments of the present disclosure.

Referring now to fig. 19, a deposition process 280 is performed on the IC device to form an aluminum-free conductive layer. However, unlike the first or second embodiments, the deposition process 280 only deposits aluminum-free conductive layers 300E-300H for the NFETs and PFETs of the vertical stack 211 (i.e., the drive-in devices), but does not deposit aluminum-free conductive layers for the NFETs or PFETs of the vertical stack 210. In other words, aluminum-free conductive layers 300E-300H are formed circumferentially around gate dielectric layers 230E-230H, respectively, while gate dielectric layers 230-230D remain exposed after deposition process 280 is performed.

Referring now to fig. 20, a gate formation process 340 is performed on the IC device 200 to form a gate electrode layer 350. Similar to the second embodiment (but not the first embodiment), the gate formation process 340 forms metal gate electrode layers 350A and 350E only over NFETs of both the corresponding device and the drive-in device, but not over PFETs of the corresponding device or PFETs of the drive-in device. As described above, the metal gate electrode layers 350A and 350E (which may not be in direct contact with each other) may each include an n-type work function metal layer configured to tune the threshold voltages of the NFETs of the corresponding device and the drive-in device.

Referring now to fig. 21, an etching process 390 is performed to remove aluminum-free conductive layers 300G and 300H of the PFET. Etch process 390 is configured to have etch selectivity between the material of aluminum-free conductive layers 300G-300H and the material of gate dielectric layers 230C-230D and 230G-230H or the material of gate electrode layers 350A-350E. For example, aluminum-free conductive layers 300G-300H are etched away at a much faster rate than the materials of gate dielectric layers 230C-230D and 230G-230H or gate electrode layers 350A-350E. As a result, gate dielectric layers 230C-230D and 230G-230H and gate electrode layers 350A-350E remain (and are exposed) after etch process 390 is performed.

Referring now to fig. 22, a gate formation process 370 is performed on the IC device 200 to form a gate electrode layer 380. As in the case of the first embodiment, the gate formation process 370 forms gate electrode layers 380C and 380G only over PFETs of both the corresponding device and the driver device. As described above, metal gate electrode layers 380C and 380G (which may not be in direct contact with each other) may each include a p-type work function metal layer configured to tune the threshold voltages of PFETs of the corresponding devices and the drive-in devices.

At this stage of fabrication, the following transistors are formed: corresponding NFETs (NFETs of vertical stack 210), corresponding PFETs (PFETs of vertical stack 210), drive-in NFETs (NFETs of vertical stack 211), and drive-in PFETs (PFETs of vertical stack 211). The threshold voltage of the corresponding NFET is tuned by a combination of the following components: an n-type work function metal layer of metal gate electrode layer 350A, undoped gate dielectric layers 230A and 230B. Note that unlike the first embodiment shown in fig. 8 or the second embodiment shown in fig. 15, in the third embodiment, the threshold voltages of the corresponding NFETs are tuned without the aluminum-free conductive layers 300A and 300B. The threshold voltage of the drive-in NFET is tuned by a combination of the following components: an n-type work function metal layer of metal gate electrode layer 350E, p-type doped gate dielectric layers 230E and 230F, and aluminum-free conductive layers 300E and 300F. Meanwhile, the threshold voltage of the corresponding PFET is tuned by a combination of: a p-type work function metal layer of metal gate electrode layer 380C, and undoped gate dielectric layers 230C and 230D. The threshold voltage driving the PFET is tuned by a combination of the following components: a p-type work function metal layer of metal gate electrode layer 380G, and p-type doped gate dielectric layers 230G and 230H.

The formation of these transistors (and the different structural arrangements of their respective components) is an inherent result of the fabrication process of fig. 16-22 performed herein. For example, the deposition of aluminum-free conductive layers 300E-300F between gate electrode layer 350E and gate dielectric layers 120E-120F is an inherent result of performing deposition process 280 (see FIG. 19 for forming aluminum-free conductive layers 300E-300F and 300G-300H), followed by gate formation process 340 (see FIG. 20) and etch process 390 (see FIG. 21 for removing aluminum-free conductive layers 300G-300H from the PFET).

It will be appreciated that while fig. 2-22 illustrate the case where the PFET is vertically above the NFET, they may be interchanged in other embodiments. It should also be appreciated that while the aluminum-free conductive layer is implemented for a bottom transistor (e.g., NFET herein), in embodiments where the NFET is implemented vertically above the PFET, the aluminum-free conductive layer may also be implemented for a top transistor.

It should also be appreciated that various aspects of the present disclosure (e.g., implementing an aluminum-free conductive layer to block aluminum diffusion) may be applied not only to GAA and FinFET devices, but also to Complementary Field Effect Transistors (CFETs). In this regard, fig. 23-27 are a series of schematic partial cross-sectional side views illustrating an example process flow of fabricating an example CFET 400 according to an embodiment of the disclosure.

Referring to fig. 23, cfet 400 includes a substrate 410, substrate 410 may be an embodiment of substrate 110 described above. In some embodiments, the substrate 410 may be a silicon substrate. A plurality of alternating semiconductor layers 430 and 431 are formed on the substrate 410. In some embodiments, semiconductor layer 430 comprises silicon germanium (SiGe) and semiconductor layer 431 comprises silicon (Si). Note that one of the semiconductor layers 430A, while having a SiGe material composition, contains a higher SiGe content or concentration than the rest of the semiconductor layer 430. As will be discussed in more detail below, this semiconductor layer 430A will be replaced with a trench isolation structure in a subsequent process. It is understood that the number of semiconductor layers 430 and 431 is not necessarily limited to the number shown in fig. 23, and that any other suitable number of semiconductor layers 430 or 431 may be implemented in other embodiments.

Portions of semiconductor layer 431 are patterned into nanostructure channels 431, e.g., nanoplates, nanotubes, nanowires, nanorods, etc. A dummy gate structure 440 is formed over the uppermost one of the nanostructure channels 431. In some embodiments, dummy gate structure 440 may include a polysilicon dummy gate electrode. Each dummy gate structure 440 may be patterned by one or more hard mask layers 450, and the hard mask 450 may include one or more dielectric materials. Gate spacers 460 are formed on sidewalls of the dummy gate structure 440. The gate spacer 460 may also include a suitable dielectric material. In some embodiments, each of the gate spacers 460 may include multiple gate spacer layers, but are not specifically shown here for simplicity. Note that a plurality of openings 470 are formed to divide the components of CFET 400 into individual stacks, with each stack having its own dummy gate structure 440.

Still referring to fig. 24, internal spacers 480 are also formed vertically between nanostructure channels 431. An inner spacer 480 is also disposed at opposite ends of each remaining portion of the semiconductor layer 430. The inner spacer 480 may also include a suitable dielectric material.

Referring now to fig. 25, source/drain regions 490 and 510 are formed in openings 470 and over isolation structures 500. As used herein, the source/drain regions 490 or "S/D regions" may refer to the source or drain of a transistor device. It may also refer to a region that provides a source and/or drain for multiple transistor devices. Each of the source/drain regions 490 and 510 may directly abut a side surface of one or more nanostructure channels 431 of the top device of the CFET 400, as well as a side surface of one or more of the inner spacers 480 of the top device of the CFET 400. The source/drain regions 490 are part of the bottom device of the CFET 400. Thus, the source/drain regions 490 may also be referred to as bottom source/drain regions 490. Source/drain regions 510 are part of the top device of CFET 400. Thus, the source/drain regions 510 may also be referred to as top source/drain regions 510. Note that isolation structures 500, which may include a dielectric liner layer (e.g., an etch stop layer) and a main dielectric feature formed on the dielectric liner layer, are disposed between and provide electrical isolation between bottom source/drain regions 490 and top source/drain regions 510. In some embodiments, the dielectric liner and the dielectric component may comprise different types of dielectric materials.

An etch stop layer 520 is formed over the top source/drain regions 510 in the openings 470. An interlayer dielectric (ILD) 530 is formed in the opening 470 over the etch stop layer 520. ILD 530 may also be referred to as ILD0. The etch stop layer 520 and ILD 530 may comprise different types of dielectric materials. The etch stop layer 520 and ILD 530 may be planarized by a Chemical Mechanical Polishing (CMP) process to planarize their upper surfaces.

Still referring to fig. 25, the dummy gate structure 440 is removed, for example, by one or more etching processes. The etching process is configured to have sufficient etch selectivity between the dummy gate structure 440 (e.g., polysilicon) and the materials of the gate spacer 460, the etch stop layer 520, and the ILD 530, which may all comprise a dielectric material. Thus, the removal of dummy gate structure 440 does not substantially affect gate spacer 460, etch stop layer 520, and ILD 530. Accordingly, the opening 550 may be formed by removing the dummy gate structure 440.

Semiconductor layer 430 (e.g., comprising SiGe) is also removed, for example, using one or more etching processes. Thereafter, a gate structure 640 for the bottom device of CFET 400 is formed. For example, gate structure 640 may include a gate dielectric structure 650 and a gate electrode 660 formed to replace removed semiconductor layer 430 and removed dummy gate structure 440 of the bottom device. Note that portions of gate dielectric structure 650 may also serve as gate dielectric structures for top-level devices of CFET 400. However, the gate of the top device of CFET 400 has not yet been formed. For example, one or more etch back processes may be performed to etch back the gate electrode 660 located in the top device region so that empty space occupies a portion of the gate electrode of the top device that will ultimately become the CFET at this time.

As shown in fig. 25, a trench isolation structure 700 is formed between each pair of bottom and top devices of CFET 400. As described above, the channel isolation structure 700 is formed instead of the removed semiconductor layer 430A having a higher SiGe content. The channel isolation structure 700 may include a dielectric material and, along with the internal spacers 480, may help provide electrical isolation between the nanostructure channel 431 of the bottom device and the nanostructure channel 431 of the top device of the CFET 400.

Referring now to fig. 26, a gate structure 740 is formed for the top device of CFET 400. The gate structure 740 may include a gate dielectric structure 650 (previously formed in fig. 25) and a gate electrode 760 that collectively fill the opening formed by removing the semiconductor layer 430 of the top device and removing the dummy gate structure 440.

The processes discussed above with reference to fig. 2-22 may be used to form gate structures 640 and/or 740. For example, the gate dielectric structure 650 may be implemented as an embodiment of one of the gate dielectric layers 230A-230H discussed above with reference to fig. 2-22, which may be undoped or doped (e.g., doped with aluminum), depending on whether the CFET 400 herein is a corresponding device or a dipole driven device. The gate electrode layers 660/760 may also be implemented as embodiments of the metal gate electrode layers 350 or 380 described above. Furthermore, although not specifically shown herein for simplicity, it should be understood that the aluminum-free conductive layer 300A/300B or aluminum-free conductive layer 300E/300F discussed above may be implemented between the gate dielectric structure 650 and the gate electrode 660, or between the gate dielectric structure 650 and the gate electrode 760, depending on whether the bottom device or the top device is an NFET.

Still referring to fig. 26, a self-aligned contact (SAC) 780 may also be formed over the gate structure 740. SAC 780 completely fills opening 550 formed by removing dummy gate structure 440. In some embodiments, SAC 780 may comprise a dielectric material.

Referring now to fig. 27, portions of ILD 530 and etch stop layer 520 are removed, thereby exposing the upper surfaces of source/drain regions 510. Thereafter, source/drain contacts 790 are formed over the source/drain regions 510 to provide electrical connection to the source/drain regions 510. In some embodiments, a silicide layer may be formed between the source/drain region 510 and the source/drain contact 790 to reduce the resistance of the source/drain contact 7900.

It is understood that additional processes may be performed to continue manufacturing CFET 400. For example, a conductive gate contact (e.g., extending vertically through SAC 780) may be formed to provide an electrical connection to gate structure 740. The form-packaging process may also be performed to continue the packaging of CFET 400.

Fig. 28 illustrates an integrated circuit manufacturing system 900 that may be used to perform the manufacturing processes discussed above with reference to fig. 2-22 and/or to manufacture the CFET 400 in accordance with embodiments of the present disclosure. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916 …, N connected by a communication network 918. The network 918 may be a single network or may be a variety of different networks, such as an intranet and the Internet, and may include both wired and wireless communication channels.

In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a process engineer controlling a process and related recipes, or an equipment engineer monitoring or adjusting the conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing a photolithography process to define gate spacers of an SRAM device; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents a high-level process control module associated with process tool 910 as well as yet other process tools; and entity 916 represents a sampling module associated with processing tool 910.

Each entity may interact with other entities and may provide integrated circuit manufacturing, process control, and/or computing capabilities to and/or receive such capabilities from other entities. Each entity may also include one or more computer systems for performing computations and performing automation. For example, the high-level processing control module of entity 914 can comprise a plurality of computer hardware with software instructions encoded therein. Computer hardware may include hard drives, flash drives, CD-ROMs, RAM memories, display devices (e.g., monitor), input/output devices (e.g., mouse and keyboard). The software instructions may be written in any suitable programming language and may be designed to perform a specific task.

Integrated circuit manufacturing system 900 is capable of interactions between entities to enable Integrated Circuit (IC) manufacturing and advanced process control for IC manufacturing. In one embodiment, advanced process control includes adjusting processing conditions, settings, and/or recipes for one processing tool for an associated wafer based on metrology results.

In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based upon process quality and/or product quality. In yet another embodiment, measurements are measured from selected fields and points of a subset of the process wafers according to an optimal sampling field/point determined based on various characteristics of process quality and/or product quality.

One of the capabilities provided by the IC fabrication system 900 may enable collaboration and information access in the areas of design, engineering and processing, metrology and advanced process control, etc. Another capability provided by the IC fabrication system 900 may integrate systems between facilities, such as between metrology tools and processing tools. This integration enables the facility to coordinate its activities. For example, integrating the metrology tool and the processing tool may enable more efficient incorporation of manufacturing information into a manufacturing process or APC module, and may enable wafer data to be obtained from in-line or in-situ measurements using the metrology tool integrated into the relevant processing tool.

Fig. 29 is a flow chart of a method 1000 of fabricating a semiconductor device in accordance with aspects of the present disclosure. The method 1000 includes a step 1010 to form a first gate dielectric layer over the first channel element and a second gate dielectric layer over the second channel element. Each of the first gate dielectric layer and the second gate dielectric layer is undoped.

The method 1000 includes a step 1020 for forming a p-dipole dopant source over the second gate dielectric layer but not over the first gate dielectric layer.

The method 1000 includes step 1030 for performing a dipole driving-in process. Atoms of the p-dipole dopant source are driven into the second gate dielectric layer by a dipole-driving-in process such that the second gate dielectric layer is doped.

The method 1000 includes a step 1040 for removing the p-dipole dopant source after the dipole-driving process has been performed.

The method 1000 includes a step 1050 of depositing an aluminum-free conductive layer over at least one of the first gate dielectric layer or the second gate dielectric layer after removing the p-dipole dopant source.

In some embodiments, step 1050 includes depositing a first aluminum-free conductive layer circumferentially surrounding the first gate dielectric layer in a cross-sectional side view, and depositing a second aluminum-free conductive layer circumferentially surrounding the second gate dielectric layer in a cross-sectional side view. In some embodiments, a gate electrode layer is formed that circumferentially surrounds the first aluminum-free conductive layer and the second aluminum-free conductive layer in a cross-sectional side view, wherein the gate electrode layer comprises an n-type work function metal.

In some embodiments, step 1050 includes depositing an aluminum-free conductive layer that circumferentially wraps the first gate dielectric layer but does not wrap over the second gate dielectric layer in a cross-sectional side view. In some embodiments, a gate electrode layer is formed that circumferentially surrounds the aluminum-free conductive layer and the second gate dielectric layer in a cross-sectional side view, wherein the gate electrode layer comprises an n-type work function metal.

In some embodiments, step 1050 includes depositing an aluminum-free conductive layer that circumferentially wraps the second gate dielectric layer but does not wrap over the first gate dielectric layer in a cross-sectional side view. In some embodiments, a gate electrode layer is formed that circumferentially surrounds the aluminum-free conductive layer and the first gate dielectric layer in a cross-sectional side view, wherein the gate electrode layer comprises an n-type work function metal.

In some embodiments, step 1050 includes depositing a titanium nitride layer as the aluminum-free conductive layer.

In some embodiments, the first channel element and the first gate dielectric layer are part of a first n-type transistor and the second channel element and the second gate dielectric layer are part of a second n-type transistor. In some embodiments, a first p-type transistor is formed over the first n-type transistor, a second p-type transistor is formed over the second n-type transistor, a third gate dielectric layer is formed over a third channel element of the first p-type transistor, and a fourth gate dielectric layer is formed over a fourth channel element of the second p-type transistor.

It should be understood that method 1000 may include additional steps performed before, during, or after steps 1010-1050. For example, method 1000 may include the step of forming an n-type metal gate electrode that circumferentially surrounds the first n-type transistor, the second n-type transistor, the first p-type transistor, and the second p-type transistor in a cross-sectional side view. The method 1000 may further include the step of removing a portion of the n-type metal gate electrode surrounding the first p-type transistor and the second p-type transistor in a cross-sectional side view. The method 1000 may further include the step of forming a p-type metal gate electrode over the remaining portion of the n-type metal gate electrode. The p-type metal gate electrode circumferentially surrounds the first and second p-type transistors in cross-sectional side view. As another example, the method 1000 may further include the step of forming an n-type metal gate electrode that circumferentially surrounds the first n-type transistor and the second n-type transistor in cross-sectional side view, but does not surround either the first p-type transistor or the second p-type transistor. The method 1000 may further include the step of forming a p-type metal gate electrode that circumferentially surrounds the first p-type transistor and the second p-type transistor in cross-sectional side view. A p-type metal gate electrode is formed on the n-type metal gate electrode. For simplicity, other additional steps are not discussed in detail herein.

In summary, the present disclosure relates to the realization of aluminum-free conductive layers between the gate dielectric layer and the metal gate electrode of NFET devices. The aluminum-free conductive layer may include a conductive material (other than aluminum) configured to block aluminum diffusion. In some embodiments, aluminum-free conductive layers are implemented for dipole-driving devices and corresponding devices. In some other embodiments, the aluminum-free conductive layer is used only for dipole driving into the device and not for the corresponding device. In other embodiments, the aluminum-free conductive layer is used only for the corresponding device and not for the dipole-driving device. In some embodiments, an aluminum-free conductive layer is implemented for NFET devices, but not for PFET devices formed in the same vertical stack as NFET devices, e.g., as part of a CFET.

Embodiments of the present disclosure provide advantages over conventional CFET devices. However, it should be understood that other embodiments may provide additional advantages, and that not all advantages are necessarily disclosed herein, and that not all implementations require a particular advantage. One advantage is that diffusion of aluminum is reduced. In more detail, aluminum is typically used as a dipole material to provide tuning of different threshold voltages for different transistors. However, the n-type workfunction metal layer may also comprise aluminum. If the aluminum-doped gate dielectric layer is not intended to be in direct contact with an aluminum-containing n-type work function metal layer, undesirable aluminum diffusion may occur between the gate dielectric layer and the n-type work function metal layer of the metal gate electrode. Such undesired diffusion may adversely interfere with tuning of the threshold voltage and/or result in insufficient difference between the threshold voltages between the drive-in transistor and the corresponding transistor. Here, the interposition of an aluminum-free conductive layer between the gate dielectric layer and an aluminum-containing metal gate electrode (e.g., an aluminum-containing work function metal layer) helps to reduce or eliminate unwanted aluminum diffusion. As a result, devices fabricated according to the present disclosure may still achieve their desired tuning of threshold voltage, thereby improving device performance. Other advantages include compatibility with existing manufacturing processes, simplicity of implementation, and low cost.

One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a first n-type transistor and a second n-type transistor. The first n-type transistor includes a first channel element, an undoped first gate dielectric layer disposed over the first channel element, and a first gate electrode disposed over the undoped first gate dielectric layer. The second n-type transistor includes a second channel element and a doped second gate dielectric layer disposed over the second channel element. The second gate dielectric layer is doped with a p-type dipole material. The second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. An aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.

In some embodiments, the first gate dielectric layer circumferentially surrounds the first channel element in a cross-sectional side view; the first gate electrode is circumferentially wrapped around the first gate dielectric layer in a cross-sectional side view; the second gate dielectric layer circumferentially surrounds the second channel element in a cross-sectional side view; the second gate electrode circumferentially surrounds the second gate dielectric layer in a cross-sectional side view; and the first gate electrode or the second gate electrode is wrapped circumferentially around the aluminum-free conductive layer in a cross-sectional side view.

In some embodiments, the first n-type transistor includes a first aluminum-free conductive layer between the first gate dielectric layer and the first gate electrode; and the second n-type transistor includes a second aluminum-free conductive layer between the second gate dielectric layer and the second gate electrode.

In some embodiments, the first n-type transistor but not the second n-type transistor includes an aluminum-free conductive layer between the first gate dielectric layer and the first gate electrode; and the second gate dielectric layer is in direct contact with the second gate electrode.

In some embodiments, the second n-type transistor but not the first n-type transistor includes an aluminum-free conductive layer between the second gate dielectric layer and the second gate electrode; and the first gate dielectric layer is in direct contact with the first gate electrode.

In some embodiments, the aluminum-free conductive layer is also free of p-type material.

In some embodiments, the aluminum-free conductive layer comprises titanium nitride.

In some embodiments, the first gate dielectric layer has a first thickness; the second gate dielectric layer has a second thickness; the aluminum-free conductive layer has a third thickness; the ratio between the third thickness and the first thickness is in a range between about 0.1:1 and about 5:1; and a ratio between the third thickness and the second thickness is in a range between about 0.1:1 and about 5:1.

In some embodiments, the semiconductor device further comprises: a first p-type transistor disposed over the first n-type transistor, wherein the first p-type transistor comprises: a third channel assembly; a third gate dielectric layer disposed over the third channel element, wherein the third gate dielectric layer is undoped; and a third gate electrode disposed over the third gate dielectric layer, wherein the third gate electrode is in direct contact with the third gate dielectric layer; and a second p-type transistor disposed over the second n-type transistor, wherein the second p-type transistor comprises: a fourth channel assembly; a fourth gate dielectric layer disposed over the fourth channel element, wherein the fourth gate dielectric layer is doped with a p-type dipole material; and a fourth gate electrode disposed over the fourth gate dielectric layer, wherein the fourth gate electrode is in direct contact with the fourth gate dielectric layer.

Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a first vertical stack of transistors. The first vertical stack of transistors includes a first n-type transistor and a first p-type transistor. The semiconductor device includes a second vertical stack of transistors. The second vertical stack of transistors includes a second n-type transistor and a second p-type transistor. The first n-type transistor and the first p-type transistor include undoped gate dielectric layers. The second n-type transistor and the second p-type transistor include doped gate dielectric layers. At least one of the first n-type transistor or the second n-type transistor is circumferentially surrounded by a conductive layer that is free of dipole material. An n-type metal gate electrode circumferentially surrounds the conductive layer.

In some embodiments, the doped gate dielectric layer is doped with aluminum; and the conductive layer is free of aluminum and comprises titanium nitride.

In some embodiments, the first p-type transistor and the second p-type transistor are not circumferentially surrounded by the conductive layer, and wherein one but not both of the first n-type transistor or the second n-type transistor are circumferentially surrounded by the conductive layer.

Another aspect of the present disclosure relates to a method of manufacturing a semiconductor device. A first gate dielectric layer is formed over the first channel element and a second gate dielectric layer is formed over the second channel element. The first gate dielectric layer and the second gate dielectric layer are each undoped. A p-dipole dopant source is formed over the second gate dielectric layer but not over the first gate dielectric layer. A dipole driving-in process is performed. Atoms of the p-dipole dopant source are driven into the second gate dielectric layer by a dipole-driving process such that the second gate dielectric layer is doped. The p-dipole dopant source is removed after the dipole driving process has been performed. After removing the p-dipole dopant source, an aluminum-free conductive layer is deposited over at least one of the first gate dielectric layer or the second gate dielectric layer.

In some embodiments, depositing includes depositing a first aluminum-free conductive layer circumferentially surrounding the first gate dielectric layer in a cross-sectional side view, and depositing a second aluminum-free conductive layer circumferentially surrounding the second gate dielectric layer in a cross-sectional side view, and wherein the method further comprises: forming a gate electrode layer circumferentially surrounding the first aluminum-free conductive layer and the second aluminum-free conductive layer in a cross-sectional side view, wherein the gate electrode layer comprises an n-type work function metal.

In some embodiments, depositing includes depositing an aluminum-free conductive layer that circumferentially wraps around the first gate dielectric layer but not over the second gate dielectric layer in a cross-sectional side view, and wherein the method further includes: a gate electrode layer is formed that circumferentially wraps around both the aluminum-free conductive layer and the second gate dielectric layer in a cross-sectional side view, wherein the gate electrode layer comprises an n-type work function metal.

In some embodiments, depositing includes depositing an aluminum-free conductive layer that circumferentially wraps around the second gate dielectric layer but not over the first gate dielectric layer in a cross-sectional side view, and wherein the method further includes: a gate electrode layer is formed that circumferentially surrounds the aluminum-free conductive layer and the first gate dielectric layer in a cross-sectional side view, wherein the gate electrode layer comprises an n-type work function metal.

In some embodiments, depositing the aluminum-free conductive layer includes depositing a titanium nitride layer as the aluminum-free conductive layer.

In some embodiments, the first channel element and the first gate dielectric layer are part of a first n-type transistor; the second channel element and the second gate dielectric layer are part of a second n-type transistor; and the method further comprises: forming a first p-type transistor over the first n-type transistor and a second p-type transistor over the second n-type transistor includes forming a third gate dielectric layer over a third channel element of the first p-type transistor and forming a fourth gate dielectric layer over a fourth channel element of the second p-type transistor.

In some embodiments, the method further comprises: forming an n-type metal gate electrode which circumferentially surrounds the first n-type transistor, the second n-type transistor, the first p-type transistor and the second p-type transistor in a cross-sectional side view; removing a portion of the n-type metal gate electrode circumferentially surrounding the first p-type transistor and the second p-type transistor; and forming a p-type metal gate electrode over the remaining portion of the n-type metal gate electrode, wherein the p-type metal gate electrode circumferentially surrounds both the first p-type transistor and the second p-type transistor in a cross-sectional side view.

In some embodiments, the method further comprises: forming an n-type metal gate electrode that circumferentially surrounds both the first n-type transistor and the second n-type transistor in a cross-sectional side view but does not surround either the first p-type transistor or the second p-type transistor; and forming a p-type metal gate electrode circumferentially surrounding the first and second p-type transistors in a cross-sectional side view, wherein the p-type metal gate electrode is formed over the n-type metal gate electrode.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

A first n-type transistor, the first n-type transistor comprising:

A first channel assembly;

a first gate dielectric layer disposed over the first channel element, wherein the first gate dielectric layer is undoped; and

A first gate electrode disposed over the first gate dielectric layer; and

A second n-type transistor, the second n-type transistor comprising:

A second channel assembly;

a second gate dielectric layer disposed over the second channel element, wherein the second gate dielectric layer is doped with a p-type dipole material; and

A second gate electrode disposed over the second gate dielectric layer;

Wherein at least one of the first n-type transistor or the second n-type transistor further comprises an aluminum-free conductive layer, and wherein the aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.

2. The semiconductor device of claim 1, wherein:

the first gate dielectric layer circumferentially surrounds the first channel assembly in a cross-sectional side view;

the first gate electrode is circumferentially wrapped around the first gate dielectric layer in a cross-sectional side view;

the second gate dielectric layer circumferentially surrounds the second channel assembly in a cross-sectional side view;

the second gate electrode is circumferentially wrapped around the second gate dielectric layer in a cross-sectional side view; and

The first gate electrode or the second gate electrode is circumferentially wrapped around the aluminum-free conductive layer in a cross-sectional side view.

3. The semiconductor device of claim 1, wherein:

the first n-type transistor includes a first aluminum-free conductive layer between the first gate dielectric layer and the first gate electrode; and

The second n-type transistor includes a second aluminum-free conductive layer between the second gate dielectric layer and the second gate electrode.

4. The semiconductor device of claim 1, wherein:

The first n-type transistor but not the second n-type transistor includes the aluminum-free conductive layer between the first gate dielectric layer and the first gate electrode; and

The second gate dielectric layer is in direct contact with the second gate electrode.

5. The semiconductor device of claim 1, wherein:

The second n-type transistor but not the first n-type transistor includes the aluminum-free conductive layer between the second gate dielectric layer and the second gate electrode; and

The first gate dielectric layer is in direct contact with the first gate electrode.

6. A semiconductor device, comprising:

a first vertical stack of transistors, wherein the first vertical stack of transistors comprises a first n-type transistor and a first p-type transistor;

A second vertical stack of transistors, wherein the second vertical stack of transistors comprises a second n-type transistor and a second p-type transistor;

wherein:

the first n-type transistor and the first p-type transistor include undoped gate dielectric layers;

The second n-type transistor and the second p-type transistor include doped gate dielectric layers;

At least one of the first n-type transistor or the second n-type transistor is circumferentially surrounded by a conductive layer that is free of dipole material; and

An n-type metal gate electrode circumferentially surrounding the conductive layer.

7. The semiconductor device of claim 6, wherein:

The doped gate dielectric layer is doped with aluminum; and

The conductive layer is free of aluminum and comprises titanium nitride.

8. The semiconductor device of claim 6, wherein the first and second p-type transistors are not circumferentially surrounded by the conductive layer, and wherein one but not both of the first or second n-type transistors are circumferentially surrounded by the conductive layer.

9. A method of manufacturing a semiconductor device, comprising:

Forming a first gate dielectric layer over the first channel element and forming a second gate dielectric layer over the second channel element; wherein the first gate dielectric layer and the second gate dielectric layer are each undoped;

forming a p-dipole dopant source over the second gate dielectric layer;

Performing a dipole driving process, wherein atoms of the p-dipole dopant source layer are driven into the second gate dielectric layer by the dipole driving process such that the second gate dielectric layer is doped;

Removing the p-dipole dopant source after the dipole driving-in process has been performed; and

An aluminum-free conductive layer is deposited over at least one of the first gate dielectric layer or the second gate dielectric layer after removing the p-dipole dopant source.

10. The method of claim 9, wherein the depositing comprises depositing a first aluminum-free conductive layer that circumferentially wraps around the first gate dielectric layer in a cross-sectional side view, and depositing a second aluminum-free conductive layer that circumferentially wraps around the second gate dielectric layer in a cross-sectional side view, and wherein the method further comprises:

Forming a gate electrode layer circumferentially surrounding the first aluminum-free conductive layer and the second aluminum-free conductive layer in a cross-sectional side view, wherein the gate electrode layer comprises an n-type work function metal.