CN118338768A

CN118338768A - Storage device, method for improving performance of storage device, and electronic device

Info

Publication number: CN118338768A
Application number: CN202310034160.7A
Authority: CN
Inventors: 杨哲; 郭晨阳; 王伦; 童浩; 涂洒; 陈一峰; 缪向水; 朱晓明
Original assignee: Huawei Technologies Co Ltd; Huazhong University of Science and Technology
Current assignee: Huawei Technologies Co Ltd; Huazhong University of Science and Technology
Priority date: 2023-01-10
Filing date: 2023-01-10
Publication date: 2024-07-12
Also published as: WO2024149079A1

Abstract

Embodiments of the present disclosure provide a storage device, a method for improving performance of the storage device, and an electronic device. A storage device comprising: the memory device includes a memory chip including a plurality of memory cells, an electrical pulse generator, and a processor. The processor is configured to: and triggering the electric pulse generator to apply an electric pulse to the target memory cell, wherein the applied electric pulse enables the leakage current of the target memory cell to be lower than the threshold leakage current. In this way, embodiments of the present disclosure can improve the reliability of the memory device, so that the magnitude of leakage current is within a desired range, for example, after a high temperature process, to meet the requirement of high density integration.

Description

Storage device, method for improving performance of storage device, and electronic device

Technical Field

The present disclosure relates to the field of semiconductor devices, and more particularly, to a memory device, a method for improving performance of the memory device, and an electronic device.

Background

With the explosion of big data and cloud computing, in order to achieve high-density storage, the size of memory cells in a memory array is becoming smaller and the integration density of memory is becoming higher. However, leakage paths exist in the cross matrix structure of the memory array. In some cases, transistors are typically used as gating devices to select the corresponding memory cells to block crosstalk currents from causing malfunction to other memory cells. However, since the transistor is a three-terminal active device, the complexity of the integration process is increased, and the cross array is difficult to be miniaturized due to the large occupied area, so that the high-density integration of the cross array is affected.

In recent years, a gating device (1S) represented by an ott threshold switch (ovonic threshold switching, OTS) replaces a transistor, and can be connected in series with a novel nonvolatile memory cell (1R) such as phase change memory, resistive memory, magnetic memory, etc., to form a cross array structure based on the 1S1R cell. This cross array configuration is beneficial in that the gate devices at both ends save floor space. Furthermore, such devices may also be stacked in 3D layers, further achieving extremely high integration densities. But such gated devices may undergo high temperature processes such as subsequent interconnects during fabrication. This may deteriorate the material properties of such a gating device to cause an increase in leakage current and even disappearance of gating characteristics. At present, the reliability is improved by component optimization through element doping or structural optimization through deposition of a heat-resistant buffer film, but the effect of the scheme is limited and the cost is increased through a complex processing technology.

Disclosure of Invention

In view of the above, embodiments of the present disclosure aim to provide a solution for improving the performance of a memory, for example, for improving the reliability of OTS devices, so that the magnitude of leakage current of OTS devices subjected to high temperature processes is within a desired range, meeting the requirements of high density integration.

According to a first aspect of the present disclosure, a storage device is provided. The storage device includes: the memory device includes a memory chip including a plurality of memory cells, an electrical pulse generator, and a processor. The processor is configured to: and triggering the electric pulse generator to apply an electric pulse to the target memory cell, wherein the applied electric pulse enables the leakage current of the target memory cell to be lower than the threshold leakage current.

As such, in the embodiments of the present disclosure, a memory cell having low reliability or leakage degradation after operation is repaired so that the memory cell after being subjected to a high temperature process can still maintain a switching characteristic, and the magnitude of its leakage current is within a desired range.

In some embodiments of the first aspect, the processor is configured to perform a read operation on the plurality of memory cells to determine a leakage current for each memory cell upon determining a target memory cell of the plurality of memory cells that has a leakage current not lower than a threshold leakage current; and comparing the leakage current of each memory cell with a threshold leakage current, respectively; and determining a memory cell having a leakage current not lower than the threshold leakage current as a target memory cell.

In this way, by determining a memory cell having a leakage current greater than the threshold leakage current as a target memory cell, the degraded memory cell can be repaired with pertinence, and the refresh efficiency can be improved.

In some embodiments of the first aspect, the voltage of the electrical pulse is greater than the threshold voltage of the target memory cell, or the current of the electrical pulse is greater than the threshold current of the target memory cell.

In this way, by applying an electrical pulse having a voltage greater than a threshold voltage or a threshold current to the target memory cell, the OTS material in the degraded target memory cell can be melt quenched and amorphized, thereby eliminating crystallization or component segregation aggregation, resulting in improved reliability of the memory cell.

In some embodiments of the first aspect, the processor is configured to trigger the electrical pulse generator to apply an electrical pulse to the target memory cell when the electrical pulse generator is triggered to apply an electrical pulse to the target memory cell, the voltage of the electrical pulse being greater than the threshold voltage of the target memory cell, or the current of the electrical pulse being greater than the threshold current of the target memory cell. The processor also determines whether the leakage current of the target memory cell is below a threshold leakage current; and in response to the leakage current not being below the threshold leakage current, increasing the magnitude of the voltage or current of the electrical pulse applied to the target memory cell until the leakage current of the target memory cell is below the threshold leakage current.

In this way, an electric pulse of gradually increasing amplitude is applied to the target memory cell with serious leakage, thereby ensuring that the degraded target memory cell can recover the switching characteristics and maintain the corresponding leakage criterion.

In some embodiments of the first aspect, the electrical pulse applied by the electrical pulse generator to the target memory cell is a voltage pulse or a current pulse having a pulse width greater than 20ns and a falling edge less than 100 ns.

Thus, by applying a series of electrical pulses with specific parameters to the degraded target memory cell, the OTS material is relieved from crystallization and composition segregation, e.g., due to heat, such that the leakage current of the target memory cell is reduced, maintaining the switching characteristics.

In some embodiments of the first aspect, the processor is further configured to: determining a first threshold voltage for a first target memory cell in the set of target memory cells; and comparing the first threshold voltage with a reference voltage; and if the first threshold voltage is higher than the reference voltage, instructing the electric pulse generator to apply the electric pulse.

Thus, by comparing the threshold voltage of the target memory cell with the reference voltage, a cell with larger threshold voltage drift is selected, and the target memory cell with inconsistent individual threshold voltage distribution is repaired again, thereby further improving the reliability.

In some embodiments of the first aspect, the reference voltage represents an arithmetic average or a weighted average of threshold voltages of some or all memory cells in the set of target memory cells.

In some embodiments of the first aspect, the processor is configured to apply a first test voltage to the first target memory cell when determining a first threshold voltage for the first target memory cell; and determining a first threshold voltage based on a test result of the first target memory cell in a case where the first test voltage is applied.

In this way, the reference voltage is obtained by determining the threshold voltage of each target memory cell in the target memory set that satisfies the leakage criterion to determine the distribution of the threshold voltages of the target memory cells.

In some embodiments of the first aspect, if the first threshold voltage is higher than the reference voltage, the electrical pulse generator is continuously instructed to apply an electrical pulse to the target memory cell until the first threshold voltage is not higher than the reference voltage.

Thus, the threshold voltage of each target memory cell tends to be uniform by applying a plurality of electric pulses, thereby improving the reliability of the memory chip.

In some embodiments of the first aspect, the processor is configured to: and when the difference between the first threshold voltage and the reference voltage is greater than a predetermined margin, applying an electric pulse to the first target memory cell.

In this way, the target memory cell having a large individual threshold voltage shift is repaired again, and the efficiency can be improved while ensuring the reliability.

According to a second aspect of the present disclosure there is provided an electronic device comprising a controller and a storage device according to the first aspect of the present disclosure, the controller being configured to read data from the storage device or write data to the storage device.

According to a third aspect of the present disclosure, there is provided a method for improving performance of a memory device comprising a memory chip, an electrical pulse generator, a processor, the memory chip comprising a plurality of memory cells. The method comprises the following steps: determining, by the processor, a target memory cell of the plurality of memory cells having a leakage current not less than a threshold leakage current; an electrical pulse is applied by an electrical pulse generator to the target memory cell to cause the leakage current of the target memory cell to be below the threshold leakage current.

According to some embodiments of the third aspect of the present disclosure, the method further comprises: determining a leakage current of the target memory cell in response to the application of the electrical pulse; and increasing the amplitude of the electrical pulse to be applied to the target memory cell in response to the leakage current not being below the threshold leakage current.

Drawings

The above and other features, advantages, and other aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

FIG. 1 illustrates a schematic structure of a memory chip according to an embodiment of the present disclosure;

FIG. 2 shows a current-voltage characteristic graph of an OTS device in accordance with one embodiment of the present disclosure;

FIG. 3 (a) shows a schematic diagram of a structure of a memory cell according to one embodiment of the present disclosure;

Fig. 3 (b) shows a schematic structure of a memory cell according to another embodiment of the present disclosure;

FIG. 4 illustrates a schematic block diagram of a storage device according to one embodiment of the present disclosure;

FIG. 5 illustrates a flowchart of an example method according to one embodiment of the present disclosure;

FIG. 6 (a) shows a current-voltage characteristic graph of a single OTS device after undergoing a high temperature process;

FIG. 6 (b) shows a current-voltage characteristic graph of a single degraded OTS device after a repair operation according to an embodiment of the present disclosure;

FIG. 7 shows a graph of leakage distribution contrast for a plurality of degraded OTS devices after a repair operation according to an embodiment of the present disclosure;

FIG. 8 illustrates a flowchart of an example method according to another embodiment of the present disclosure;

FIG. 9 illustrates a graph of threshold voltage distribution comparisons of different memory cells before and after a refresh operation, according to an embodiment of the present disclosure;

FIG. 10 illustrates a schematic diagram of an example integrated circuit for improving memory in accordance with an embodiment of the present disclosure;

FIG. 11 illustrates a block diagram of a computing device in accordance with various embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below. In addition, even in the case where a specific numerical example is described, it may be a numerical value exceeding the specific numerical value, or may be a numerical value less than the specific numerical value, except that it is theoretically obvious to be limited to the numerical value.

In the following description of the specific embodiments, some repetition is not described in detail, but it should be understood that the specific embodiments have mutual references and may be combined with each other.

As described above, the memory cell is degraded in reliability due to the gate material such as OTS material being subjected to a high temperature process. One conventional approach is to improve the reliability by doping C, si or other elements into the Ge-As-Se material, such As Ge-Si-As-Se or Ge-Si-As-Te, to achieve high reliability. However, si, se, as are sensitive to moisture in the air, and can easily generate extremely toxic substances during the preparation process. Secondly, the components of the high-reliability system are complex, and especially elements such as Ge, se and the like are easy to migrate and segregate in the repeated erasing and writing process, so that leakage current is increased and the device is invalid. Another conventional approach is to use structural optimization of cushioning wraps, multilayer films, etc. to improve reliability. Such as a multilayer film structure design of Ge/NSbSe. But the range of enhancement of buffer layers or multilayer films is currently limited. It can still be difficult to withstand the high temperature process of 400 ℃ for OTS materials with low crystallization (or glass transition) temperatures. In addition, the deposition cost of the multilayer film technology is higher, reducing the cost advantage. Therefore, the current solutions for improving the reliability thereof have limited improvement effects and bring about increased costs and safety problems.

Embodiments of the present disclosure provide a method for improving performance of a memory. According to the method, the electric pulse generating device is used for applying the electric pulse to the deteriorated memory cell, so that the gating device in the memory cell restores the initial switching characteristic before high-temperature annealing, and the reliability of the 1S1R memory cell can be improved in a simple and efficient manner. That is, in some embodiments, by employing embodiments of the present disclosure, the magnitude of leakage current of a memory cell, for example, that is subjected to a back-end high temperature process (e.g., temperature T > 400 ℃) can be made within a desired range.

Fig. 1 illustrates a schematic structure of a memory chip 100 according to an embodiment of the present disclosure. In some embodiments, memory chip 100 may be implemented as a three-dimensional memory cell cross array, for example, comprising a plurality of memory cells 101-104 arranged in row and column directions. Memory cells 101-104 are connected to respective bit lines BL0, BL1 and respective word lines WL0 and WL1, respectively. It should be understood that only 4 memory cells are shown in fig. 1, but the example embodiments are not limited thereto, and the number of rows (bit lines BL) and columns (word lines WL) may each be any integer greater than 1. Each memory cell may include a memory element and an OTS gating device connected in series therewith. The memory element may comprise at least one of a phase change, a resistive change, or a magnetic tunnel junction memory element, for example. The present disclosure is not limited thereto and the memory element may be any two-terminal memory element that satisfies the circuit requirements.

In one embodiment, the gating device shown in fig. 1 may be a two-terminal gating device having OTS characteristics. OTS devices have typical nonlinear voltage-current (IV) characteristics 200, as shown in fig. 2. When the applied voltage is less than the threshold voltage (Vth), the current in the OTS device is small, remains high-resistance, and is in an off state (off state shown by the dashed line in the figure). When the applied voltage exceeds the threshold, the current in the OTS device increases rapidly, transitioning to a low resistance, and being in an on state (the on state shown by the dashed line in the figure). The OTS device has a holding voltage Vhold and the current of the OTS device does not decrease rapidly, i.e. does not turn off easily (on state shown by solid line in the figure), before the voltage gradually decreases to Vhold. When the voltage decreases below Vhold, the OTS resumes high resistance, in the off state (off state shown by solid line in the figure). The IV characteristics of the OTS device shown in fig. 2 show only the curve of the applied forward voltage as an example. OTS devices also have similar IV characteristics (not shown) when negative voltage is applied as bidirectional threshold switching devices.

In some embodiments, the current at one-half of the threshold voltage Vth of an OTS device is defined as the leakage current of a single device. The smaller the leakage current, the greater the integrable density of the memory array and correspondingly the less power consumption. In some embodiments, if the read current of a 1K crossbar array is 1 microampere (mA), then the leakage current should be below 1 nanoamp (nA) in a single ovonic threshold switching device. In other words, for the 1k×1k crossbar array, the threshold leakage current is 1nA, and the leakage current must be smaller than the threshold leakage current to ensure the normal read/write operation of each memory element. That is, in some embodiments, the threshold leakage current is set according to the size of the memory array and the read current for the array. It should be appreciated that in other embodiments, the current at 1/3 or other partial proportion of the threshold voltage Vth of an OTS device may also be defined as the leakage current of a single device. The present disclosure is not limited in this regard.

The operation of the memory cell according to an embodiment of the present disclosure is described in detail below in conjunction with fig. 3 (a) -3 (b). Fig. 3 (a) shows a schematic structure of a memory cell 300 according to one embodiment of the present disclosure. Before describing the operation of the memory cell 300, the structure of the memory cell as shown in fig. 3 (a) will be described. Memory cell 300 includes an integrated cell structure between word line 301 and bit line 302. The integrated cell structure includes an upper electrode 303, a memory element 304, an upper buffer layer 305, OTS devices 306, a lower buffer layer 307, and a lower electrode 308, which are stacked in this order. The above layer stack is then processed by using appropriate hard mask materials, double exposure lithography, multiple etching protection, ALD filling, and other process means to produce the PCM element integrated cell structure with OTS device as shown in fig. 3 (a).

The upper electrode 303 and the lower electrode 308 are made of, for example, an inert metal material, and both may be made of the same or different materials. The inert metallic material includes: pt, ti, W, au, ru, al, tiW, tiN, taN, irO ₂, ITO, and IZO, or Pt, ti, W, au, ru, al, tiW, tiN, taN, irO ₂, ITO, and IZO, or an alloy material formed by combining any two or more of them. In some embodiments, the film thickness of the upper and lower electrodes may be any thickness from 35nm to 100 nm. The upper and lower buffer layers 305 and 307 may include, for example: the thickness of the amorphous carbon layer (or one or more of C-Si, C-S (Te, S) compounds, and MoTe ₂、MoS₂、MnTe、HfO₂/TaO/Al₂O₃、WTe₂ and WS ₂. The upper and lower buffer layers 305 and 307 may be any thickness from 5nm to 20 nm.

In one embodiment, the memory element 304 may be a Phase Change Memory (PCM) type memory element. The PCM element may be made of GST material along the GeTe-Sb ₂Te₃ pseudobinary line, ternary compounds such as ,Ge₂Sb₂Te₅,Ge₁Sb₄Te₇,Ge₁Sb₂Te₄,Ge₃Sb₂Te₆ and their dopants. PCM elements may also be made by doping Ti, ta, zr, hf, in or the like with Sb ₂Te₃ material. OTS device 306 is a Te/Se/S based binary or multi-element OTS material having the switching characteristics described above, which may include, but is not limited to GeTe, CTe, BTe, siTe, alTe, znTe, cdTe, NTe, mgTe, caTe, gaTe, geS, geSe, and which may be doped with one or more of the following elements: a small amount B, C, N, ge, si, al, zn, ga, S, se, as.

The above materials may be formed using any method of preparation known in the art, and the disclosure is not limited herein. In some embodiments, the OTS material and buffer layer material may be prepared using physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, or metal-organic deposition processes. It is to be understood that the numerical values or numerical ranges described above and elsewhere herein are merely exemplary and are intended to assist the reader in understanding the concepts of the embodiments of the disclosure. Any other suitable value/range of values is possible, and the scope of the present disclosure is not limited in this respect. In addition, the materials/elements exemplified by the embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto.

As described above with respect to fig. 2, when the voltage applied to the OTS device is greater than the threshold voltage Vth or greater than the holding voltage Vhold, the OTS device is in an on state, gating the storage element 304 connected thereto. In this case, the operation of the memory element 304 depends on the magnitude of the voltage applied thereto. When no voltage or a voltage less than Vhold/Vth is applied across the OTS device, the current flowing through the OTS device is minimal and the OTS device is in an off state. Accordingly, the current flowing through the memory element 304 in series with the OTS device is also minimal. If the OTS device deteriorates, causing Vth to become smaller, then when a smaller voltage is applied to the OTS, the OTS will be turned on, thereby gating the memory element 304 in series with the OTS device, i.e., causing malfunction.

Because of this non-linear IV switching characteristic, OTS devices can be integrated into a memory array not only as a gating device, but also to enable nonvolatile storage by switching between high and low resistance states through different polarity electrical operation, as shown in fig. 3 (b). Fig. 3 (b) shows a schematic structure of a memory cell 300' according to another embodiment of the present disclosure. The memory cell 300' has a similar structure to the memory cell 300 in fig. 3 (a). The difference is that OTS device 306 'in memory structure 300' combines the functions of gating and storing, omitting storage element 304 in fig. 3 (a). Therefore, in the preparation process, the whole material can be simplified, the process cost can be further reduced, and meanwhile, the storage density can be further increased due to the structural optimization. The upper and lower electrodes 303' and 308', upper and lower buffer layers 305' and 307' of the memory cell 200' have the same or similar structure/material/composition as the upper and lower electrodes 303 and 308, upper and lower buffer layers 305 and 307 of the memory structure 300. Accordingly, aspects described with respect to fig. 3 (a) with respect to memory structure 300 may be applicable to memory structure 300' in fig. 3 (b), and are not described in detail herein.

Fig. 4 illustrates an example block diagram of a storage device 400 according to one embodiment of this disclosure. Memory device 400 includes a memory chip 402, an electrical pulse generator 406, and a processor 408. Memory chip 402 includes a plurality of memory cells 404. In some embodiments, the structure of the memory unit 404 is the same as or similar to the structure of the memory unit 300 or 300' of fig. 3, and thus various aspects described with respect to fig. 3 may be applied to the memory device of fig. 4, and are not repeated herein.

The processor 408 determines a target memory cell of the plurality of memory cells 404 that has a leakage current not less than the threshold leakage current. The processor 408 performs a read operation on the plurality of memory cells 404 to determine a leakage current for each memory cell, and compares the determined leakage currents with threshold leakage currents, respectively, to determine a memory cell of the plurality of memory cells having a leakage current not lower than the threshold leakage current as a target memory cell. The processor 408 also triggers the electrical pulse generator 406 to apply an electrical pulse to the determined target memory cell such that the leakage current of the target memory cell is below the threshold leakage current.

In some embodiments, the electrical pulses applied by electrical pulse generator 406 include voltage pulses or current pulses having a pulse width greater than 20ns and a falling edge less than 100 ns. The electrical pulses applied by the electrical pulse unit 406 are described in detail below in connection with fig. 5.

Fig. 5 illustrates a flowchart of an example method 500 according to one embodiment of this disclosure. It will be appreciated that the various aspects described above with respect to fig. 1-4 may be selectively applied to the method 500. It should be understood that method 500 may also include additional blocks not shown and/or that certain blocks shown may be omitted. The scope of the present disclosure is not limited in this respect. The method 500 of fig. 5 may be performed, for example, by a computer, and more particularly, by a processor according to instructions stored in a read-only memory, which is a transient memory that stores volatile information in which data is volatile after power failure. It is understood that this read-only memory is different from the memory for which method 500 is directed, which is typically a non-volatile memory. Hereinafter, unless otherwise described, "memory" by default refers to memory for which various embodiments of the present disclosure are directed. Alternatively, the method 500 may be performed by other electronic devices having computing or processing functions, such as by a field programmable gate array (field programmable GATE ARRAY, FPGA), without limitation. It is to be appreciated that the method 500 can be performed after the memory device is manufactured and prior to sale to achieve optimized performance. Alternatively or additionally, it may also be performed in case the memory has deteriorated after the user has used the memory for a period of time.

At block 510, a read operation is performed by processor 408 on memory cells 404 in memory chip 402 to determine a leakage current for each memory cell 404, and the determined leakage currents are compared to threshold leakage currents, respectively, to determine a memory cell of the plurality of memory cells having a leakage current not below the threshold leakage current as a target memory cell. As previously described with respect to fig. 2, the current at 1/2 of the threshold voltage of the OTS device is described as an example of leakage current Ioff. The leakage current Ioff for each memory cell is determined by reading each of the plurality of memory cells 101-104 (shown in fig. 1).

The magnitude of the read voltage depends on the type of gating device in the memory. In some embodiments, taking an OTS device made of phase change material as an example, if the threshold voltage of the OTS device is set to Vth1, the threshold voltage of the phase change material itself in the amorphous state is Vth2. The read voltage of the entire memory cell is Vth1 < Vread < (Vth 1+vth 2). In some embodiments, vth1 ranges between 1V-5V, and Vth2 ranges between 0.5V-4V. In other embodiments, vth1 is about 2V and Vth2 is about 1V. In this embodiment, the read voltage may be slightly higher than the threshold voltage Vth1+0.5v when the read operation is performed.

Referring to FIG. 1, in some embodiments, 1/2 Vread is applied on a selected bit line, e.g., BL0, and-1/2 Vread is applied on a selected word line WL0, at which point the voltage applied on memory cell 101 at the intersection of bit line BL0 and word line WL0 is Vread. Thereby gating in memory cell 101 and performing a read. However, if the leakage current of the memory cell 101 is too large, a large current flows in the neighboring memory cell 102 on the same bit line BL 0. In this case, the memory cell 102 may also be gated, resulting in a read error.

At block 520, the electrical pulse generator 406 is caused to apply an electrical pulse to the target memory cell such that the leakage current of the target memory cell is below the threshold leakage current. The electrical pulse generator 406 may generate the corresponding electrical pulses from pulse waveform data, which may include, for example, at least one of an amplitude, a polarity, a pulse width, a frequency, a duty cycle, a rising edge width, a falling edge width, etc., pulse parameters. In some embodiments, the electrical pulse is a step wave electrical pulse having a magnitude greater than a threshold voltage (current) and a falling edge less than 100ns and a pulse width greater than 1 μs. The target memory cell with a large degradation or leakage current, after being applied with an electrical pulse, causes the OTS material to melt quench but not crystallize, thereby eliminating crystallization or component segregation aggregation due to high temperature heating. Thus, the OTS device is re-operated in an amorphous state, reducing leakage current in the half-gated (1/2 Vread) state, thereby improving the performance of the memory cell integrated with the OTS device. It will be appreciated that the relevant pulse parameters of the electrical pulses described above are merely examples and are not limiting on the scope of the present disclosure. In some other cases, electrical pulses with different parameters may be used for other memory devices to eliminate crystallization or component segregation aggregates caused by high temperature heating, thereby reforming an amorphous state.

Parameters of the repair electric pulse can be set for different memory chips (ots+different memory elements) and different phase change materials and component ratios. In some embodiments, the pulse width is greater than 20ns and the falling edge is less than 100ns. In other embodiments, the pulse width may be greater than 1 μs with a falling edge greater than 8ns for less than 50 seconds. The parameters of the electrical pulses may vary according to different integrated cell structures and materials, i.e., may be other numerical ranges, and the disclosure is not limited in any way to the numerical ranges and sizes herein.

Furthermore, in some embodiments, since the initial degradation levels are different for different memory cells, there is a recovery of the leakage current of individual memory cells to a desired range after only a single application of an electrical pulse. In other embodiments, multiple electrical pulses are applied to restore the leakage current to the desired range for memory cells with higher degradation.

At block 530, in response to the application of the electrical pulse at block 520, a leakage current of the target memory cell is determined by the processor 408 to determine a leakage condition. If the leakage criterion is met ("yes" in the figure), i.e., the leakage current is below the threshold leakage current, then proceed to block 560; if the leakage criterion is not met ("no" in the figure), i.e., the leakage current is still not below the threshold leakage current, then proceed to block 550 to apply an electrical pulse to the memory cell that increases in magnitude by Δv or Δi. In some embodiments, the pulse width, falling edge of the electrical pulse may be the same as the parameters at the time the pulse was last applied. The steps in blocks 530 through 550 are repeated with the amplitude of the electrical pulse increased by nΔV or nΔI until it is determined that the memory cell meets the leakage criterion, i.e., is less than the threshold leakage current, and then proceed to block 560, ending the method.

Fig. 6 (a) shows a current-voltage characteristic diagram 500 of a single gating device after being subjected to a high temperature process. Taking the OTS gate device as an example, when the OTS material is Ge ₁₀Te₉₀、Ge₁₅Te₈₅,C₄Ge₁₄Te₈₂ with a lower crystallization temperature, most of the OTS device becomes low-resistance due to crystallization after the subsequent 400 ℃ annealing of the interconnect, as shown in fig. 6 (a). As the applied voltage increases, the current gradually increases, and at about 0.7V, the current remains constant. The IV curve in fig. 6 (a) is approximately linear and OTS devices lose switching characteristics. The reliability of the memory cell containing the OTS device is reduced.

Fig. 6 (b) shows a current-voltage characteristic graph 500' of the single degraded OTS device of fig. 6 (a) after a repair operation according to an embodiment of the present disclosure. Applying an electrical pulse as described in fig. 5 to the degraded memory cell, the OTS device resumes the switching characteristics again when a pulse with a falling edge of 8ns is applied to a voltage pulse greater than 3V (or greater than 200u current pulse) with a pulse width greater than 500ns, as shown in fig. 6 (b). At this time, the threshold voltage was about 1.6V, and the leakage current was about 10nA. According to the embodiment of the disclosure, the degraded memory cells in the memory array are selected and the continuous electric pulse is applied to perform electric repair, so that the electric leakage generated after a high-temperature process is reduced, and the reliability of the memory array is improved.

Fig. 7 shows a plot 700 of leakage distribution contrast for a plurality of degraded OTS devices after a repair operation according to an embodiment of the present disclosure. A curve 701 shown by a dotted line represents a leakage current distribution after a plurality of memory cells are subjected to a high temperature process. As can be seen from curve 701, the leakage current of most of the memory cells, which account for about 70% or more of the total number of memory cells, is distributed between 100nA and 1 μa. A curve 702 shown by a solid line represents a leakage current distribution after a plurality of memory cells undergo a repair operation. As can be seen from curve 702, the leakage current of 68% of the memory cells has fallen below 10 nA. It can be seen that the leakage current profile of the memory cell has been shifted to the left, i.e., the leakage current is reduced, and the reliability of the memory array as a whole is improved, by undergoing only one repair operation. And OTS devices with optimized leakage distribution are more matched with PCM storage elements with higher requirements on driving current, so that the OTS devices have commercial value in industry.

However, in some embodiments, the first target memory cell and the second target memory cell in the set of target memory cells each satisfy the leakage criterion after undergoing a repair operation. The threshold voltages of both may be different and thus the read operation can only be performed by applying a voltage in accordance with the larger of the two threshold voltages. In this case, a voltage far greater than the threshold voltage thereof may still be applied to the memory cell having a smaller threshold voltage, which may lead to an increase in power consumption and even a read-write error. After performing the repair operation as shown in fig. 5 on the memory cells in the memory, a refresh operation is further applied to make the threshold voltage distributions of the different memory cells uniform, thereby satisfying the uniformity requirement, will be described below with reference to fig. 8.

Fig. 8 illustrates a flowchart of an example method 800 according to another embodiment of the present disclosure. It is to be appreciated that the various aspects described above with respect to fig. 1, 3, 4, and 6 (a) -6b may be selectively applied to the method 800. It should be appreciated that method 800 may also include additional blocks not shown and/or that certain blocks shown may be omitted. The scope of the present disclosure is not limited in this respect. The method 800 may be performed, for example, by a computer, and more particularly, by a processor according to instructions stored in a memory. Alternatively, the method 800 may be performed by other electronic devices having computing or processing functions, such as an FPGA, without limitation of the present disclosure. It is to be appreciated that the method 800 can be performed after the memory device is manufactured and prior to sale to achieve optimized performance. Alternatively or additionally, it may also be performed in case the memory has deteriorated after the user has used the memory for a period of time.

At block 810, a read operation is performed on a memory cell in a memory to determine a leakage current. The decision criteria for the read operation and the leakage current in fig. 8 are the same as or similar to those previously described with respect to fig. 5, and are not described in detail herein.

At block 820, a determination is made as to whether the leakage current of the read memory cell is less than a threshold leakage current. If not less than the threshold current (NO in FIG. 8), which generally means that the memory cell is degraded, a repair operation is required, then proceed to block 830. If less than the threshold leakage current (yes in fig. 8), proceed to block 850.

At block 830, the electrical pulse generating device is caused to apply an electrical pulse to the memory cell having an amplitude greater than a threshold voltage (current) of the memory cell. In this step, the applied electrical pulse has the same or similar parameters as the applied electrical pulse in fig. 5, and the aspects described with respect to blocks 520 to 550 may be applied to blocks 830 to 850, which are not described again.

At block 860, a threshold voltage of the memory cell is determined in response to determining that the memory cell meets the leakage criterion. Determining a threshold voltage of a memory cell includes applying a first test voltage to a first target memory cell to obtain a test result, and determining the first threshold voltage based on the test result. In some embodiments, the memory cell is assumed to be in a low resistance state, i.e., storing a data "1". The test voltage is applied to the memory cell in the low resistance state from small to large, and when the read current is obviously increased, the test voltage at the moment is the first threshold voltage of the first target memory cell. Assuming that the memory cell is in a high resistance state, a large current cannot be read out with vread=first threshold voltage+Δv (Δv < Vth 2). At this time, the write pulse SET is applied to place the memory cell at "1" and then read its first threshold voltage.

At block 860, the threshold voltage is compared to a reference voltage to determine whether the threshold voltage meets a uniformity requirement. In some embodiments, it is determined whether the difference between the threshold voltage of each target memory cell and the reference voltage is less than a margin. In block 870, if the difference is less than the margin (yes in fig. 8), the method ends (proceeding to block 890). If the difference is greater than the margin (no in fig. 8), i.e., the threshold voltage deviation of the memory cell is greater, then proceed to block 880.

In block 880, a power pulse is applied to the memory cell to perform a refresh operation to further improve reliability. In some embodiments, the electrical pulse applied in block 880 and the electrical pulse applied in block 830 may be the same or different, and the disclosure is not limited herein. The operations of blocks 860 through 880 are repeated until the threshold voltages of all memory cells meet the uniformity requirement. The margin may be a percentage or a specific voltage value, which is not limited by the present disclosure. In some embodiments, the reference voltage may be an average of the threshold voltages of some or all of the memory cells in the set of target memory cells. In other embodiments, the reference voltage may also be the variance of the threshold voltages of some or all of the memory cells or other mathematical statistical parameter. The present disclosure does not limit the expression form of the statistical parameter.

Fig. 9 illustrates a threshold voltage distribution versus graph 900 of memory cells in a memory before and after implementing the method described in fig. 8, according to an embodiment of the disclosure. Curve 901 represents the threshold voltage distribution of different memory cells prior to a refresh operation. It can be seen that the distribution of threshold voltages of different memory cells is more diffuse, exceeding 3.5V at maximum and as low as 2V at minimum. In this case, when the memory array is read, the applied voltage is limited, and the reliability of the entire memory array is lowered.

Curve 902 represents the threshold voltage distribution of different memory cells after a refresh operation. It can be seen that the threshold voltage distribution after the refresh operation is uniform for different memory cells, which is around 2.5V. This enables memory cells with greater threshold voltage shifts to be selected and individually corrected to achieve a more uniform threshold voltage across the memory array, thereby improving array uniformity.

Fig. 10 shows a schematic diagram of an example integrated circuit 1000 for improving memory in accordance with an embodiment of the present disclosure. Integrated circuit 1000 may be formed as at least a portion of memory device 400. In one embodiment, integrated circuit 1000 includes, but is not limited to, a read circuit 1001, a PCM-OTS integrated array 1002, and an electrical pulse generating device 1003. The read circuit 1001 is configured to perform a read operation on memory cells in the memory 1002 to obtain a leakage current for each memory cell. The read circuit 1001 also includes a comparator (not shown) configured to compare the leakage current of each memory cell to a threshold leakage current. The read circuit 1001 determines a memory cell whose leakage current is greater than the threshold leakage current as a target memory cell set.

The electric pulse generating means 1003 comprises electric pulse generating means (not shown in the figures). The electric pulse generating device generates a voltage pulse or a current pulse with an amplitude greater than a threshold voltage or a threshold current, a pulse width greater than 20ns and a falling edge less than 100 ns. The electric pulse generating means 1003 applies the above electric pulse to each target memory cell in the target memory cell set to perform the electric repair operation as described above with respect to fig. 5 and 8. It should be appreciated that integrated circuit 900 may also include additional circuitry not shown and/or that some of the circuitry shown may be omitted. The scope of the present disclosure is not limited in this respect.

FIG. 11 illustrates a schematic block diagram of a computing device 1100 that may be used to implement embodiments of the present disclosure. As shown, the device 1100 includes a Central Processing Unit (CPU) 1101 that can perform various suitable actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM) 1102 or loaded from a storage unit 1108 into a Random Access Memory (RAM) 1103. In the RAM 1103, various programs and data required for the operation of the device 1100 can also be stored. The CPU 1101, ROM 1102, and RAM 1103 are connected to each other by a bus 1104. An input/output (I/O) interface 1105 is also connected to bus 1104.

Various components in device 1100 are connected to I/O interface 1105, including: an input unit 1106 such as a keyboard, a mouse, etc.; an output unit 1107 such as various types of displays, speakers, and the like; a storage unit 1108, such as a magnetic disk, optical disk, etc.; and a communication unit 1109 such as a network card, modem, wireless communication transceiver, or the like. The communication unit 1109 allows the device 1100 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The processing unit 1101 performs the various methods and processes described above, such as any of the methods 500 and 800. For example, in some embodiments, any of the methods 500 and 800 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 1108. In some embodiments, some or all of the computer programs may be loaded and/or installed onto device 1100 via ROM 1102 and/or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by CPU 1101, one or more steps of any of the methods 500 and 800 described above may be performed. Alternatively, in other embodiments, CPU 1101 may be configured to perform any of methods 500 and 800 by any other suitable means (e.g., by means of firmware).

The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), etc.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, read Only Memory (ROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

Claims

1. A storage device, the storage device comprising: a memory chip, an electrical pulse generator, and a processor, the memory chip comprising a plurality of memory cells;

The processor is configured to:

Determining a target memory cell of the plurality of memory cells having a leakage current not lower than a threshold leakage current, and

Triggering the electrical pulse generator to apply an electrical pulse to the target memory cell, the applied electrical pulse causing the leakage current of the target memory cell to be lower than the threshold leakage current.

2. The memory device of claim 1, wherein a voltage of the electrical pulse is greater than a threshold voltage of the target memory cell or a current of the electrical pulse is greater than a threshold current of the target memory cell.

3. The memory device of claim 1, wherein the processor is configured to, upon triggering the electrical pulse generator to apply an electrical pulse to the target memory cell:

Triggering the electric pulse generator to apply an electric pulse to the target memory cell, wherein the voltage of the electric pulse is greater than the threshold voltage of the target memory cell, or the current of the electric pulse is greater than the threshold current of the target memory cell;

determining whether a leakage current of the target memory cell is below the threshold leakage current;

In response to the leakage current not being below a threshold leakage current, increasing the voltage or the magnitude of the current of the electrical pulse applied to the target memory cell until the leakage current of the target memory cell is below the threshold leakage current.

4. A memory device according to any one of claims 1 to 3, wherein the processor is configured, in determining a target memory cell of the plurality of memory cells for which the leakage current is not below a threshold leakage current:

Performing a read operation on the plurality of memory cells to determine a leakage current for each memory cell; and

Comparing the leakage current of each memory cell with the threshold leakage current; and

And determining a memory cell with the leakage current not lower than the threshold leakage current as the target memory cell.

5. The memory device of any of claims 1-4, wherein the electrical pulse generator applies voltage pulses or current pulses to the target memory cell that are greater than 20ns in pulse width and less than 100ns in falling edge.

6. The storage device of any of claims 1-5, wherein the processor is configured to:

Determining a first threshold voltage for a first target memory cell of the set of target memory cells; and

Comparing the first threshold voltage with a reference voltage; and

The electrical pulse generator is instructed to apply the electrical pulse if the first threshold voltage is higher than the reference voltage.

7. The memory device of claim 6, wherein if the first threshold voltage is higher than the reference voltage, continuing to instruct the electrical pulse generator to apply electrical pulses to the target memory cell until the first threshold voltage is not higher than the reference voltage.

8. The storage device of claim 6, wherein the processor is further configured to: the electrical pulse is applied to the first target memory cell when the difference between the first threshold voltage and the reference voltage is greater than a predetermined margin.

9. An electronic device comprising a controller and a storage device according to any of claims 1-8, the controller being configured to read data from or write data to the storage device.

10. A method for improving performance of a memory device, the memory device comprising a memory chip, an electrical pulse generator, a processor, the memory chip comprising a plurality of memory cells, the method comprising:

Determining, by the processor, a target memory cell of the plurality of memory cells having a leakage current not less than a threshold leakage current;

triggering an electrical pulse generator by the processor to apply an electrical pulse to the target memory cell to cause a leakage current of the target memory cell to be below the threshold leakage current.

11. The method according to claim 10, wherein the method further comprises:

Determining a leakage current of the target memory cell in response to applying the electrical pulse; and

In response to the leakage current not being below a threshold leakage current, increasing the amplitude of the electrical pulse to be applied to the target memory cell.