CN118335163A - Memory test system, method, device, chip and computer storage medium - Google Patents

Abstract

The disclosure provides a memory test system, a method, a device, a chip and a computer storage medium, and belongs to the technical field of memories. The system comprises: a controller to test the access port and the memory; the test access port is configured to receive an algorithm selection instruction sent by external test equipment and transmit the algorithm selection instruction to the controller, wherein the algorithm selection instruction comprises a target algorithm identifier; the controller is configured to determine at least one instruction to be tested corresponding to the target algorithm identification according to the target algorithm identification, wherein the corresponding relation between a plurality of target algorithm identifications and an instruction set to be tested is prestored in the controller, and at least one instruction to be tested is executed to test the memory. The memory test system capable of realizing flexible switching of various algorithms without modifying a hardware circuit.

Description

Memory test system, method, device, chip and computer storage medium

Technical Field

The present disclosure relates to the field of memory technologies, and in particular, to a memory test system, a method, an apparatus, a chip, and a computer storage medium.

Background

A large amount of memories are designed in the chip, and in order to ensure that each memory has a desired function in design, test simulation needs to be performed on the memories. In the test simulation process of the memory, the selection of a test algorithm is critical, and the test algorithm is used for producing a test vector capable of detecting the failure of the memory.

However, the conventional built-in self-test (Memory Built-IN SELF TEST, MBIST) of the memory is usually implemented by adopting a fixed test algorithm to generate a corresponding test circuit for simulation test, but the test of the memory may be incomplete by adopting only one test algorithm, so that possible faults of the memory are not detected.

Disclosure of Invention

The present disclosure provides a memory test system, method, apparatus, chip, and computer storage medium; the memory test system capable of realizing flexible switching of various algorithms without modifying a hardware circuit.

The technical scheme of the present disclosure is realized as follows:

in a first aspect, the present disclosure provides a memory test system comprising: a controller to test the access port and the memory; the test access port is configured to receive an algorithm selection instruction sent by external test equipment and transmit the algorithm selection instruction to the controller, wherein the algorithm selection instruction comprises a target algorithm identifier; the controller is configured to determine at least one instruction to be tested corresponding to the target algorithm identification according to the target algorithm identification, wherein the corresponding relation between a plurality of target algorithm identifications and an instruction set to be tested is prestored in the controller; and executing at least one instruction to be tested to test the memory. Therefore, when the built-in self-test of the memory is carried out, if the algorithm needs to be switched, the controller can identify the algorithm selection instruction and determine at least one instruction to be tested corresponding to the switched algorithm, so that a hardware circuit does not need to be regenerated, flexible switching of the algorithm can be realized when the memory is tested, and the test of the memory is more comprehensive and has higher test efficiency.

In some embodiments of the present disclosure, the at least one instruction to be tested is a plurality of instructions to be tested; a controller specifically configured to: and determining an instruction sequence to be tested corresponding to the target algorithm identification according to the target algorithm identification. For a plurality of instructions to be tested, determining the execution sequence of the instructions to be tested so as to ensure that the faults of the memory can be accurately detected through the instructions to be tested, and avoiding test report errors or false detection caused by error of the execution sequences of the instructions to be tested.

In some embodiments of the present disclosure, the controller is specifically configured to: and determining a command sequence to be detected corresponding to the target algorithm identifier through an algorithm state machine according to the target algorithm identifier. Because each section of logic implementation needs to occupy a certain physical space in the hardware design, the same instruction to be tested in each algorithm is multiplexed through the algorithm state machine, so that the required hardware resources can be reduced, and the area of the whole circuit is reduced.

In some embodiments of the present disclosure, the memory test system further comprises: the special instruction module is internally provided with a self-test access interface; a special instruction module configured to determine whether a channel between the test access port and the built-in self-test access interface is on; the test access port is specifically configured to transmit an algorithm selection instruction to the built-in self-test access interface under the condition that a channel between the test access port and the built-in self-test access interface is communicated; the built-in self-test access interface is configured to store an algorithm selection instruction into a test data register included in the built-in self-test access interface; the controller is specifically configured to determine at least one instruction to be tested corresponding to the target algorithm identifier based on the target algorithm identifier of the algorithm test instruction in the test data register. The special instruction module can screen the test data, only the specific test data is allowed to reach the controller, and the condition that the test data needs to be screened by the controller is avoided; the built-in self-test access interface can store the received algorithm selection instructions, and when a plurality of algorithm selection instructions are transmitted to the built-in self-test access interface, the test data register can be used for managing the plurality of algorithm selection instructions, so that the test is ensured to be executed according to a preset sequence. The modules work together, so that hardware circuits do not need to be regenerated when algorithm switching is performed, and the memory can be tested by using different algorithms.

In a second aspect, the present disclosure provides a memory testing method, a chip including a controller, a test access port and a memory, applied to the controller, the memory testing method including: receiving an algorithm selection instruction sent by external test equipment from a test access port, wherein the algorithm selection instruction comprises a target algorithm identifier; determining at least one instruction to be tested corresponding to the target algorithm identification according to the target algorithm identification; at least one instruction to be tested is executed to test the memory.

In some embodiments of the present disclosure, the at least one instruction to be tested is a plurality of instructions to be tested; according to the target algorithm identification, determining at least one instruction to be tested corresponding to the target algorithm identification comprises: and determining an instruction sequence to be tested corresponding to the target algorithm identification according to the target algorithm identification.

In some embodiments of the present disclosure, determining, according to a target algorithm identifier, a sequence of instructions to be tested corresponding to the target algorithm identifier includes: and determining a command sequence to be detected corresponding to the target algorithm identifier through an algorithm state machine according to the target algorithm identifier.

In a third aspect, the present disclosure provides a memory test apparatus comprising: the device comprises a receiving module, a determining module and an executing module; the receiving module is configured to receive an algorithm selection instruction sent by external test equipment from the test access port, wherein the algorithm selection instruction comprises a target algorithm identifier; the determining module is configured to determine at least one instruction to be tested corresponding to the target algorithm identifier according to the target algorithm identifier; and the execution module is configured to execute at least one instruction to be tested so as to test the memory.

In a fourth aspect, the present disclosure provides a chip comprising the memory test system of the first aspect.

In a fifth aspect, the present disclosure provides a computer readable storage medium having stored thereon a program or instructions which when executed by a processor performs the steps of the memory testing method according to the second aspect.

In a sixth aspect, the present disclosure provides a computer program product, wherein the computer program product comprises a computer program or instructions which, when run on a processor, cause the processor to execute the computer program or instructions implementing the steps of the memory testing method as described in the second aspect.

The present disclosure provides a memory test system, comprising: a controller to test the access port and the memory; the test access port is configured to receive an algorithm selection instruction sent by external test equipment and transmit the algorithm selection instruction to the controller, wherein the algorithm selection instruction comprises a target algorithm identifier; the controller is configured to determine at least one instruction to be tested corresponding to the target algorithm identifier according to the target algorithm identifier; and executing at least one instruction to be tested to test the memory. Therefore, when the built-in self-test of the memory is carried out, if the algorithm needs to be switched, the controller can identify the algorithm selection instruction and determine at least one instruction to be tested corresponding to the switched algorithm, so that a hardware circuit does not need to be regenerated, flexible switching of the algorithm can be realized when the memory is tested, and the test of the memory is more comprehensive and has higher test efficiency.

Drawings

FIG. 1 is a schematic diagram of a memory test system provided by the present disclosure;

FIG. 2 is a schematic flow chart of a simulation test provided by the present disclosure;

FIG. 3 is a logic diagram of an algorithm state machine executing an instruction under test provided by the present disclosure;

FIG. 4 is a schematic diagram of another memory test system provided by the present disclosure;

FIG. 5 is a flow chart of a memory testing method provided by the present disclosure;

fig. 6 is a block diagram of a memory test device provided in the present disclosure.

Detailed Description

Technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the present disclosure, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

In chip design, memory (memory) occupies a large part, and testing and verifying it is a key step in ensuring the quality of the chip. Memory built-In Self-Test (MBIST) is a built-In Self-Test technique that allows memory to be Self-tested independent of external Test equipment. MBIST is typically combined with Tessent flows to achieve more efficient and automated memory test simulation. Tessent provides a comprehensive memory and logic test solution that supports testing and verification of a variety of memory and logic circuits.

MBIST hardware and logic may be integrated into the memory module during the chip design phase. This includes test controllers, test vector stores, test algorithm logic, and the like. MBIST supports a variety of test algorithms, such as row/column tests, boundary scan tests, data compression tests, etc., which can detect for different memory defect types.

In particular, existing software tools for Integrated Circuit (IC) design and testing typically use some sort of deterministic target algorithm in actual testing, and the tools generate a hardware circuit containing the target algorithm based on the target algorithm, through which a test simulation of the memory is performed.

However, actual fault testing of the memory typically requires testing by a variety of algorithms to ensure that the memory is fully tested to avoid possible faults not being detected. In the related art, when various algorithm tests are required, for example: the memory is tested through the algorithm A and the algorithm B, and a hardware circuit (comprising each test module and a connection relation) corresponding to the algorithm A and a hardware circuit corresponding to the algorithm B are required to be generated respectively. The controller is used for executing a test instruction 1 and a test instruction 2 corresponding to the algorithm A in the hardware circuit corresponding to the algorithm A; in the hardware circuit corresponding to the algorithm B, the controller is used for executing the test instruction 2 and the test instruction 3 corresponding to the algorithm B. That is, in the related art, for each algorithm to be tested, a hardware circuit adapted to the algorithm needs to be generated before testing.

Therefore, when detecting the memory through MBIST, a set of hardware circuits needs to be regenerated each time the algorithm is changed, and then the test is performed, resulting in long test time, low efficiency, and possibly increased cost and time for product development.

To overcome these problems, the present disclosure aims to provide a memory test system capable of implementing flexible switching of various algorithms without modifying hardware circuitry. First, FIG. 1 is a memory test system 10 shown in the present disclosure. As shown in fig. 1, the system includes: test access port 101, controller 102 and memory 103.

The test access port 101 is configured to receive an algorithm selection instruction sent by the external test device, and transmit the algorithm selection instruction to the controller 102.

The algorithm selection instruction comprises a target algorithm identification, wherein the target algorithm identification is used for uniquely indicating one algorithm. The algorithms used for testing in this disclosure are not limited, for example: an algorithm to detect faults by writing and reading a moving bit pattern back and forth in the memory 103; an algorithm for detecting a double bit error by writing a specific checkerboard pattern in the memory 103; an algorithm for detecting a fault in the address decode logic; an algorithm for detecting a significant access error; detecting a random failure in the memory 103 by a random data pattern; algorithms for detecting single bit errors, coupling errors, address decoding errors, etc.; an algorithm for detecting a double bit error; an algorithm for detecting whether the memory cell is stuck at a certain level (high level or low level), and the like.

The controller 102 is configured to determine at least one instruction to be tested corresponding to the target algorithm identifier according to the target algorithm identifier; and executing at least one instruction to be tested to test the memory 103.

In some examples, the flow of the simulation test is as shown in fig. 2, including steps S201 to S206.

S201, executing a testability design flow according to a configured algorithm and a configuration file of a memory, and generating an MBIST hardware circuit.

S202, optimizing an MBIST hardware circuit to obtain the memory test system.

To enable the controller 102 to identify the algorithm selection instruction, the controller 102 provided by the present disclosure includes an input port for receiving the algorithm selection instruction, and the controller 102 is capable of determining a corresponding instruction to be tested based on the received algorithm selection instruction, such that the controller 102 controls execution of the instruction to be tested to complete testing of the memory 103. The goal of optimizing MBIST hardware circuitry is therefore to add an input port in the original controller for receiving the algorithm selection instruction.

S203, performing simulation test based on the memory test system.

S204, whether the simulation test is passed.

If yes, step S205 is executed, otherwise step S203 is executed.

S205, whether a switching algorithm is needed.

If yes, go to step S206, otherwise end.

S206, generating a corresponding algorithm selection instruction according to the switched algorithm.

In the related art, for each algorithm, a testability design flow is executed according to the configured algorithm and the configuration file of the memory 103, so as to generate an MBIST hardware circuit. Therefore, each switching algorithm requires a significant amount of test time. In the present disclosure, only once MBIST hardware circuit is generated for the first time, and then this hardware circuit is optimized to obtain the memory test system of the present disclosure, only the corresponding algorithm selection instruction needs to be generated for each algorithm switching, and the controller 102 can analyze the algorithm selection instruction to determine the corresponding instruction to be tested, so that the hardware circuit does not need to be generated again for each algorithm switching, thereby improving the test efficiency.

In order to enable the controller 102 to determine at least one corresponding instruction to be tested according to the target algorithm identifier, a corresponding relationship between the algorithm identifier and the instruction set to be tested may be preset in the controller 102, or a model capable of determining the instruction set to be tested through the algorithm identifier may be preset in the controller 102, which is not particularly limited in this disclosure.

If there are a plurality of instructions to be tested corresponding to the algorithm, in order to enable the algorithm to accurately detect the corresponding faults, the execution sequence of the plurality of instructions to be tested needs to be determined, so in some embodiments of the present disclosure, at least one instruction to be tested is the plurality of instructions to be tested; the controller 102 is specifically configured to: and determining an instruction sequence to be tested corresponding to the target algorithm identification according to the target algorithm identification.

The controller 102 serially executes each instruction to be tested according to the instruction sequence to be tested to detect the memory 103.

The instruction to be tested corresponding to each algorithm needs layout circuits, such as: the algorithm A corresponds to the to-be-tested instruction 1 to the to-be-tested instruction 3, the algorithm B corresponds to the to-be-tested instruction 1 and the to-be-tested instruction 2, and the algorithm C corresponds to the to-be-tested instruction 1 and the to-be-tested instruction 3. I.e. three corresponding circuits need to be laid out, which complicates the layout of the circuit and leads to an increase in circuit area. To address this issue, in some embodiments of the present disclosure, the controller 102 is specifically configured to: and determining a command sequence to be detected corresponding to the target algorithm identifier through an algorithm state machine according to the target algorithm identifier.

The algorithm state machine disclosed by the disclosure is used for simulating the execution process of various algorithms, including state conversion and condition judgment. The status is used to indicate a particular stage in the algorithm execution, such as: an initial state (state in which the algorithm starts executing), an intermediate state (state in which a certain test instruction is executed), or an end state (state in which the algorithm is completed). Conditions are used to indicate conditions that trigger state transitions, which may be particular attributes of the input data, values of internal variables of the algorithm, etc. The working principle of the algorithm state machine may comprise the following steps: starting, the algorithm is executed from an initial state; judging the condition, and checking whether the specific condition in the current state is met; executing the action, and if the condition is met, executing the corresponding action; state transition, wherein the algorithm is transferred to a new state according to the condition of meeting the condition; repeating: repeating the processes of evaluating condition judgment, executing action and state conversion in a new state; and ending, and when the ending state is reached, ending the algorithm execution.

Illustratively, as shown in FIG. 3, a logic diagram of an instruction to be tested is executed by an algorithm state machine. The start state and the end state are represented in idle states.

In the case where the algorithm is in algorithm a, algorithm B or algorithm C, the transition from the idle state to executing instruction 1 under test. Under the condition that the algorithm is algorithm A or algorithm B, the instruction 1 to be tested is converted into the instruction 2 to be tested after being executed; and under the condition that the algorithm is the algorithm C, converting the execution of the instruction to be tested 1 into the execution of the instruction to be tested 3 after the execution is completed. Under the condition that the algorithm is the algorithm A, the instruction 2 to be tested is converted into the instruction 3 to be tested after being executed; and under the condition that the algorithm is the algorithm B, the to-be-tested instruction 2 is converted into an idle state after being executed. And under the condition that the algorithm is algorithm A or algorithm C, the instruction 3 to be tested is converted into an idle state after being executed.

In hardware design, each segment of logic implementation needs to occupy a certain physical space. The algorithm state machine can reduce the required hardware resources by multiplexing the same instruction to be tested, thereby reducing the area of the whole circuit.

In some embodiments of the present disclosure, as shown in fig. 4, the memory test system further includes: special instruction module 104, built-in self-test access interface 105. A special instruction module 104 configured to determine whether a channel between the test access port 101 and the built-in self-test access interface 105 is on; the test access port 101 is specifically configured to transmit an algorithm selection instruction to the built-in self-test access interface 105 in case a channel between the test access port 101 and the built-in self-test access interface 105 is on; a built-in self-test access interface 105 configured to store an algorithm selection instruction into a test data register included in the test built-in self-test access interface; the controller 102 is specifically configured to determine, based on the target algorithm identification of the algorithm test instruction in the test data register, at least one instruction to be tested corresponding to the target algorithm identification.

The special instruction module 104 contains a single bit shift register that determines the flow path of the test data. Because there are multiple types of test data arriving at the test access port 101, the special instruction module 104 can control the flow direction of the test data between the test access port 101 and the internal test logic, and can select different test paths according to the values in the shift register, so as to realize that the test data carrying the test selection instruction required in the present disclosure is transmitted to the built-in self-test access interface 105, avoiding that various test data are transmitted to the built-in self-test access interface 105, and the controller 102 is required to perform screening processing.

To enable the built-in self-test access interface 105 to transmit algorithm selection instructions to the controller 102, the built-in self-test access interface 105 includes an output port for making algorithm selections. The test data register is used to store the algorithm selection instructions to be loaded into the controller 102. During testing of the memory 103, the test data register distributes the algorithm selection instructions to the input ports of the controller 102 for receiving the algorithm selection instructions. Since it takes a certain time period for the memory 103 to be tested by a certain algorithm, when a plurality of algorithm selection instructions are transmitted to the built-in self-test access interface 105, the test data register may be used to manage the plurality of algorithm selection instructions, ensuring that the test is performed in a predetermined order.

In this way, in the memory test system of the present disclosure, when the algorithm is switched, the algorithm selection instruction may be transmitted to the controller 102 through the external test device, so as to implement the test on the memory 103, without regenerating the hardware circuit for each switching algorithm.

The present disclosure also provides a memory test method applied to a controller 102 in a chip that includes the controller 102, a test access port 101, and a memory 103. As shown in fig. 5, the memory test method includes the following steps S501 to S503.

In step S501, an algorithm selection instruction sent by an external test device is received from a test access port.

The algorithm selection instruction comprises a target algorithm identification.

In step S502, at least one instruction to be tested corresponding to the target algorithm identifier is determined according to the target algorithm identifier. The correspondence between a plurality of target algorithm identifiers and an instruction set to be tested is stored in the controller 102 in advance.

In step S503, at least one instruction to be tested is executed to test the memory.

In some embodiments of the present disclosure, the at least one instruction to be tested is a plurality of instructions to be tested; the step S502 determines at least one instruction to be tested corresponding to the target algorithm identifier according to the target algorithm identifier, which may be specifically implemented in the following step S502 a.

In step S502a, according to the target algorithm identifier, a sequence of instructions to be tested corresponding to the target algorithm identifier is determined.

In some embodiments of the present disclosure, the step S502a determines, according to the target algorithm identifier, a sequence of instructions to be tested corresponding to the target algorithm identifier, and may be specifically implemented by the following step S502 b.

In step S502b, according to the target algorithm identifier, the instruction sequence to be tested corresponding to the target algorithm identifier is determined by the algorithm state machine.

It should be noted that, the beneficial effects of the above memory test method may refer to the related description of the above memory test system, and will not be repeated here.

The present disclosure also provides a memory test apparatus, as shown in fig. 6, the memory test apparatus 60 including: a receiving module 601, a determining module 602 and an executing module 603;

A receiving module 601, configured to receive an algorithm selection instruction sent by an external test device from the test access port 101, where the algorithm selection instruction includes a target algorithm identifier; a determining module 602, configured to determine, according to the target algorithm identifier, at least one instruction to be tested corresponding to the target algorithm identifier; the execution module 603 is configured to execute at least one instruction to be tested to test the memory 103.

In some embodiments of the present disclosure, the at least one instruction to be tested is a plurality of instructions to be tested; the determining module 602 is specifically configured to determine, according to the target algorithm identifier, a sequence of instructions to be tested corresponding to the target algorithm identifier.

In some embodiments of the present disclosure, the determining module 602 is specifically configured to determine, according to the target algorithm identifier, a sequence of instructions to be tested corresponding to the target algorithm identifier through an algorithm state machine.

It should be noted that, the memory test device may be a chip in the above embodiment of the method of the present application, or may be a functional module and/or a functional entity in the chip that can implement the functions of the embodiment of the device, which is not limited in the embodiment of the present application.

In the embodiment of the present application, each module may implement the memory testing method provided in the above method embodiment, and may achieve the same technical effects, so that repetition is avoided and redundant description is omitted here.

The present disclosure provides a chip including any of the memory test systems described above therein. The memory test system can realize the self-test of the chip.

The present disclosure also provides a computer-readable storage medium storing at least one instruction for execution by a processor to implement the memory testing method described in the various embodiments above.

The present disclosure also provides a computer program product comprising computer instructions stored in a computer-readable storage medium; the processor of the electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions so that the electronic device executes to implement the memory test method described in the above embodiments.

The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the embodiment of the memory testing method, and can achieve the same technical effects, so that repetition is avoided, and the description is omitted here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, apparatuses, servers and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Those of skill in the art will appreciate that in one or more of the examples described above, the functions described in this disclosure may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

It should be noted that: the embodiments described in the present disclosure may be arbitrarily combined without any collision.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention.

Claims (10)

1. A memory test system, the system comprising: a controller to test the access port and the memory;

The test access port is configured to receive an algorithm selection instruction sent by external test equipment and transmit the algorithm selection instruction to the controller, wherein the algorithm selection instruction comprises a target algorithm identifier;

The controller is configured to determine at least one instruction to be tested corresponding to the target algorithm identifier according to the target algorithm identifier, and the corresponding relation between a plurality of target algorithm identifiers and an instruction set to be tested is prestored in the controller; and executing the at least one instruction to be tested to test the memory.

2. The system of claim 1, wherein the at least one instruction to be tested is a plurality of instructions to be tested;

the controller is specifically configured to: and determining an instruction sequence to be detected corresponding to the target algorithm identifier according to the target algorithm identifier.

3. The system of claim 2, wherein the controller is specifically configured to: and determining an instruction sequence to be detected corresponding to the target algorithm identifier through an algorithm state machine according to the target algorithm identifier.

4. A system according to any one of claims 1 to 3, further comprising: the special instruction module is internally provided with a self-test access interface;

the special instruction module is configured to determine whether a channel between the test access port and the built-in self-test access interface is on;

the test access port is specifically configured to transmit the algorithm selection instruction to the built-in self-test access interface when a channel between the test access port and the built-in self-test access interface is connected;

the built-in self-test access interface is configured to store the algorithm selection instruction into a test data register included in the built-in self-test access interface;

the controller is specifically configured to determine, based on a target algorithm identifier of an algorithm test instruction in the test data register, at least one instruction to be tested corresponding to the target algorithm identifier.

5. A method for testing a memory, wherein a chip includes a controller, a test access port and a memory, the method being applied to the controller, the method comprising:

Receiving an algorithm selection instruction sent by external test equipment from the test access port, wherein the algorithm selection instruction comprises a target algorithm identifier;

Determining at least one instruction to be tested corresponding to the target algorithm identification according to the target algorithm identification, wherein the corresponding relation between a plurality of target algorithm identifications and an instruction set to be tested is prestored in the controller;

and executing the at least one instruction to be tested to test the memory.

6. The method of claim 5, wherein the at least one instruction to be tested is a plurality of instructions to be tested; the determining, according to the target algorithm identifier, at least one instruction to be tested corresponding to the target algorithm identifier includes:

And determining an instruction sequence to be detected corresponding to the target algorithm identifier according to the target algorithm identifier.

7. The method of claim 6, wherein determining, based on the target algorithm identifier, a sequence of instructions to be tested corresponding to the target algorithm identifier comprises:

And determining an instruction sequence to be detected corresponding to the target algorithm identifier through an algorithm state machine according to the target algorithm identifier.

8. A memory test apparatus, the apparatus comprising: the device comprises a receiving module, a determining module and an executing module;

The receiving module is configured to receive an algorithm selection instruction sent by external test equipment from the test access port, wherein the algorithm selection instruction comprises a target algorithm identifier;

the determining module is configured to determine at least one instruction to be tested corresponding to the target algorithm identifier according to the target algorithm identifier;

The execution module is configured to execute the at least one instruction to be tested to test the memory.

9. A chip comprising a system as claimed in any one of claims 1 to 4.

10. A computer readable storage medium, characterized in that the readable storage medium has stored thereon a program or instructions which, when executed by a processor, implement the steps of the memory testing method according to any of claims 5 to 7.