CN118332997A

CN118332997A - Through hole layout splitting method and device, electronic equipment and medium

Info

Publication number: CN118332997A
Application number: CN202310012790.4A
Authority: CN
Inventors: 朱中钦; 翁坤
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Filing date: 2023-01-05
Publication date: 2024-07-12

Abstract

The application provides a method, a device, electronic equipment and a medium for splitting a through hole layout, which comprise the following steps: reading a chip-level layout file and determining a through hole layer; splitting the through hole layer to obtain a plurality of through hole sub-layers, wherein different through hole sub-layers correspond to different masks; wherein, the splitting process comprises: traversing the through holes in the through hole pattern layer, detecting whether the distance between the through holes and the adjacent through holes meets the set distance condition, and if not, dividing the through holes and the adjacent through holes into different through hole sub-layers; and synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip-level layout file. The scheme can realize the splitting of the through hole layout.

Description

Through hole layout splitting method and device, electronic equipment and medium

Technical Field

The present application relates to integrated circuit technologies, and in particular, to a method and apparatus for splitting a through hole layout, an electronic device, and a medium.

Background

With the development of integrated circuit technology, it is widely used in various fields, such as the use of dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM).

In practice, the fabrication of integrated circuits generally involves a series of stages, such as design, fabrication, and packaging, wherein the design stages include circuit design and layout design, and the layout is used to prepare masks used in subsequent integrated circuit fabrication stages. Along with the continuous shrinkage of the semiconductor process node, the size of the through holes, including the spacing between the through holes, is also gradually reduced, and similar through hole shorting problems easily occur in the subsequent manufacturing stage. Therefore, in order to ensure reliable preparation of the subsequent integrated circuit, the layout of the through holes needs to be adjusted in the layout design stage.

Disclosure of Invention

The embodiment of the application provides a through hole layout splitting method, a through hole layout splitting device, electronic equipment and a medium.

According to some embodiments, a first aspect of the present application provides a method for splitting a via layout, including: reading a chip-level layout file and determining a through hole layer; splitting the through hole layer to obtain a plurality of through hole sub-layers, wherein different through hole sub-layers correspond to different masks; wherein, the splitting process comprises: traversing the through holes in the through hole pattern layer, detecting whether the distance between the through holes and the adjacent through holes meets the set distance condition, and if not, dividing the through holes and the adjacent through holes into different through hole sub-layers; and synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip-level layout file.

In some embodiments, the splitting process further comprises: if the distance between the through hole and the adjacent through hole meets the distance condition, dividing the adjacent through hole into the same through hole sub-layers as the through hole.

In some embodiments, traversing a via in a via layer, detecting whether a distance between the via and an adjacent via meets a set distance condition, and if not, dividing the via and the adjacent via into different via sub-layers, including: from the current traversing through hole, searching the through holes which are adjacent to the through hole and are not traversed along a first direction and a second direction which are perpendicular to each other respectively to serve as a first adjacent through hole and a second adjacent through hole; acquiring a first distance between adjacent boundaries of the through hole and a second adjacent through hole parallel to the first direction, and acquiring a second distance between adjacent boundaries of the through hole and the first adjacent through hole parallel to the second direction; if the first distance does not meet the distance condition, dividing the second adjacent through holes into through hole sub-layers different from the through holes; and if the second distance does not meet the distance condition, dividing the first adjacent through holes into through hole sub-layers different from the through holes.

In some embodiments, if the distance between the via and the adjacent via meets a distance condition, dividing the adjacent via into the same via sub-layers as the via comprises: if the first distance meets the distance condition, dividing the second adjacent through holes into through hole sub-layers which are the same as the through holes; and if the second distance meets the distance condition, dividing the first adjacent through holes into the through hole sub-layers which are the same as the through holes.

In some embodiments, the splitting process includes: obtaining the distance between each pair of adjacent and parallel two boundaries, and screening out a first boundary pair of which the distance does not meet the distance condition; traversing the through holes corresponding to the first boundary pairs, and dividing the two through holes into different through hole sub-layers if the first boundary pairs contact the two through holes at the same time; and dividing the through holes into any through hole sub-layers aiming at the non-traversed through holes corresponding to the second boundary pairs except the first boundary pairs.

In some embodiments, traversing the through holes in the through hole layer, before detecting whether the distance between the through hole and the adjacent through hole meets the set distance condition, further comprises: and taking the through hole layer as a selected target layer, calling a layering function, and creating an initial plurality of through hole sub-layers.

In some embodiments, synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip level layout file, including: and replacing the through hole layer in the chip-level layout file with a plurality of through hole sub-layers to obtain the target layout file.

In some embodiments, before performing the splitting process on the via image layer to obtain the plurality of via sub-layers, the method further includes: performing a physical verification on the via layer, the physical verification including at least one of: design rule verification, electrical rule verification and layout and circuit diagram consistency verification.

According to some embodiments, a second aspect of the present application provides a through-hole layout splitting apparatus, including: the reading module is used for reading the chip-level layout file and determining a through hole layer; the processing module is used for executing splitting processing on the through hole sub-layers to obtain a plurality of through hole sub-layers, and different through hole sub-layers correspond to different masks; wherein, the splitting process comprises: traversing the through holes in the through hole pattern layer, detecting whether the distance between the through holes and the adjacent through holes meets the set distance condition, and if not, dividing the through holes and the adjacent through holes into different through hole sub-layers; and the synthesis module is used for synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip-level layout file.

In some embodiments, when the processing module performs the splitting process, the processing module is further configured to divide the adjacent via into the same via sub-layers as the via if the distance between the via and the adjacent via meets the distance condition.

In some embodiments, the processing module comprises: the first recognition unit is used for searching the through holes which are adjacent to the through holes and are not traversed along a first direction and a second direction which are perpendicular to each other from the currently traversed through holes, and the first recognition unit is used as a first adjacent through hole and a second adjacent through hole; an acquisition unit configured to acquire a first distance between adjacent boundaries of the through hole and a second adjacent through hole parallel to the first direction, and acquire a second distance between adjacent boundaries of the through hole and the first adjacent through hole parallel to the second direction; the first processing unit is used for dividing the second adjacent through holes into through hole sub-layers different from the through holes if the first distance does not meet the distance condition; and if the second distance does not meet the distance condition, dividing the first adjacent through holes into through hole sub-layers different from the through holes.

In some embodiments, the first processing unit is further configured to: if the first distance meets the distance condition, dividing the second adjacent through holes into through hole sub-layers which are the same as the through holes; and if the second distance meets the distance condition, dividing the first adjacent through holes into the through hole sub-layers which are the same as the through holes.

In some embodiments, the processing module comprises: the second identification unit is used for acquiring the distance between each pair of adjacent and parallel boundaries and screening out a first boundary pair of which the distance does not meet the distance condition; the second processing unit is used for traversing the through holes corresponding to the first boundary pairs, and dividing the two through holes into different through hole sub-layers if the first boundary pairs contact the two through holes at the same time; the second processing unit is further configured to divide, for a non-traversed via corresponding to a second boundary pair other than the first boundary pair, the via into any via sub-layers.

In some embodiments, the processing module further comprises: and the creating unit is used for taking the through hole layer as the selected target layer, calling the layering function and creating a plurality of initial through hole sub-layers.

In some embodiments, the synthesis module is specifically configured to replace a through hole layer in the chip-level layout file with a plurality of through hole sub-layers, so as to obtain the target layout file.

In some embodiments, the apparatus further comprises: the verification module is used for performing physical verification on the through hole layer, and the physical verification comprises at least one of the following steps: design rule verification, electrical rule verification and layout and circuit diagram consistency verification.

According to some embodiments, a third aspect of the present application provides an electronic device, comprising: a processor, and a memory communicatively coupled to the processor; the memory stores computer-executable instructions; the processor executes computer-executable instructions stored in the memory to implement a method as described in any of the preceding.

According to some embodiments, a fourth aspect of the application provides a computer-readable storage medium having stored therein computer-executable instructions for implementing a method as described in any of the preceding claims when executed by a processor.

According to the through hole layout splitting method, the through hole layout splitting device, the electronic equipment and the medium, through hole layers in the chip-level layout file are read, through holes in the through hole layers are traversed, the through holes are divided into split through hole sub-layers according to whether the distance between adjacent through holes meets the distance condition, the through hole layers in the chip-level layout file are split into through hole sub-layers corresponding to different masks, and finally the through hole sub-layers are synthesized into the original chip-level layout file, so that the final target layout file is obtained. In the scheme, after the chip-level layout design is completed, through traversing the through holes in the through hole image layer, splitting of the through hole layout is realized, and based on the target layout file synthesized by the split through hole sub-layer and the layout file, the reliability of subsequent integrated circuit preparation can be improved, and the problems of adjacent through hole short circuit and the like in the preparation process caused by too close through hole spacing are avoided.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the embodiments of the application.

FIG. 1 is an exemplary diagram of a chip fabrication process;

FIG. 2 is an example of a via layout employing a single pass mask;

FIG. 3 is an example of a via layout employing a dual pattern technique;

FIG. 4 is a flowchart illustrating a method for splitting a via layout according to an embodiment;

FIG. 5 is a diagram of an example process for via splitting;

FIG. 6 is an exemplary diagram of a via layer;

FIG. 7 is a flowchart illustration of an exemplary splitting process;

FIG. 8 is an exemplary diagram of an exemplary via arrangement;

FIG. 9 is a flowchart illustration of an exemplary splitting process;

FIG. 10 is an exemplary diagram of an exemplary via arrangement;

fig. 11 to 13 are structural example diagrams of an example through-hole layout splitting device;

Fig. 14 is a diagram showing a structural example of an electronic device according to an embodiment.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The terms "comprising" and "having" in the present application are used to mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second," etc. are used merely as labels or distinction and do not limit the order or quantity of their objects. Furthermore, the various elements and regions in the figures are only schematically illustrated and are therefore not limited to the dimensions or distances illustrated in the figures.

The technical scheme is described in detail below with specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Chips, also known as integrated circuits, or microcircuits, microchips, are understood to be miniaturized circuits. In particular, the chip is often part of a computer or electronic device, and performs functions such as operations, processing tasks, and storage, such as a memory. Fig. 1 is an exemplary diagram of a chip manufacturing process, and as shown in fig. 1, the chip manufacturing process generally includes: chip design, wafer fabrication, package fabrication, cost testing, and the like.

In practical applications, the fabrication of integrated circuits involves transferring a pattern on a mask to a wafer by photolithography and etching processes. The geometry of the mask used is defined as the layout of the integrated circuit, and the integrated circuit manufacturer can manufacture the mask according to the layout, and then manufacture the integrated circuit based on the mask. Therefore, in the design stage of the integrated circuit, a layout file is generated according to the design circuit of the integrated circuit. Since the fabrication of integrated circuits is generally based on planar technology to realize three-dimensional structures, and requires layer-by-layer fabrication, layout files for integrated circuits are also typically composed of multiple layers, including, for example, via layers that reflect the via structure in the chip.

Taking the through hole structure as an example, when the previous process node is relatively large, the distance between the through holes is relatively large, the precision requirement on the preparation stage is not high, the requirement of exposure can be met by only one photomask generally, and the phenomenon of short circuit between the through holes is not easy to occur in the preparation process. However, with the development of integrated circuits, the process nodes shrink, the size of the via holes, including the pitch between the via holes, becomes smaller, and the process precision requirements are higher and higher, so that if the semiconductor device is still manufactured by a single photolithography process, short circuits between adjacent via holes are likely to occur. As shown in fig. 2, fig. 2 is an example of a through hole layout using a single mask, wherein the same shadow in the drawing indicates that the same mask is used for manufacturing subsequently, the left diagram is an example of the layout, and the right diagram is a wafer view when the through hole manufacturing is performed based on the layout of the left diagram. It can be seen that short circuits easily occur between the through holes when the single process is used for manufacturing. In this regard, a dual patterning technique may be employed, which refers to splitting an original layout into multiple layouts, i.e., transferring the patterns in the original layout design to multiple masks, so as to split an original one-time masking process into multiple masking processes in a subsequent preparation to meet the requirements of small process nodes.

In some examples, fig. 3 is an example of a via layout using a dual-pattern technique, and as shown in fig. 3, in the parameter cell design stage (PARAMETER CELL LEVEL, PCELL LEVEL), the via PC is split and divided into PC1 and PC2 (shown in the figure with different patterns shaded), where each corresponds to a mask. That is, by dividing the original primary mask into two masks, during the subsequent preparation, the through hole corresponding to one mask, such as PC1, can be prepared first, and then the other mask is used to prepare other through holes, such as PC2, so as to avoid the problem that the through hole short circuit is easy to occur during the primary preparation. In this example, in the design stage of the parameter unit (also referred to as a standard unit, typically the minimum unit in the circuit design), that is, the through hole splitting is performed during the bottom layer design, it is also necessary to scale the size of the standard unit and combine the standard units in a connection manner, and in this process, the number of through holes and the relative positional relationship in the original parameter unit are changed due to the size and the positional change, so that problems such as a through hole collision may occur.

Aspects of embodiments of the present application relate to the above considerations. The following describes an example of a solution in connection with some embodiments.

Example 1

Fig. 4 is a flowchart illustrating a method for splitting a via layout according to an embodiment, as shown in fig. 4, where the method for splitting a via layout includes:

Step 401: reading a chip-level layout file and determining a through hole layer;

Step 402: splitting the through hole layer to obtain a plurality of through hole sub-layers, wherein different through hole sub-layers correspond to different masks; wherein, the splitting process comprises: traversing the through holes in the through hole pattern layer, detecting whether the distance between the through holes and the adjacent through holes meets the set distance condition, and if not, dividing the through holes and the adjacent through holes into different through hole sub-layers;

step 403: and synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip-level layout file.

In practical application, the execution body of the embodiment may be a through hole layout splitting device, and the implementation form of the device is not limited, for example, the device may be implemented by a computer program, for example, application software, etc.; or may be embodied as a medium storing a related computer program, e.g., a usb disk, a cloud disk, etc.; or may be implemented by physical means, such as a chip, terminal, personal computer, etc., incorporating or installing the relevant computer program.

The chip-level layout file refers to a layout file in a full-chip design stage, the data format can be GDSII file format, the file in the stage usually completes the combination and connection of all standard units, the layout design of an integral chip is formed, and the physical verification of various full-chip levels can be supported. As an example, before step 402, it may further include: performing a physical verification on the chip-level layout, the physical verification including at least one of: design rule verification, electrical rule verification and layout and circuit diagram consistency verification. The design rule verification (Design Rule Check, abbreviated as DRC) is used to check whether the layout conforms to the design rules supported by the process, such as width, pitch, area, etc., after the layout is generated. Electrical rule verification (Electronic Rule Check, ERC for short) is used to check whether the chip-level layout meets electrical rules, such as device inspection, node open, node short, isolated via inspection, etc. The consistency verification (Layout versus Schematic, abbreviated as LVS) of the layout and the circuit diagram is used for checking whether the layout is consistent with the circuit.

For better understanding of the present solution, fig. 5 is an exemplary diagram of a process of splitting a via, and as shown in fig. 5, a via layer is determined by first reading a chip-level layout file (GDSII file in the figure). The through hole layer refers to a layout layer used for describing physical parameters of the through holes in the chip-level layout file, and it can be understood that the through holes in the chip-level layout file are through holes designed after standard unit combination connection. And then, carrying out splitting treatment on each through hole layer, wherein the principle of splitting treatment is to divide the pair of through holes into different through hole sub-layers when the distance between any pair of adjacent through holes in the through hole layers does not meet the set distance condition, wherein the different through hole sub-layers correspond to different masks. That is, the vias divided into different via sub-layers are prepared through two masks respectively in the subsequent process preparation, thereby avoiding short circuit caused by the closer distance between the two vias in the process preparation. After splitting treatment, a plurality of through hole sub-layers (two are exemplified in the figure) are obtained, and then the obtained plurality of through hole sub-layers are synthesized into an original chip-level layout file to obtain a final layout file, namely a target layout file.

In practical applications, when designing a layout, a layout engineer may distinguish between different layers by coloring through holes of different layers, so in order to facilitate layout design, in an example, before step 403, the method may further include: and coloring the through holes in the plurality of through hole sub-layers to ensure that the through holes in the same through hole sub-layer have the same color, and the through holes in different through hole sub-layers have different colors.

In the above-mentioned splitting process, another possible situation is that when the distance between the adjacent through holes satisfies the set distance condition, the short circuit caused by the distance is not easy to occur when the two through holes are prepared by the process, so that the same or a plurality of masks can be adopted for preparation. As an example, the splitting process further includes: and if the distance between the through hole and the adjacent through hole meets the distance condition, dividing the adjacent through hole into the same through hole sub-layers as the through hole. Specifically, in this example, for adjacent vias whose pitch satisfies the distance condition, a manner of dividing the two adjacent vias into the same via sub-layers is adopted to simplify the subsequent splitting process.

Specifically, after the through hole pattern layer is determined, splitting treatment can be performed on the through holes in the through hole pattern layer based on the distance condition so as to split the through holes into a plurality of through hole sub-layers. The distance condition may be set according to practical situations, such as process accuracy. In one example, the distance condition includes a pitch of not less than 0.5 microns. For example, in a certain via pattern layer, it is assumed that via 1 and via 2 are adjacent and the distance between them is 0.3 micrometers, i.e., the distance between via 1 and via 2 does not meet the set distance condition; assuming that the through-hole 2 and the through-hole 3 are adjacent and the space therebetween is 1 nm, the distance between the through-hole 2 and the through-hole 3 meets the set distance condition. Specifically, the pitch refers to the distance between adjacent sides of adjacent vias, and taking fig. 6 as an example, fig. 6 is an example of a via layer, where the via layer shown in fig. 6 includes a plurality of vias arranged in an array. For vias arranged in the same row, the spacing between adjacent vias refers to the distance between the right of the left via and the left of the right via; for vias arranged in the same column, the spacing between adjacent vias refers to the distance between the lower edge of an upper via and the upper edge of a lower via. It should be noted that fig. 6 is only an example, and other possible manners are not excluded, for example, for the through holes in other arrangements, the distance between the adjacent through holes may be defined according to the actual arrangement of the through holes.

In practical applications, the number of via sub-layers may be set as required, for example, two via sub-layers may be set. In some examples, traversing the through holes in the through hole layer in the splitting process, and before detecting whether the distance between the through hole and the adjacent through hole meets the set distance condition, further includes: and taking the through hole layer as a selected target layer, calling a layering function, and creating an initial plurality of through hole sub-layers. Specifically, for the through hole layer to be split, a plurality of initial through hole sub-layers can be created through a layering function/function (such as DFM DP function) of layout design software, and then through splitting processing, through holes in the original through hole layer are divided into the through hole sub-layers, so that each through hole sub-layer including the through holes is obtained. It should be noted that, in order to ensure the accuracy of chip preparation based on the layout, the size of the via sub-layer may be set to be identical to the original size of the via layer, and the position in the via sub-layer is identical to the position of the via in the original via layer after dividing into the via sub-layers.

In this embodiment, there may be various implementation manners of the splitting process. In an example, fig. 7 is a flowchart illustrating an example splitting process, as shown in fig. 7, in the splitting process of step 402, traversing a via in the via layer, detecting whether a distance between the via and an adjacent via meets a set distance condition, and if not, dividing the via and the adjacent via into different via sub-layers, which may specifically include:

step 501: from the current traversing through hole, searching the through holes which are adjacent to the through hole and are not traversed along a first direction and a second direction which are perpendicular to each other respectively to serve as a first adjacent through hole and a second adjacent through hole;

Step 502: acquiring a first distance between adjacent boundaries of the through hole and a second adjacent through hole parallel to the first direction, and acquiring a second distance between adjacent boundaries of the through hole and the first adjacent through hole parallel to the second direction;

step 503: if the first distance does not meet the distance condition, dividing the second adjacent through holes into through hole sub-layers different from the through holes; and if the second distance does not meet the distance condition, dividing the first adjacent through holes into through hole sub-layers different from the through holes.

Specifically, the present example completes the splitting process of all vias in the via layer by traversing adjacent vias in different directions. Fig. 8 is an exemplary diagram of via arrangement, and in combination with the illustration in fig. 8, a via may be selected from the vias in the via layer for the first time, for example, via 1 located at the bottom left corner (the first via located in the last row) is used as the current via to be traversed, then, in a first direction and a second direction perpendicular to each other, for example, assuming that the first direction is transverse, the second direction is longitudinal, the vias adjacent to the current via to be traversed are found, so that the first adjacent via and the second adjacent via may be obtained, for example, as illustrated in fig. 8, the adjacent via that finds via 1 in the transverse direction to the right is via 2, and the adjacent via that finds via 1 in the longitudinal direction to be via 3. The figures are only examples and are not limiting of other possibilities for the first direction and the second direction, such as longitudinal for the first direction, transverse for the second direction, etc.

It should be noted that, in the above example, the currently traversed via is located at the edge of the entire via array, for example, the first row/column and the last row/column are both edges of the via array, but this example also includes the case that the traversed via is located at a non-edge. Specifically, for the currently traversed through hole, the step of searching for the first adjacent through hole and the second adjacent through hole along the first direction and the second direction perpendicular to each other may be performed multiple times, and the first direction and the second direction in each execution may be redetermined to find out all the through holes adjacent to the currently traversed through hole. For example, assuming that the first traversing via is not located at the edge of the entire via array, e.g., assuming that the first direction is lateral and the second direction is longitudinal, via 4 shown in fig. 8, there are adjacent vias around each of the vias 4. Then, for the through-hole 4, the first adjacent through-hole which finds the through-hole 4 laterally to the left/right is the through-hole 5/through-hole 6, and the second adjacent through-hole which finds the through-hole 4 longitudinally upward/downward is the through-hole 7/through-hole 8.

Still referring to the via 1 in fig. 8 as an example of the via currently traversed, the distance d1 between the first adjacent via (via 2) of the via 1 and the via 1 is found in the lateral direction as the distance between the adjacent longitudinal edges of the via 1 and the via 2. The distance d2 between the second adjacent through hole (through hole 3) of the through hole 1 and the through hole 1, found in the longitudinal direction, is the distance between the adjacent lateral sides of the through hole 1 and the through hole 3. If the distance d1 does not meet the distance condition, the through hole 1 and the through hole 2 are divided into different through hole sub-layers, and if the distance d2 does not meet the distance condition, the through hole 1 and the through hole 3 are divided into different through hole sub-layers. In practical applications, for the first through hole to be traversed, the through hole sub-layer to which the through hole is to be divided may be set first, for example, assuming that the through hole 1 in fig. 8 is the first through hole to be traversed, the through hole 1 may be set to be divided into the first through hole sub-layer in advance, and in the above-mentioned case, when the distance d1 and the distance d2 do not meet the distance condition, the through hole 2 and the through hole 3 will be divided into the second through hole sub-layer different from the first through hole sub-layer. In addition, for a non-first-time-traversed through hole, for example, a later-traversed through hole, the sub-layer of the through hole where the through hole is located may already be determined in the splitting process of the previously-traversed through hole, so that the sub-layer division of the adjacent through holes of the through hole can be directly performed according to the previously-determined sub-layer of the through hole where the through hole is located. For example, when the through hole 2 is the currently traversed through hole, based on previous traversal of the through hole 1, since the distance d1 does not meet the distance condition, it is determined that the through hole is divided into the second through hole sub-layer, and for the traversal of the through hole 2, the through hole sub-layer to which the adjacent through hole should be divided may be determined by combining the distance between the through hole 2 and the adjacent through hole on the premise that this is the premise.

Alternatively, assuming that the distance between the currently traversed via and the neighboring via meets the distance condition, the via and its neighboring vias may be partitioned into the same via sub-layer. In an example, in combination with the traversal manner of this example, in the foregoing splitting process, if the distance between the through hole and the adjacent through hole meets the distance condition, the dividing the adjacent through hole into the same through hole sub-layer as the through hole may specifically include: if the first distance meets the distance condition, dividing the second adjacent through holes into the same through hole sub-layers as the through holes; and if the second distance meets the distance condition, dividing the first adjacent through holes into the same through hole sub-layers as the through holes. Still in combination with the foregoing example, if the distance d1 meets the distance condition, the via 2 may also be divided into the first via sub-layer, and if the distance d2 meets the distance condition, the via 3 may also be divided into the first via sub-layer.

In this example, through traversing each through hole, finding adjacent through holes along mutually perpendicular directions, and dividing the adjacent through holes into through hole sub-layers according to whether the actual distance meets the distance condition, the sub-layer division of all through holes in the through hole layer is completed, and the through hole layer is split into a plurality of through hole sub-layers.

In another example, fig. 9 is a flowchart illustrating an example splitting process, as shown in fig. 9, where the splitting process of step 402 may specifically include:

step 601: obtaining the distance between each pair of adjacent and parallel two boundaries, and screening out a first boundary pair of which the distance does not meet the distance condition;

Step 602: traversing the through holes corresponding to the first boundary pairs, and dividing the two through holes into different through hole sub-layers if the first boundary pairs contact the two through holes at the same time;

Step 603: and dividing the through hole into any through hole sub-layer aiming at the non-traversed through hole corresponding to the second boundary pair except the first boundary pair.

Specifically, the present example uses a pattern recognition and processing technique to first identify all adjacent and parallel boundary pairs in the via layer, and perform distance judgment and sub-layer division of the via based on the boundary pairs, thereby completing splitting processing of all vias in the via layer. FIG. 10 is an exemplary diagram of an exemplary via arrangement, as shown in connection with FIG. 10, where all parallel boundary pairs are first identified, where the identified boundary pairs may include various situations, such as parallel opposite sides of the same via, e.g., sides 1 and 2 of via a in FIG. 10; and adjacent sides of adjacent vias, e.g., side 3 of via b and side 4 of adjacent via c in fig. 10. In this solution, it is necessary to determine whether or not the boundary pair of the distance condition is met, which is the case because of the distance between the adjacent sides of the adjacent through holes, i.e., the distance between the adjacent through holes.

In this example, after all boundary pairs are identified, first boundary pairs whose distances do not meet the distance condition are screened out, and in combination with the foregoing examples, these first boundary pairs may include the above cases, so that further screening out boundary pairs capable of characterizing the distances between adjacent vias is required. As an example, it is detected whether each pair of edges contacts two vias simultaneously, and if two vias are contacted simultaneously, this pair of edges is indicated as the adjacent edge of the adjacent via. As shown in fig. 10, assuming that the distance between the side 1 and the side 2 does not meet the distance condition and the distance between the side 3 and the side 4 does not meet the distance condition, the side 1 and the side 2 are taken as a pair of boundary pairs, and the side 1 contacts the through hole a while the side 2 also contacts the through hole a, that is, the boundary pairs contact the same through hole at the same time, so that the judgment of the distance condition is not made; side 3 and side 4 are another pair of boundaries, side 3 contacting via b, while side 4 contacting via c, i.e., both vias. The via b and the via c are divided into different via sub-layers. After the splitting treatment, the remaining boundary pairs are all through holes meeting the distance condition, so that the through holes can be divided into any through hole sub-layers.

In this example, all boundary pairs which do not meet the distance condition are identified, the boundary pairs which contact two through holes simultaneously are divided into different sub-layers, then the through holes corresponding to the rest boundary pairs are divided into any sub-layer, so that sub-layer division of all through holes in the through hole layer is completed, and the through hole layer is split into a plurality of through hole sub-layers.

The above illustrates several ways of splitting, it being understood that further splitting may be performed depending on the actual layout. As an example, the present embodiment considers that, while minimizing the number of via sub-layers, it is ensured that adjacent vias in the split sub-layers also satisfy the distance condition. The method is characterized in that the number of the through hole sub-layers is larger as the different through hole sub-layers represent different masks, so that the more the number of the through hole sub-layers is, the more process steps are needed to be executed in the subsequent preparation, and therefore, in order to further simplify the process and reduce the process cost, the number of the split through hole sub-layers is reduced as much as possible while the process precision is ensured through the split of the through holes.

In combination with the above consideration, in one example, in combination with the foregoing manner of traversing adjacent through holes to split, in the splitting process, for a currently traversed through hole, determining that the two through holes are divided into the same or different sub-layers based on the distance between the through hole and its adjacent through hole, at this time, further, continuing to find an interval through hole closest to the currently traversed through hole (i.e., an adjacent through hole of the currently traversed through hole), detecting the distance between the through hole and the interval through hole, dividing the through hole and the adjacent through hole into the same or different sub-layers according to whether a distance condition is satisfied, where the different sub-layers refer to a new sub-layer that is not the sub-layer to which the currently traversed through hole belongs, but also not the sub-layer to which the adjacent through hole of the currently traversed through hole belongs; and the like, searching the next through hole along the direction facing the spacing through hole to divide the through holes until the distance between the currently found through hole and the currently traversed through hole meets the distance condition, so that the adjacent through holes in any split sub-layer are ensured to meet the distance condition, and the number of the through hole sub-layers is reduced as much as possible.

An example is given in connection with fig. 8, assuming that the currently traversed via is via 7 in the figure, the neighboring via that finds via 7 longitudinally down is via 4, and assuming that the distance between via 7 and via 4 is too close, via 7 is divided into via sub-layer a, and via 4 is divided into via sub-layer b. In combination with the above example, further, the next via hole closest to the via hole 7, i.e. via hole 8, is found in the direction towards the via hole 4, i.e. still in the longitudinal downward direction, and if the distance condition is met between the via hole 8 and the via hole 7, then it is not necessary to add a new sub-layer, and the via hole 8 is divided into sub-layers a, so that it is not only possible to implement that the via hole 7 and the via hole 4 are located in different sub-layers, but also that it is not necessary to add a new sub-layer. In contrast, if the distance between the via 7 and the via 8 does not satisfy the distance condition, the distance condition between the via 8 and the via 4 must not be satisfied, so the via 8 cannot be located in the same sub-layer as the via 7 or the same sub-layer as the via 4, so a new sub-layer, for example, a via sub-layer c is added, and the same via 8 is divided into the via sub-layer c. Therefore, adjacent through holes in any split sub-layer are guaranteed to meet the distance condition, and the number of the through hole sub-layers is reduced as much as possible.

In another example, the above-described effect can also be achieved by performing the splitting process a plurality of times. Specifically, the through hole splitting method may further include: and executing splitting processing on each current obtained through hole sub-layer until all adjacent through holes in the current through hole sub-layers meet the distance condition.

Specifically, after a plurality of through hole sub-layers are obtained through splitting treatment, the through hole sub-layers can be combined into an original chip-level layout file. The merging method is not limited. In one example, step 403 may specifically include: and replacing the through hole layer in the chip-level layout file with the plurality of through hole sub-layers to obtain the target layout file. In the example, merging of the through hole sub-layers into the layout file is completed in an alternative mode, and a final target layout file is obtained.

In this embodiment, after the fabrication of the chip-level layout file is completed, the through hole pattern layer in the chip-level layout file is split into a plurality of through hole sub-layers through splitting processing, so as to realize the splitting of the through holes. Compared with the bottom layer design stage, the through hole splitting is carried out in the standard unit design stage, so that the problem that collision can occur when standard unit combination connection is carried out later can be avoided, for example, the problem that direct splicing cannot be carried out due to sub-layer collision of the through hole can occur when units are spliced. In addition, the through hole splitting method of the embodiment can keep the original structure of the original layout file, and when the modification or iteration is needed, the through hole layout can be updated more conveniently and efficiently.

In the through hole layout splitting method provided by the embodiment, the through hole layers in the chip-level layout file are read, through holes in the through hole layers are traversed, the through holes are divided into split through hole sub-layers according to whether the distances between adjacent through holes meet the distance condition, the through hole layers in the chip-level layout file are split into the through hole sub-layers corresponding to different masks, and finally the through hole sub-layers are synthesized into the original chip-level layout file, so that the final target layout file is obtained. In the scheme, after the chip-level layout design is completed, through traversing the through holes in the through hole image layer, splitting of the through hole layout is realized, and based on the target layout file synthesized by the split through hole sub-layer and the layout file, the reliability of subsequent integrated circuit preparation can be improved, and the problems of adjacent through hole short circuit and the like in the preparation process caused by too close through hole spacing are avoided.

Example two

Fig. 11 is a diagram illustrating a structure of a through hole layout splitting apparatus according to an embodiment, as shown in fig. 11, the through hole layout splitting apparatus includes:

The reading module 11 is used for reading the chip-level layout file and determining a through hole layer;

A processing module 12, configured to perform splitting processing on the via sub-layers to obtain a plurality of via sub-layers, where different via sub-layers correspond to different masks; wherein the splitting process comprises: traversing the through holes in the through hole pattern layer, detecting whether the distance between the through holes and the adjacent through holes meets the set distance condition, and if not, dividing the through holes and the adjacent through holes into different through hole sub-layers;

And the synthesis module 13 is used for synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip-level layout file.

In practical application, the implementation form of the through hole layout splitting device is not limited, for example, the through hole layout splitting device can be implemented by a computer program, for example, application software and the like; or may be embodied as a medium storing a related computer program, e.g., a usb disk, a cloud disk, etc.; or may be implemented by physical means, such as a chip, terminal, personal computer, etc., incorporating or installing the relevant computer program.

The chip-level layout file refers to a layout file in a full-chip design stage, the data format can be GDSII file format, the file in the stage usually completes the combination and connection of all standard units, the layout design of an integral chip is formed, and the physical verification of various full-chip levels can be supported. As an example, the apparatus further comprises: the verification module is used for performing physical verification on the chip-level layout, and the physical verification comprises at least one of the following steps: design rule verification, electrical rule verification and layout and circuit diagram consistency verification.

The reading module 11 first determines the via layer by reading the chip-level layout file (GDSII file in the figure). The through hole layer refers to a layout layer used for describing physical parameters of the through holes in the chip-level layout file, and it can be understood that the through holes in the chip-level layout file are through holes designed after standard unit combination connection. Then, the processing module 12 performs a splitting process for each via pattern layer, where the principle of the splitting process is to divide a pair of vias into different via sub-layers when the distance between any pair of adjacent vias in the via pattern layer does not meet a set distance condition, where the different via sub-layers correspond to different masks. That is, the vias divided into different via sub-layers are prepared through two masks respectively in the subsequent process preparation, thereby avoiding short circuit caused by the closer distance between the two vias in the process preparation. After splitting treatment, a plurality of through hole sub-layers are obtained, and then the synthesis module 13 synthesizes the obtained plurality of through hole sub-layers into the original chip-level layout file to obtain a final layout file, namely the target layout file.

In practical applications, when designing a layout, a layout engineer may distinguish between different layers by coloring through holes of different layers, so in order to facilitate layout design, in one example, the apparatus further includes: and the coloring module is used for coloring the through holes in the plurality of through hole sub-layers so that the through holes in the same through hole sub-layer have the same color, and the through holes in different through hole sub-layers have different colors.

As an example, when the processing module 12 performs the splitting process, it is further configured to divide the adjacent through hole into the same sub-layers of the through holes as the through holes if the distance between the through hole and the adjacent through hole meets the distance condition. Specifically, in this example, for adjacent vias whose pitch satisfies the distance condition, a manner of dividing the two adjacent vias into the same via sub-layer is adopted.

The distance condition may be set according to practical situations, such as process accuracy. In one example, the distance condition includes a pitch of not less than 0.5 microns. In practical applications, the number of via sub-layers may be set as required, for example, two via sub-layers may be set. In some examples, the processing module 21 further includes: and the creating unit is used for calling a layering function by taking the through hole layer as a selected target layer and creating a plurality of initial through hole sub-layers. Specifically, the creating unit may create a plurality of initial via sub-layers through a layering function/function (for example, DFM DP function) of the layout design software for the via layers to be split, and then execute splitting processing through the processing module 21, so as to divide the vias in the original via layers into the via sub-layers, to obtain each via sub-layer including the vias. It should be noted that, in order to ensure the accuracy of chip preparation based on the layout, the size of the via sub-layer may be set to be identical to the original size of the via layer, and the position in the via sub-layer is identical to the position of the via in the original via layer after dividing into the via sub-layers.

In this embodiment, there may be various implementation manners of the splitting process. In one example, fig. 12 is a diagram illustrating a structural example of a through hole layout splitting apparatus of an example, as shown in fig. 12, the processing module 12 includes:

A first identifying unit 121, configured to find, from a currently traversed through hole, a through hole adjacent to the through hole and not traversed in a first direction and a second direction perpendicular to each other, as a first adjacent through hole and a second adjacent through hole, respectively;

An acquisition unit 122 for acquiring a first distance between adjacent boundaries of the through hole and a second adjacent through hole parallel to the first direction, and acquiring a second distance between adjacent boundaries of the through hole and the first adjacent through hole parallel to the second direction;

a first processing unit 123, configured to divide the second adjacent via into via sub-layers different from the via if the first distance does not meet the distance condition; and if the second distance does not meet the distance condition, dividing the first adjacent through holes into through hole sub-layers different from the through holes.

Alternatively, assuming that the distance between the currently traversed via and the neighboring via meets the distance condition, the via and its neighboring vias may be partitioned into the same via sub-layer. In one example, the first processing unit 121 is further configured to: if the first distance meets the distance condition, dividing the second adjacent through holes into the same through hole sub-layers as the through holes; and if the second distance meets the distance condition, dividing the first adjacent through holes into the same through hole sub-layers as the through holes.

In this example, each through hole is traversed by the first recognition unit, adjacent through holes are found along the directions perpendicular to each other, the first processing unit divides the adjacent through holes into sub-layers of the through holes according to whether the actual distances obtained by the obtaining unit meet the distance conditions, so as to divide the sub-layers of all the through holes in the through hole layer, and split the through hole layer into a plurality of sub-layers of the through holes.

In another example, fig. 13 is a diagram illustrating a structure of an example through hole layout splitting apparatus, as shown in fig. 13, the processing module 12 includes:

A second identifying unit 124, configured to obtain a distance between each pair of adjacent and parallel two boundaries, and screen out a first boundary pair whose distance does not meet a distance condition;

the second processing unit 125 is configured to traverse the through holes corresponding to the first boundary pair, and divide the two through holes into different through hole sub-layers if the first boundary pair contacts the two through holes at the same time;

The second processing unit 125 is further configured to divide, for a non-traversed via corresponding to a second boundary pair other than the first boundary pair, the via into any via sub-layers.

Specifically, after the second identifying unit 124 identifies all the boundary pairs in this example, the first boundary pair whose distance does not meet the distance condition is screened out, and the second processing unit 125 completes sub-layer division based on whether the boundary pair contacts two vias at the same time, thereby completing the splitting process of all the vias in the via layer. In this example, all boundary pairs which do not meet the distance condition are identified, the boundary pairs which contact two through holes simultaneously are divided into different sub-layers, then the through holes corresponding to the rest boundary pairs are divided into any sub-layer, so that sub-layer division of all through holes in the through hole layer is completed, and the through hole layer is split into a plurality of through hole sub-layers.

As an example, consider that while minimizing the number of via sub-layers, neighboring vias in the split sub-layers are guaranteed to also satisfy the distance condition. In combination with the above consideration, in one example, in combination with the foregoing manner of splitting by traversing the adjacent through hole, the processing module 12 is further configured to determine, for the currently traversed through hole, to divide the two through holes into the same or different sub-layers based on the distance between the through hole and its adjacent through hole in the splitting process, at this time further, continue to search for the closest spaced through hole to the currently traversed through hole (i.e., the adjacent through hole of the currently traversed through hole), detect the distance between the through hole and the spaced through hole, divide the through hole and the spaced through hole into the same or different sub-layers according to whether the distance condition is satisfied, where the different sub-layers refer to a new sub-layer that is not the sub-layer to which the currently traversed through hole belongs, but also not the sub-layer to which the adjacent through hole of the currently traversed through hole belongs; and the like, searching the next through hole along the direction facing the spacing through hole to divide the through holes until the distance between the currently found through hole and the currently traversed through hole meets the distance condition, so that the adjacent through holes in any split sub-layer are ensured to meet the distance condition, and the number of the through hole sub-layers is reduced as much as possible. In another example, the processing module 12 may also achieve the above effect by performing the splitting process multiple times. In particular, the processing module 12 may also be configured to: and executing splitting processing on each current obtained through hole sub-layer until all adjacent through holes in the current through hole sub-layers meet the distance condition.

Specifically, after a plurality of through hole sub-layers are obtained through splitting treatment, the through hole sub-layers can be combined into an original chip-level layout file. The merging method is not limited. In one example, the synthesis module 13 is specifically configured to replace a through hole layer in the chip-level layout file with a plurality of through hole sub-layers, so as to obtain the target layout file. In the example, merging of the through hole sub-layers into the layout file is completed in an alternative mode, and a final target layout file is obtained.

In the through hole layout splitting device provided by the embodiment, the reading module reads the through hole layers in the chip-level layout file, the processing module traverses the through holes in the through hole layers, the through holes are divided into split through hole sub-layers according to whether the distances between adjacent through holes meet the distance conditions, the through hole layers in the chip-level layout file are split into the through hole sub-layers corresponding to different masks, and the final synthesis module synthesizes the through hole sub-layers into the original chip-level layout file to obtain the final target layout file. In the scheme, after the chip-level layout design is completed, through traversing the through holes in the through hole image layer, splitting of the through hole layout is realized, and based on the target layout file synthesized by the split through hole sub-layer and the layout file, the reliability of subsequent integrated circuit preparation can be improved, and the problems of adjacent through hole short circuit and the like in the preparation process caused by too close through hole spacing are avoided.

Example III

Fig. 14 is a diagram showing a structural example of an electronic device according to an embodiment, and as shown in fig. 14, the electronic device includes:

a processor 291, the electronic device further comprising a memory 292; a communication interface (Communication Interface) 293 and bus 294 may also be included. The processor 291, the memory 292, and the communication interface 293 may communicate with each other via the bus 294. Communication interface 293 may be used for information transfer. The processor 291 may call logic instructions in the memory 292 to perform the methods of the above-described embodiments.

Further, the logic instructions in memory 292 described above may be implemented in the form of software functional units and stored in a computer-readable storage medium when sold or used as a stand-alone product.

The memory 292 is a computer-readable storage medium that may be used to store a software program, a computer-executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 291 executes functional applications and data processing by running software programs, instructions and modules stored in the memory 292, i.e., implements the methods of the method embodiments described above.

Memory 292 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created according to the use of the terminal device, etc. Further, memory 292 may include high-speed random access memory, and may also include non-volatile memory.

The disclosed embodiments provide a non-transitory computer readable storage medium having stored therein computer-executable instructions that, when executed by a processor, are configured to implement the method of the previous embodiments.

Example IV

The present embodiment provides a computer-readable storage medium having stored thereon a computer program that is executed by a processor to implement the method provided by any one of the embodiments of the present application.

Example five

The present embodiments provide a computer program product comprising a computer program which, when executed by a processor, implements the method provided by any one of the embodiments of the present application.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. The through hole layout splitting method is characterized by comprising the following steps of:

Reading a chip-level layout file and determining a through hole layer;

Splitting the through hole pattern layer to obtain a plurality of through hole sub-layers, wherein different through hole sub-layers correspond to different masks; wherein the splitting process comprises: traversing the through holes in the through hole pattern layer, detecting whether the distance between the through holes and the adjacent through holes meets the set distance condition, and if not, dividing the through holes and the adjacent through holes into different through hole sub-layers;

And synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip-level layout file.

2. The method of claim 1, wherein the splitting process further comprises:

and if the distance between the through hole and the adjacent through hole meets the distance condition, dividing the adjacent through hole into the same through hole sub-layers as the through hole.

3. The method of claim 2, wherein traversing the via in the via layer, detecting whether a distance between the via and an adjacent via meets a set distance condition, and if not, dividing the via and the adjacent via into different via sub-layers, comprises:

From the current traversing through hole, searching the through holes which are adjacent to the through hole and are not traversed along a first direction and a second direction which are perpendicular to each other respectively to serve as a first adjacent through hole and a second adjacent through hole;

Acquiring a first distance between adjacent boundaries of the through hole and the second adjacent through hole parallel to the first direction, and acquiring a second distance between adjacent boundaries of the through hole and the first adjacent through hole parallel to the second direction;

If the first distance does not meet the distance condition, dividing the second adjacent through holes into through hole sub-layers different from the through holes; and if the second distance does not meet the distance condition, dividing the first adjacent through holes into through hole sub-layers different from the through holes.

4. The method of claim 3, wherein dividing the adjacent via into the same via sub-layer as the via if the distance between the via and the adjacent via meets the distance condition comprises:

If the first distance meets the distance condition, dividing the second adjacent through holes into the same through hole sub-layers as the through holes;

and if the second distance meets the distance condition, dividing the first adjacent through holes into the same through hole sub-layers as the through holes.

5. The method of claim 1, wherein the splitting process comprises:

obtaining the distance between each pair of adjacent and parallel two boundaries, and screening out a first boundary pair of which the distance does not meet the distance condition;

traversing the through holes corresponding to the first boundary pairs, and dividing the two through holes into different through hole sub-layers if the first boundary pairs contact the two through holes at the same time;

and dividing the through hole into any through hole sub-layer aiming at the non-traversed through hole corresponding to the second boundary pair except the first boundary pair.

6. The method of claim 1, wherein traversing the via in the via pattern layer, before detecting whether a distance between the via and an adjacent via meets a set distance condition, further comprises:

and taking the through hole layer as a selected target layer, calling a layering function, and creating an initial plurality of through hole sub-layers.

7. The method according to claim 1, wherein synthesizing the target layout file after splitting the via layout according to the plurality of via sub-layers and the chip-level layout file comprises:

And replacing the through hole layer in the chip-level layout file with the plurality of through hole sub-layers to obtain the target layout file.

8. The method according to any one of claims 1-7, wherein before synthesizing the target layout file after splitting the via layout according to the plurality of via sub-layers and the chip-level layout file, the method further comprises:

and coloring the through holes in the plurality of through hole sub-layers to enable the colors of the through holes in the same through hole sub-layer to be the same, and the colors of the through holes in different through hole sub-layers to be different.

9. The utility model provides a through-hole territory split device which characterized in that includes:

The reading module is used for reading the chip-level layout file and determining a through hole layer;

The processing module is used for executing splitting processing on the through hole sub-layers to obtain a plurality of through hole sub-layers, and different through hole sub-layers correspond to different masks; wherein the splitting process comprises: traversing the through holes in the through hole pattern layer, detecting whether the distance between the through holes and the adjacent through holes meets the set distance condition, and if not, dividing the through holes and the adjacent through holes into different through hole sub-layers;

and the synthesis module is used for synthesizing the target layout file after splitting the through hole layout according to the plurality of through hole sub-layers and the chip-level layout file.

10. The apparatus of claim 9, wherein the device comprises a plurality of sensors,

And when the processing module executes the splitting processing, the processing module is further used for dividing the adjacent through holes into the same through hole sub-layers as the through holes if the distance between the through holes and the adjacent through holes meets the distance condition.

11. The apparatus of claim 10, wherein the processing module comprises:

The first recognition unit is used for searching the through holes which are adjacent to the through holes and are not traversed along a first direction and a second direction which are perpendicular to each other from the currently traversed through holes, and the first recognition unit is used as a first adjacent through hole and a second adjacent through hole;

an acquisition unit configured to acquire a first distance between adjacent boundaries of the through hole and the second adjacent through hole parallel to the first direction, and acquire a second distance between adjacent boundaries of the through hole and the first adjacent through hole parallel to the second direction;

The first processing unit is used for dividing the second adjacent through holes into through hole sub-layers different from the through holes if the first distance does not meet the distance condition; and if the second distance does not meet the distance condition, dividing the first adjacent through holes into through hole sub-layers different from the through holes.

12. The apparatus of claim 11, wherein the first processing unit is further configured to:

13. The apparatus of claim 9, wherein the processing module comprises:

The second identification unit is used for acquiring the distance between each pair of adjacent and parallel boundaries and screening out a first boundary pair of which the distance does not meet the distance condition;

the second processing unit is used for traversing the through holes corresponding to the first boundary pairs, and dividing the two through holes into different through hole sub-layers if the first boundary pairs contact the two through holes at the same time;

the second processing unit is further configured to divide, for a non-traversed through hole corresponding to a second boundary pair other than the first boundary pair, the through hole into any through hole sub-layers.

14. The apparatus of claim 9, wherein the processing module further comprises:

And the creating unit is used for calling a layering function by taking the through hole layer as a selected target layer and creating a plurality of initial through hole sub-layers.

15. The apparatus of claim 9, wherein the device comprises a plurality of sensors,

The synthesis module is specifically configured to replace the through hole layer in the chip-level layout file with the plurality of through hole sub-layers, so as to obtain the target layout file.

16. The apparatus according to any one of claims 9-15, wherein the apparatus further comprises:

And the coloring module is used for coloring the through holes in the through hole sub-layers so that the through holes in the same through hole sub-layer have the same color, and the through holes in different through hole sub-layers have different colors.

17. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;

the memory stores computer-executable instructions;

The processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1-8.

18. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1-8.