CN118331905B - Extensible on-chip interconnection bus structure - Google Patents
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Abstract
The invention relates to the technical field of on-chip interconnection bus design, in particular to an extensible on-chip interconnection bus structure, which comprises a plurality of host interface circuits and a plurality of slave arbitration selection logic circuits, wherein the host interface circuits are connected with the slave arbitration selection logic circuits to form a hardware interconnection matrix structure, the management of host ports is completed by the host interface circuits, and the management of slave ports is completed by the slave arbitration selection logic circuits; the expansion or the reduction of the host port and the slave port are completed by adding or removing a host interface circuit and a slave arbitration selection logic circuit; the slave arbitration selection logic circuit supports two arbitration logics, namely a fixed priority comparison algorithm and a cyclic priority algorithm, and meets arbitration requirements when a plurality of bus hosts access the same slave under different application scenes by selecting different arbitration modes.
Description
Technical Field
The invention belongs to the technical field of on-chip interconnection bus design, and particularly relates to an extensible on-chip interconnection bus structure.
Background
Along with the continuous improvement of the manufacturing level of integrated circuits, the design scale of system chips is continuously increased, the types and the number of functional modules integrated by the system chips are more and more, all the functional modules realize on-chip interaction by means of on-chip interconnection buses, and the on-chip interconnection buses are designed to determine the running efficiency of the system chips.
At present, most system chips have higher customization degree of on-chip interconnection bus design structures and weak flexible expansion capability for ensuring operation efficiency.
Disclosure of Invention
In order to solve the technical problems in the background art, the invention provides an extensible on-chip interconnection bus structure (hereinafter referred to as an extensible bus), which realizes flexible extension of an on-chip interconnection bus host and a slave on the premise of ensuring good bus operation efficiency and remarkably improves the expandability and the universality of the on-chip interconnection bus structure.
Specifically, the invention provides an expandable on-chip interconnection bus structure, which comprises a plurality of host interface circuits and a plurality of slave arbitration selection logic circuits, wherein the host interface circuits are connected with the slave arbitration selection logic circuits to form a hardware interconnection matrix structure, the hardware interconnection matrix structure supports that a plurality of buses are connected with an expansion access interface through a bus host expansion interface, and a host can access any slave on the buses to jointly form an on-chip interconnection bus; the management of the host port is completed by the host interface circuit, and the management of the slave port is completed by the slave arbitration selection logic circuit;
On one hand, the expansion or the reduction of the host port and the slave port is completed by connecting a plurality of buses with an expansion access interface through a bus host expansion interface to form an on-chip interconnection bus; on the other hand, the method is completed by adding the same bus or removing a host interface circuit and a slave arbitration selection logic circuit;
The slave arbitration selection logic circuit supports hierarchical arbitration logic, each slave interface divides a host connected to the bus into a plurality of groups through the hierarchical arbitration logic circuit, the hosts in the same group adopt one priority mode, and the hosts in different groups adopt another priority mode; the priority mode supports a fixed priority comparison algorithm or a round robin priority algorithm. The hierarchical arbitration logic circuit supports the fine control of the host accessing the slave, can better meet the arbitration requirements of a plurality of bus hosts accessing the same slave under different application scenes, and improves the access efficiency.
Preferably, the host interface circuit is used for sending host access control signals and write data to the target host, and receiving response signals and read data from the slave, and comprises a read data selection circuit and a host interface control state machine;
the input signals of the host interface circuit comprise clock and reset signals, host data signals, host control signals, slave read data signals and slave response signals, and the output signals comprise host data signals, host control signals, target slave read data signals, slave response signals and host state indication signals;
The host interface circuit outputs the target slave read data signal to a host according to a slave selection signal, and outputs the host data signal and the host control signal to the slave arbitration selection logic circuit; the host interface control state machine takes the slave response signal and the host control signal as inputs, controls the state of the host interface circuit, and outputs the slave response signal, the host state indication signal and the current slave selection signal.
Preferably, the input signals of the read data selecting circuit are all slave read data signals and slave selecting signals on the bus, and the output signals are target slave read data signals;
The read data selecting circuit selects target slave read data signals from all the input slave read data signals according to the slave select signals; outputting the data to a corresponding host; when the current host has no access request, the output of the read data selecting circuit is kept in a constant state.
Preferably, the input signals of the host interface control state machine are clock and reset signals of a bus, slave response signals and host control signals, and the output signals are host state indication signals, slave response signals and slave selection signals;
the host data signal and the host control signal are output from the host, and are output to each slave arbitration selection logic circuit after passing through the host interface circuit; when the current host has no access request, the host control signal and the host data signal output are kept in a constant state.
Preferably, the slave arbitration selection logic circuit is configured to receive data and control signals from each host on the bus, select, based on a priority mode and configuration, access priorities of a plurality of hosts that access simultaneously, and output currently valid host access control and write data to the slave according to each host priority that accesses simultaneously, and simultaneously output response signals and read data of the slave to corresponding host ports, and includes a host selection circuit, a hierarchical arbitration logic circuit, a slave arbitration selection logic state machine and a slave register;
the input signals of the slave arbitration selection logic circuit comprise all host data and control signals, slave configuration signals, slave read data signals and response signals, slave configuration clocks and reset signals and slave arbitration selection logic circuit working clocks and reset signals on a bus, and the output signals comprise current host data and control signals, slave access state signals and slave read data signals and response signals;
The slave arbitration selection logic circuit selects an effective host port from all host ports on the bus based on the priority mode and the configuration signal according to the slave state and the host control signal, and outputs the host data and the control signal to the slave.
Preferably, the input signals of the host selection circuit comprise all host data and control signals and host selection signals on the bus, and the output signals are current host data and control signals;
the host selection signal is generated by a slave arbitration selection logic state machine, the host selection circuit determines a currently effective host port according to the host selection signal and gives the control authority of the currently effective host port to a current host, and current host data and control signals are output; when the slave has no host port access, the current host data and control signal output keep in a constant state.
Preferably, the input signals of the slave register comprise a slave configuration signal, a slave configuration clock and a reset signal; the slave configuration signal comprises a slave arbitration mode and an arbitration priority configuration;
the slave register stores the configuration of the slave arbitration mode and the arbitration priority, and outputs the priority mode and the configuration signal to the hierarchical arbitration logic circuit.
Preferably, the input signal of the slave arbitration selection logic state machine is an arbitration result of a slave arbitration selection logic circuit working clock, a reset signal and a hierarchical arbitration logic circuit, and is output as a slave access state signal;
The slave arbitration selection logic state machine generates the latest host selection signal and the slave access state signal according to the arbitration result and the current slave controlled state, and the latest host selection signal is output to the hierarchical arbitration logic circuit and the host selection circuit.
Preferably, the hierarchical arbitration logic circuit is used for realizing the hierarchical arbitration logic of the expandable bus, wherein the input signals are host selection signals, priority modes and configuration signals, and the output signals are the access priority arbitration results of all hosts;
Each slave interface of the hierarchical arbitration logic circuit can conduct hierarchical configuration on priorities of all hosts on the expandable bus through a hierarchical arbitration logic structure, for any slave interface, the hosts under the same level complete arbitration based on one priority arbitration logic, the priority arbitration logic is different among different levels, the priority arbitration logic algorithm comprises a fixed priority comparison algorithm and a cyclic priority algorithm, and the different levels select different arbitration logic algorithms as arbitration logic of the level;
The workflow of the hierarchical arbitration logic circuit is that all host selection signals, priority modes and configurations and priority grouping configuration signals are used as the input of the priority grouping configuration circuit, and the corresponding host IDs are also used as the input of the priority grouping configuration circuit when the host selection signals are valid; the priority grouping configuration circuit groups all host selection signals according to the host IDs and the priority grouping configuration signals, inputs the priority modes and the configuration signals in the groups and the valid host selection signals in the same group into the hierarchical arbitration logic circuit, wherein each group comprises i hosts, j groups are all, and the host selection signals in the same group pass through the hierarchical arbitration logic circuit to output the priority in each host in the group; the priority group allocation circuit inputs all host selection signals in the group into the OR circuit, when any host selection signal in the group is valid, the host selection signals in all groups are input into the hierarchical arbitration logic circuit, and the circuit outputs the priorities of all groups; the group priority signal and the group priority results of all the hosts in the group are input into a priority combination circuit, the priority combination circuit executes the multiplication operation of the group priority of the host and the corresponding group priority, the access priority of each host is output, and the access priority of the host is used as an arbitration basis when a plurality of hosts access the slave at the same time.
Preferably, when the hierarchical arbitration logic circuit adopts a fixed priority comparison algorithm, the hierarchical arbitration logic circuit directly outputs the input priority configuration of each host as the priority arbitration result of each host; if two hosts request to access the slave port, the host with higher priority will obtain the control authority to the slave port; when a host port sends a request to a slave port, the slave port checks whether the priority of the new requested host port is higher than the priority of the host port currently controlling the slave port; the slave port performs arbitration check at each clock edge, and if the priority of the newly requested host is higher than the priority of the host currently controlling the slave port, the newly requested host obtains the control authority of the slave port at the next clock edge; if the host currently controlling the slave port is executing burst transmission or locked transmission with a fixed length, whether the priority of the newly requested host is higher than that of the host currently executing access or not, the control authority of the slave port can be obtained only after the burst transmission or locked transmission is ended;
when the hierarchical arbitration logic circuit adopts a cyclic priority algorithm, each host port allocates a relative priority according to a physical host port number, compares the relative priority with the last host port performing transmission on a bus, and requests a host to obtain the control authority of the next transmission boundary slave by the highest priority; after the host obtains the control authority of the target slave, the host can execute data transmission to the port until another host sends a request to the same slave port; the next host is allowed to access the slave port at the next transfer boundary, and if the current master does not have a pending access request, then it is accessed in the next clock cycle.
The invention has the beneficial effects that:
the extensible on-chip interconnection bus structure provided by the invention can flexibly select the number of the integrated hosts and slaves according to actual needs. The main advantages of the scalable bus are as follows:
(1) The extensible on-chip interconnection bus supports that a plurality of buses are connected with an expansion access interface through a bus host expansion interface, and a host can access any slave on the buses to form an on-chip interconnection bus together, so that the expansion of the on-chip interconnection bus is realized, and the flexibility of bus expansion is improved;
(2) The expansion bus in the invention adopts a hardware interconnection matrix mode to connect all the host and slave ports on the bus, supports flexible expansion, supports all the bus hosts to simultaneously access different bus slaves, and effectively improves the bus access efficiency. Meanwhile, in order to relieve the problem of power consumption rise caused by a hardware interconnection matrix structure in the extensible bus, constant output is kept for all the inactive host ports in the bus so as to reduce circuit power consumption;
(3) The scalable bus of the present invention designs a hierarchical arbitration logic circuit for each slave arbitration selection. The slave can classify the host connected to the slave according to the type of the host, the host of the same type is divided into a group and adopts a priority arbitration mode, the host group containing the host of different types adopts a priority arbitration mode, and the hierarchical arbitration logic circuit design realizes the fine control of the host to access the slave for arbitration, can better meet the arbitration requirements when a plurality of bus hosts access the same slave in different application scenes, and improves the access efficiency. The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
Fig. 1 is a diagram of an extensible on-chip interconnect bus architecture provided by the present invention.
Fig. 2 is an example of a scalable on-chip bus interconnect bus cascade structure provided by the present invention.
Fig. 3 is a circuit structure of a host port provided in the present invention.
FIG. 4 is a diagram of a slave arbitration select logic circuit architecture provided by the present invention.
FIG. 5 is a block diagram of a hierarchical arbitration logic circuit according to the present invention.
FIG. 6 is a block diagram of a hierarchical arbitration logic circuit with 8 hosts.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
Aiming at the problems that in order to ensure the running efficiency of most system chips, the on-chip interconnection bus design structure has higher customization degree and weak flexible expansion capability, the invention provides an expandable on-chip interconnection bus structure, and the expandable on-chip interconnection bus is connected with a host and a slave in a mode of a hardware interconnection matrix, so that a plurality of buses are supported to be connected with an expansion access interface through a bus host expansion interface, the host can access any slave on the buses to form an on-chip interconnection bus together, and the expansion of the on-chip interconnection bus is realized. The expandable bus structure is shown in fig. 1, the expandable bus after cascade expansion is shown in fig. 2, M0, M1, mn in fig. 1 and fig. 2 represent n+1 host interfaces, and S0, S1, sm represent m+1 slave interfaces. The extensible on-chip interconnection bus connects a bus host and a slave by using a hardware interconnection matrix, management of a host port is completed by a host interface circuit, and management of a slave port is completed by a slave arbitration selection logic circuit. The plurality of host interface circuit units are connected with the plurality of slave arbitration selection logic circuit units to form a hardware interconnection matrix structure.
The expandable bus is provided with a hierarchical arbitration logic circuit for each slave arbitration selection, and each slave interface can be used for layering the priority configuration of the hosts connected to the bus through the hierarchical arbitration logic circuit, namely, the hosts are divided into a plurality of groups, the hosts in the same group adopt a priority mode, and the different groups adopt a priority mode. The priority mode supports a fixed priority comparison algorithm or a round robin priority algorithm. For a host to access a slave, multiplying the intra-group priority of the host by the belonging group priority results in a final access priority when the host accesses a slave. For the slave, the hosts connected to the slave can be classified according to the types of the hosts, the hosts of the same type are divided into a group, and a priority arbitration mode is adopted, for example, the hosts of the same type have the same access characteristic, and the hosts can be configured into a cyclic arbitration priority, so that the hosts can acquire the access rights uniformly; different types of host groups employ a priority arbitration mode. For example, a fixed priority mode is adopted among the host groups, the host groups have different host characteristics, and the fixed priority can better confirm that some types of hosts are responded preferentially. The hierarchical arbitration logic circuit supports the fine control of the host accessing the slave, can better meet the arbitration requirements of a plurality of bus hosts accessing the same slave under different application scenes, and improves the access efficiency.
All accesses on the scalable bus are initiated by the host. When a host accesses a slave, if the accessed target slave is available (idle), the host can access the target slave immediately (in a zero-waiting state), the slave can be accessed in a single clock period through an expandable bus, and the expandable bus returns all response information of the slave to the host requesting access; if the target slave port of the access is busy, the master access is inserted into a wait state until the target slave port is able to respond to the master request. The delay of service requests depends on the priority of each master and the access time of the responding slave. After the host completes access to the target slave, the host still maintains the right to control the slave port until after an idle period or the host initiates access to another slave. When another host port with higher priority sends a request to the slave port, if the current host is carrying out burst transmission with fixed length, the current host keeps controlling the slave port until the burst transmission is completed; otherwise, the current host port loses control authority over the slave port.
Specifically, the scalable on-chip interconnect bus structure includes:
1) A host interface circuit, the circuit structure of which is shown in fig. 3;
The host interface circuit is mainly used for sending host access control signals and write data to the target host, and simultaneously receiving response signals and read data from the slave, and mainly comprises a read data selection circuit and a host interface control state machine.
The input signals of the host interface circuit comprise clock and reset signals, host data signals, host control signals, slave read data signals and slave response signals, and the output signals mainly comprise host data signals, host control signals, target slave read data signals, slave response signals and host state indication signals.
The host interface circuit outputs a target slave read data signal to the host according to the slave select signal, and outputs host data and control signals to the slave arbitration select logic circuit of the expandable bus. The host interface control state machine takes the slave response signal and the host control signal as inputs, controls the state of a host interface circuit, and outputs the slave response signal, the host state indication signal and the current slave selection signal.
(101) Read data selection circuit
The input signals of the read data selection circuit are all slave read data signals and slave selection signals on the bus, and the output signals are target slave read data signals; the read data selecting circuit selects a target slave read data signal from all the input slave read data signals according to the slave select signal, and outputs the target slave read data signal to the corresponding master. When the current host has no access request, the output of the read data selecting circuit is kept in a constant state, so that the circuit power consumption is reduced.
(102) Host interface control state machine
The host interface control state machine is a host interface circuit controller, the input signals of which are clock and reset signals of the expandable bus, slave response signals and host control signals, and the output signals are host state indication, slave response signals and slave selection signals. Meanwhile, the host data signal and the host control signal are output from the host, and are output to each slave arbitration selection logic circuit after passing through the host interface circuit. When the current host has no access request, the host control signal and the host data signal output keep in a constant state so as to reduce the power consumption of the circuit.
2) The slave arbitration selection logic circuit has a circuit structure shown in fig. 4;
The slave arbitration selection logic circuit is mainly used for receiving data and control signals from all the hosts on the bus, based on the priority mode and the configuration, the access priorities of a plurality of hosts which are accessed simultaneously are given, and the current effective host access control and write data are selected according to the priorities of all the hosts which are accessed simultaneously and output to the slave. And simultaneously, the response signal and the read data of the slave are output to the corresponding host port, and the slave mainly comprises a host selection circuit, a hierarchical arbitration logic circuit, a slave arbitration selection logic state machine and a slave register.
The input signals of the slave arbitration selection logic circuit mainly comprise data and control signals of all host ports on the extensible bus, slave configuration signals, slave read data and response signals, slave configuration clocks and reset signals, and slave arbitration selection logic circuit working clocks and reset signals, and the output signals mainly comprise current host data and control signals, slave access state signals and slave read data and response signals.
The slave arbitration selection logic circuit selects an effective host port from all host ports on the expandable bus based on the priority mode and the configuration signal according to the slave state and the host access control signal, and outputs the host data and the control signal to the slave.
(201) Host selection circuit
The input signal of the host selection circuit is host data and control signal and host selection signal. The host data and control signals include data and control signals for all host ports on the scalable bus. The master select signal is generated by a slave arbitration select logic state machine. The host selection circuit determines the currently effective host port according to the host selection signal, gives the control authority to the current host, and outputs the current host data and the control signal. When the slave machine has no host machine port access, the current host machine data and control signal output are kept in a constant state, so that the circuit power consumption is reduced.
(202) Slave register
The input signals of the slave register are a slave configuration signal, a slave configuration clock and a reset signal. The slave configuration signals include an arbitration mode, an arbitration priority configuration. The slave register stores the configuration of the slave arbitration mode and the arbitration priority and outputs the configuration to the hierarchical arbitration logic circuit.
(203) Slave arbitration selection logic state machine
The input signals of the slave arbitration selection logic state machine are the arbitration results of the slave arbitration selection logic circuit working clock, the reset signals and the hierarchical arbitration logic circuit, and are output as slave access state signals. The slave arbitration selection logic state machine generates the latest host selection signal and the slave access state signal according to the arbitration result and the current slave controlled state, and the latest host selection signal is output to the hierarchical arbitration logic circuit and the host selection circuit.
(204) Hierarchical arbitration logic circuit
The hierarchical arbitration logic circuit is capable of implementing a hierarchical arbitration structure of the scalable bus. The hierarchical arbitration logic circuit design is shown in FIG. 5, wherein M0_ID [7:0], M1_ID [7:0], mn_ID [7:0] represent the port numbers of host 0, host 1, host n, respectively, and INT (0) represents the input 0 value. Each slave interface can perform hierarchical setting on the priorities of all the hosts on the extensible bus through a hierarchical arbitration logic structure, and the hierarchical methods of different slave interfaces can be different. For any slave interface, the host under the same level performs arbitration based on one priority arbitration logic, and the priority arbitration logic can be different among different levels. The priority arbitration logic algorithm comprises a fixed priority comparison algorithm and a cyclic priority algorithm, different levels can flexibly select different arbitration logic algorithms as arbitration logic of the level, and the arbitration flexibility of different types of host access slaves is improved.
The operation logic of the hierarchical arbitration logic circuit is that all host selection signals, priority modes and configurations, and priority grouping configuration signals are used as inputs of the priority grouping configuration circuit, and the corresponding host IDs are also used as inputs of the priority grouping configuration circuit when the host selection signals are valid. The priority grouping configuration circuit groups all host selection signals according to the host IDs and the priority grouping configuration signals, and inputs the priority modes and the configuration signals in the groups and the valid host selection signals in the same group into the hierarchical arbitration logic circuit, wherein each group comprises i hosts, and j groups are all arranged. The host selection signals in the same group pass through a hierarchical arbitration logic circuit to output the priority in the group of each host in the group; the priority group allocation circuit inputs all host selection signals in the group into the OR circuit, when any host selection signal in the group is valid, the host selection signals in all groups are input into the hierarchical arbitration logic circuit, and the circuit outputs the priorities of all groups; the group priority signal and the group priority results of all the hosts in the group are input into a priority combination circuit, and the priority combination circuit executes the multiplication operation of the group priority of the host and the corresponding group priority and outputs the access priority of each host. The access priority of the host is used as an arbitration basis when a plurality of hosts access the slave at the same time.
(205) Hierarchical arbitration logic circuit
The hierarchical arbitration logic circuit realizes two arbitration methods of the expandable bus, including a fixed priority comparison algorithm and a cyclic priority algorithm. The input signals of the hierarchical arbitration logic circuit are host selection signals, priority modes and configuration signals. The output signals are the results of the arbitration of the access priorities of the various hosts. The hierarchical arbitration logic circuit selectively executes fixed priority comparison algorithm arbitration logic or cyclic priority algorithm arbitration logic through the priority mode signal.
When the hierarchical arbitration logic circuit adopts a fixed priority comparison algorithm, the hierarchical arbitration logic circuit directly outputs the input priority configuration of each host as the priority arbitration result of each host. Each host is assigned a unique fixed priority while operating in the fixed priority mode. If two hosts request access to a slave port, the host with the higher priority will gain control of the slave port. When a host port makes a request to a slave port, the slave port will check whether the priority of the newly requested host port is higher than the priority of the host port currently controlling the slave port. The slave port performs an arbitration check at each clock edge. If the priority of the newly requesting host is higher than the host priority of the currently controlling slave port, the newly requesting host will gain control authority over the slave port on the next clock edge. An exception to this arbitration method is that the master currently controlling the slave port is performing a burst transfer or a locked transfer of fixed length. In this case, even if the priority of the newly requesting host is higher than that of the host currently performing access, it is necessary to wait for the burst transfer or the lock transfer to end before obtaining control authority for the slave port.
When the hierarchical arbitration logic circuit adopts a round robin priority algorithm, each host port is assigned a relative priority according to a physical host port number. This relative priority is compared to the last host port performing the transfer on the bus. The highest priority requests the master to obtain the control authority of the next transmission boundary slave. After the host obtains the control authority of the target slave, the host can perform data transmission to the port until another host sends out a request to the same slave port. The next host is allowed to access the slave port at the next transfer boundary and, if the current master does not have a pending access request, it is accessed in the next clock cycle.
FIG. 6 shows an example of a hierarchical arbitration logic circuit with 8 hosts, wherein current_m0 represents the 8 host selection signal, current_m0 represents the host 0 selection signal, and current_m7 represents the host 7 selection signal. When the arbitration mode selects the fixed priority comparison algorithm mode, the hierarchical arbitration logic circuit directly outputs the configuration of the arbitration priority in the fixed priority mode as the unique fixed arbitration priority of each host; when the arbitration mode selects the round robin priority algorithm mode, the arbitration priority of each host port is a relative priority, and the priority of the host under a certain slave port will change with the change of the host port currently accessing the slave. Assuming that the scalable bus master ports 0, 1, 2, 3,4, 5 and 7 are used, if the master port controlling a certain slave port at this time is the master port 3 and the master ports 0, 2,4, 5 and 7 issue requests at the same time, they will sequentially obtain access rights to the target slaves in the order of 4, 5, 7, 0 and 2.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present technology without departing from the spirit or scope of the technology. Thus, if such modifications and variations of the present technical solution fall within the scope of the present technical solution claims and the technical equivalents thereof, the present technical solution is also intended to include such modifications and variations.
Claims (10)
1. The expandable on-chip interconnection bus structure is characterized by comprising a plurality of host interface circuits and a plurality of slave arbitration selection logic circuits, wherein the host interface circuits are connected with the slave arbitration selection logic circuits to form a hardware interconnection matrix structure, the hardware interconnection matrix structure supports that a plurality of buses are connected with an expansion access interface through a bus host expansion interface, and a host can access any slave on the buses to form an on-chip interconnection bus together; the management of the host port is completed by the host interface circuit, and the management of the slave port is completed by the slave arbitration selection logic circuit;
On one hand, the expansion or the reduction of the host port and the slave port is completed by connecting a plurality of buses with an expansion access interface through a bus host expansion interface to form an on-chip interconnection bus; on the other hand, the method is completed by adding the same bus or removing a host interface circuit and a slave arbitration selection logic circuit;
The slave arbitration selection logic circuit supports hierarchical arbitration logic, each slave interface divides a host connected to the bus into a plurality of groups through the hierarchical arbitration logic circuit, the hosts in the same group adopt one priority mode, and the hosts in different groups adopt another priority mode; the priority mode supports a fixed priority comparison algorithm or a round robin priority algorithm.
2. The scalable on-chip interconnect bus structure of claim 1, wherein said host interface circuit is configured to send host access control signals, write data, to a target host while receiving response signals, read data from a slave, including read data selection circuitry and a host interface control state machine;
the input signals of the host interface circuit comprise clock and reset signals, host data signals, host control signals, slave read data signals and slave response signals, and the output signals comprise host data signals, host control signals, target slave read data signals, slave response signals and host state indication signals;
The host interface circuit outputs the target slave read data signal to a host according to a slave selection signal, and outputs the host data signal and the host control signal to the slave arbitration selection logic circuit; the host interface control state machine takes the slave response signal and the host control signal as inputs, controls the state of the host interface circuit, and outputs the slave response signal, the host state indication signal and the current slave selection signal.
3. The expandable on-chip interconnect bus structure of claim 2 wherein the input signals of said read data select circuit are all slave read data signals and slave select signals on the bus and the output signals are target slave read data signals;
The read data selecting circuit selects target slave read data signals from all the input slave read data signals according to the slave select signals; outputting the data to a corresponding host; when the current host has no access request, the output of the read data selecting circuit is kept in a constant state.
4. The expandable on-chip interconnection bus structure of claim 2, wherein the input signals of the host interface control state machine are clock and reset signals, slave response signals and host control signals of the bus, and the output signals are a host state indication signal, a slave response signal and a slave selection signal;
the host data signal and the host control signal are output from the host, and are output to each slave arbitration selection logic circuit after passing through the host interface circuit; when the current host has no access request, the host control signal and the host data signal output are kept in a constant state.
5. The scalable on-chip interconnect bus structure of claim 1, wherein the slave arbitration select logic is configured to receive data and control signals from each of the hosts on the bus, select currently valid host access control and write data to output to the slave according to each of the host priorities accessed simultaneously based on the priority mode and the access priorities of the plurality of hosts configured to be accessed simultaneously, and output response signals and read data of the slave to corresponding host ports, comprising a host select circuit, a hierarchical arbitration logic, a slave arbitration select logic state machine, and a slave register;
the input signals of the slave arbitration selection logic circuit comprise all host data and control signals, slave configuration signals, slave read data signals and response signals, slave configuration clocks and reset signals and slave arbitration selection logic circuit working clocks and reset signals on a bus, and the output signals comprise current host data and control signals, slave access state signals and slave read data signals and response signals;
The slave arbitration selection logic circuit selects an effective host port from all host ports on the bus based on the priority mode and the configuration signal according to the slave state and the host control signal, and outputs the host data and the control signal to the slave.
6. The expandable on-chip interconnect bus structure of claim 5 wherein the input signals of the host select circuit comprise all host data and control signals on the bus, the host select signal, the output signal being the current host data and control signal;
the host selection signal is generated by a slave arbitration selection logic state machine, the host selection circuit determines a currently effective host port according to the host selection signal and gives the control authority of the currently effective host port to a current host, and current host data and control signals are output; when the slave has no host port access, the current host data and control signal output keep in a constant state.
7. The scalable on-chip interconnect bus structure of claim 5, wherein the input signals of the slave registers comprise a slave configuration signal, a slave configuration clock and a reset signal; the slave configuration signal comprises a slave arbitration mode and an arbitration priority configuration;
the slave register stores the configuration of the slave arbitration mode and the arbitration priority, and outputs the priority mode and the configuration signal to the hierarchical arbitration logic circuit.
8. The expandable on-chip interconnection bus structure of claim 5, wherein the input signal of the slave arbitration selection logic state machine is an arbitration result of a slave arbitration selection logic circuit working clock and reset signal and a hierarchical arbitration logic circuit, and is output as a slave access state signal;
The slave arbitration selection logic state machine generates the latest host selection signal and the slave access state signal according to the arbitration result and the current slave controlled state, and the latest host selection signal is output to the hierarchical arbitration logic circuit and the host selection circuit.
9. The scalable on-chip interconnect bus structure of claim 5, wherein the hierarchical arbitration logic is configured to implement a hierarchical arbitration logic for the scalable bus, wherein the input signals are host selection signals, priority modes and configuration signals, and the output signals are respective host access priority arbitration results;
Each slave interface of the hierarchical arbitration logic circuit can conduct hierarchical configuration on priorities of all hosts on the expandable bus through a hierarchical arbitration logic structure, for any slave interface, the hosts under the same level complete arbitration based on one priority arbitration logic, the priority arbitration logic is different among different levels, the priority arbitration logic algorithm comprises a fixed priority comparison algorithm and a cyclic priority algorithm, and the different levels select different arbitration logic algorithms as arbitration logic of the level;
The workflow of the hierarchical arbitration logic circuit is that all host selection signals, priority modes and configurations and priority grouping configuration signals are used as the input of the priority grouping configuration circuit, and the corresponding host IDs are also used as the input of the priority grouping configuration circuit when the host selection signals are valid; the priority grouping configuration circuit groups all host selection signals according to the host IDs and the priority grouping configuration signals, inputs the priority modes and the configuration signals in the groups and the valid host selection signals in the same group into the hierarchical arbitration logic circuit, wherein each group comprises i hosts, j groups are all, and the host selection signals in the same group pass through the hierarchical arbitration logic circuit to output the priority in each host in the group; the priority group allocation circuit inputs all host selection signals in the group into the OR circuit, when any host selection signal in the group is valid, the host selection signals in all groups are input into the hierarchical arbitration logic circuit, and the circuit outputs the priorities of all groups; the group priority signal and the group priority results of all the hosts in the group are input into a priority combination circuit, the priority combination circuit executes the multiplication operation of the group priority of the host and the corresponding group priority, the access priority of each host is output, and the access priority of the host is used as an arbitration basis when a plurality of hosts access the slave at the same time.
10. The scalable on-chip interconnect bus structure of claim 9, wherein when the hierarchical arbitration logic circuit employs a fixed priority comparison algorithm, the hierarchical arbitration logic circuit directly outputs an input priority configuration of each host as each host priority arbitration result; if two hosts request to access the slave port, the host with higher priority will obtain the control authority to the slave port; when a host port sends a request to a slave port, the slave port checks whether the priority of the new requested host port is higher than the priority of the host port currently controlling the slave port; the slave port performs arbitration check at each clock edge, and if the priority of the newly requested host is higher than the priority of the host currently controlling the slave port, the newly requested host obtains the control authority of the slave port at the next clock edge; if the host currently controlling the slave port is executing burst transmission or locked transmission with a fixed length, whether the priority of the newly requested host is higher than that of the host currently executing access or not, the control authority of the slave port can be obtained only after the burst transmission or locked transmission is ended;
when the hierarchical arbitration logic circuit adopts a cyclic priority algorithm, each host port allocates a relative priority according to a physical host port number, compares the relative priority with the last host port performing transmission on a bus, and requests a host to obtain the control authority of the next transmission boundary slave by the highest priority; after the host obtains the control authority of the target slave, the host can execute data transmission to the port until another host sends a request to the same slave port; the next host is allowed to access the slave port at the next transfer boundary, and if the current master does not have a pending access request, then it is accessed in the next clock cycle.
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