CN118331388A - Bare chip and clock synchronization method - Google Patents
Bare chip and clock synchronization method Download PDFInfo
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
A bare chip and a clock synchronization method relate to the technical field of chips and solve the problem that clocks of a plurality of bare chips are not synchronized. The specific scheme is as follows: an output end of a first clock source in the first bare chip is coupled with an input end of the first output interface, and a first phase adjusting circuit is coupled with an output end of the first input interface; when the first clock source is used as a clock source of a reference clock, the first output interface is used for receiving a first clock signal of the first clock source and sending the first clock signal to the input interface and the first input interface of at least one second die through a reference network, the first clock signal is used for clock synchronization between the at least one second die and the first die, and the reference network is a signal path for communication between the at least one second die and the first die and between the first output interface and the first input interface; the first phase adjustment circuit is used for adjusting the clock phase of the first clock network according to the first clock signal.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a bare chip and clock synchronization method.
Background
Currently, as the demand for computing power by artificial intelligence increases, it has been difficult for a single die (die) to meet the increasing application scenario demands. In addition, the yield of a single die is low, resulting in high production costs. Thus, the die (chip) and 3D stack designs become hot spots for current chip designs, which can use multiple dies to integrate more functionality.
In a core particle, can splice according to the demand between the naked piece, can realize that 3D piles up, satisfies different application scenario, the yields of core particle is improved to the size of accessible rational control naked piece to reduce core particle manufacturing cost, improve the competitiveness of core particle. However, the design of the core particle is more difficult than the design of a single die, wherein, how to realize the full synchronization of clock signals among the dies, achieving the effect similar to the bus connection in the dies, is always a difficulty of research in the industry.
Disclosure of Invention
The embodiment of the application provides a bare chip and a clock synchronization method, which solve the problem that clocks of a plurality of bare chips in a chip system are not synchronous.
In order to achieve the above purpose, the following technical scheme is adopted in the embodiment of the application.
In a first aspect, an embodiment of the present application provides a first die including a first clock network, a first phase adjustment circuit, a first clock source, a first input interface, and a first output interface, an output of the first clock source coupled to an input of the first output interface, the first phase adjustment circuit coupled to an output of the first input interface; when the first clock source is used as a clock source of a reference clock, the first output interface is used for receiving a first clock signal of the first clock source and sending the first clock signal to the input interface and the first input interface of at least one second die through a reference network, the first clock signal is used for clock synchronization between the at least one second die and the first die, and the reference network is a signal path for communication between the at least one second die and the first die and between the first output interface and the first input interface; the first phase adjustment circuit is used for performing clock phase adjustment on the first clock network according to the first clock signal. The reference network may be, for example, a signal path composed of high-level metal.
Thus, the first clock source acts as the clock source for the reference clock, i.e., the first die acts as the master die. The first clock signal of the first clock source may be transmitted over the reference network to the input interface and the first input interface of the at least one second die. The first clock signal may be used as a phase discriminator of the first phase adjusting circuit, where phase discriminator may be understood as that the first phase adjusting circuit adjusts the clock signal of the first clock network of the first die based on the first clock signal, so that the phase of the clock network of each die in the chip system may be adjusted to be the same as the phase of the first clock signal, so as to achieve full synchronization of the clock signals of the dies in the chip system.
In one possible design, the second die includes a second clock network, a second phase adjustment circuit, a second clock source, a second input interface, and a second output interface, an output of the second clock source coupled to an input of the second output interface, and an output of the second phase adjustment circuit coupled to an output of the second input interface; when the second clock source is used as the clock source of the reference clock, the first input interface is used for receiving the second clock signal sent by the second output interface through the reference network and sending the second clock signal to the first phase adjustment circuit; the first phase adjustment circuit is used for adjusting the clock phase of the first clock network according to the second clock signal.
In this design, each die in the system-on-chip includes an independent clock source, the first die including a first clock source, and the second die including a second clock source. The clock source of each die in the chip system can be used as the clock source of the reference clock, so that the dies in the chip system can be spliced or cut at will.
In one possible design, the first die further includes a third input interface, a third output interface, and a multiplexer, an output of the third input interface being coupled to the multiplexer, an input of the third input interface being coupled to the reference network, an input of the third output interface being coupled to the first clock source, an output of the third output interface being coupled to the reference network, the first phase adjustment circuit being coupled to an output of the first input interface via the multiplexer.
In this design, the first die may be reserved with a third input interface, a third output interface, and a multiplexer for enabling flip-up and flip-down and flip-left. Wherein the multiplexer may be used to select the combination of the first input interface and the first output interface, or the combination of the third input interface and the third output interface.
In one possible design, the states of the first input interface, the first output interface, the third input interface, and the third output interface include a high impedance state; when the first clock source is used as a clock source of the reference clock and the first input interface and the first output interface are used as transmission interfaces of the first clock signal, the states of the third input interface and the third output interface are in a high-resistance state.
In the design, the states of the unused third input interface and the third output interface are set to be in a high-resistance state, so that the influence of the reserved input and output interfaces on a chip system can be reduced.
In one possible design, the state of the output interface of the at least one second die is a high impedance state when the first clock source is the clock source of the reference clock and the first input interface and the first output interface are the transmission interfaces of the first clock signal.
In the design, the states of the unused output interfaces in the chip system are all set to be in a high configuration, so that the influence of the unused output interfaces on the chip system can be reduced.
In one possible design, the first phase adjustment circuit includes a digital phase detector, a phase alignment unit, and a delay circuit, an output of the digital phase detector is coupled to the phase alignment unit, an output of the phase alignment unit is coupled to the delay circuit, and the delay circuit includes a plurality of delay units; a digital phase discriminator for comparing the phase difference between the first clock signal and the clock signal of the first clock network and outputting a digital control signal; and a phase alignment unit for adjusting the number of the turned-on delay units in the delay circuit based on the digital control signal to adjust the phase of the first clock signal.
In the design, when the first clock network is influenced by the voltage and temperature changes, the first phase adjusting circuit can adjust the phase of the clock signal of the first clock network in real time so as to ensure that the phase of the clock signal of the first clock network is the same as the phase of the first clock signal, and the influence of errors on the die can be effectively reduced.
In a second aspect, an embodiment of the present application provides a clock synchronization method applied to a first die, the first die including a first clock network, a first phase adjustment circuit, a first clock source, a first input interface, and a first output interface, an output of the first clock source being coupled to an input of the first output interface, the first phase adjustment circuit being coupled to an output of the first input interface, the method comprising: when the first clock source is used as a clock source of a reference clock, the first output interface is controlled to receive a first clock signal of the first clock source, and the first clock signal is sent to the input interface and the first input interface of at least one second die through a reference network, wherein the first clock signal is used for clock synchronization between the at least one second die and the first die, and the reference network is a signal path for communication between the at least one second die and the first die and between the first output interface and the first input interface; the first phase adjusting circuit is controlled to perform clock phase adjustment on the first clock network according to the first clock signal.
The advantages of the second aspect can be seen from the description of the first aspect.
In one possible design, the second die includes a second clock network, a second phase adjustment circuit, a second clock source, a second input interface, and a second output interface, an output of the second clock source coupled to an input of the second output interface, an output of the second phase adjustment circuit coupled to an output of the second input interface, the method further comprising: when the second clock source is used as the clock source of the reference clock, the first input interface is controlled to receive the second clock signal sent by the second output interface through the reference network, and the second clock signal is sent to the first phase adjusting circuit; the first phase adjusting circuit is controlled to perform clock phase adjustment on the first clock network according to the second clock signal.
In one possible design, the first die further includes a third input interface, a third output interface, and a multiplexer, an output of the third input interface being coupled to the multiplexer, an input of the third input interface being coupled to the reference network, an input of the third output interface being coupled to the first clock source, an output of the third output interface being coupled to the reference network, the first phase adjustment circuit being coupled to an output of the first input interface via the multiplexer.
In one possible design, the states of the first input interface, the first output interface, the third input interface, and the third output interface include a high impedance state; when the first clock source is used as a clock source of the reference clock and the first input interface and the first output interface are used as transmission interfaces of the first clock signal, the states of the third input interface and the third output interface are in a high-resistance state.
In one possible design, the state of the output interface of the at least one second die is a high impedance state when the first clock source is the clock source of the reference clock and the first input interface and the first output interface are the transmission interfaces of the first clock signal.
In one possible design, the first phase adjustment circuit includes a digital phase detector, a phase alignment unit, and a delay circuit, an output of the digital phase detector is coupled to the phase alignment unit, an output of the phase alignment unit is coupled to the delay circuit, the delay circuit includes a plurality of delay units, and the first phase adjustment circuit clocks the first clock network according to the first clock signal includes: controlling the digital phase discriminator to compare the phase difference between the first clock signal and the clock signal of the first clock network and outputting a digital control signal; the control phase alignment unit adjusts the number of turned-on delay units in the delay circuit based on the digital control signal to adjust the phase of the first clock signal.
In a third aspect, embodiments of the present application provide a chip system including at least two dies, the at least two dies including a first die; when a first clock source of the first die is used as a clock source of a reference clock, the first die sends first clock signals to input interfaces of at least two dies through a reference network, the first clock signals are used for clock synchronization of the at least two dies, and the reference network is a signal path for communication between the at least two dies and between an output interface and an input interface of each die; the at least two dies perform clock phase adjustment on a clock network of the at least two dies according to the first clock signal.
In a fourth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a printed circuit board and the first die of the first aspect, and the first die is electrically connected to the printed circuit board.
In a fifth aspect, embodiments of the present application provide a computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the clock synchronization method of any one of the above aspects and any one of the possible implementations.
In a sixth aspect, embodiments of the present application provide a computer program product which, when run on a computer or processor, causes the computer or processor to perform the clock synchronization method of any one of the above aspects and any one of the possible implementations.
It is to be understood that any of the first die, the chip system, the computer readable storage medium, the computer program product, etc. provided above may be applied to the corresponding method provided above, and thus, the advantages achieved by the method may refer to the advantages in the corresponding method, which are not described herein.
These and other aspects of the application will be more readily apparent from the following description.
Drawings
Fig. 1 is a schematic structural diagram of a clock splicing network circuit according to an embodiment of the present application;
Fig. 2 is a schematic structural diagram of an execution device according to an embodiment of the present application;
Fig. 3 is a schematic structural diagram of a chip system according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a first die 40 according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating another system-on-chip dicing according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating another system-on-chip cutting provided in an embodiment of the present application;
Fig. 7 is a schematic structural diagram of a 3D stacked chip system according to an embodiment of the present application;
fig. 8 is a flowchart of a clock synchronization method according to an embodiment of the present application.
Detailed Description
For ease of understanding, a description of some of the concepts related to the embodiments of the application are given by way of example for reference. The following is shown:
The H-tree, a structure of a clock tree, has a physical form similar to the letter H, and is thus named H-tree. Each level of drivers of the H-tree is physically connected by an H-shaped metal network, gradually expanding from the root of the clock tree and covering all drivers.
Spine-tree (spine-tree), a structure of a clock tree. The spine-tree is a two-layer architecture, devices in the spine-tree are bidirectional traffic, and input devices are output devices.
Interposer (interposer): a silicon interposer, logic chips placed on the interposer are connected by through silicon vias (through silicon via, TSVs) microelectrodes.
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Wherein, in the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "plurality" means two or more than two.
The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a clock splicing network circuit according to an embodiment of the present application. The clock splicing network circuit comprises a master phase locked loop (phase locked loop, PLL), a global clock tree (global tree), a plurality of calibration control units (ALIGNMENT CONTROL, AC), a plurality of variable delays (DELAY ELEMENT, VDE), a plurality of local clock networks (local mesh) and a plurality of Phase Detectors (PD). Wherein AC includes AC1, AC2 and AC3, VDE includes VDE1, VDE2 and VED3, local clock network includes local clock network 1, local clock network 2 and local clock network 3, and PD includes PD1 and PD2. After the main PLL generates clock signals, the clock signals are respectively sent to the calibration control unit and the variable delay through a global clock tree, wherein the global clock tree is basically symmetrical or has a topological structure meeting equal delay. After receiving the clock signals, the calibration control unit and the variable delay device can adjust the phases of the clock signals according to the phase detection result of the phase detector until the phase detector judges that the phases of the two input clock signals are synchronous. For example, if the clock signals of the local clock network 1 and the local clock network 2 have a phase deviation, AC2 and VDE2 corresponding to the local clock network 2 are adjusted until the PD1 determines that the phases of the local clock network 1 and the local clock network 2 are synchronized. By this method, the clock phases of the local clock network 1, the local clock network 2 and the local clock network 3 can be aligned, and clock synchronization between the local clock networks can be realized.
However, after the multiple dies are coupled, there is no clock source in the circuit to provide the local clock networks for phase alignment, and when the multiple local clock networks have phase changes due to the influence of on-chip errors (on chip variation, OCV), there may be a case that the phase compensation is not timely or is misplaced. And the scheme in fig. 1 has no function of cutting and splicing, in the scheme, local clock networks are cascaded, the middle local clock network cannot be cut, or a cascade chain cannot be used for deleting any ring, otherwise, the scheme cannot work. Meanwhile, after the topological structure of the scheme is fixed, a new local clock network cannot be spliced again to enter a chain of the local clock network.
Thus, embodiments of the present application provide a first die that is applied to a chip system. The chip system will be described first.
The chip system (chip system) may be applied to different devices, such as the execution device 20 shown in fig. 2, and fig. 2 is a schematic structural diagram of an execution device according to an embodiment of the present application. The executing device 20 may be a terminal, such as a server 21, a mobile phone terminal 22, a tablet computer 23, a notebook computer 24, an augmented reality (augmented reality, AR) device (not shown in fig. 2), a Virtual Reality (VR) device (not shown in fig. 2), an in-vehicle terminal (not shown in fig. 2), or the like.
The chip system comprises a plurality of dies (die) which have specific functions and can be assembled in a modularized mode, for example, the dies can realize functions of data storage, calculation, signal processing, data flow management and the like. Based on the rich intellectual property core (intellectual property core, IP) reserves, the chiplet system proposes the concept of IP chipping (IP AS A CHIPLET, IAAC) aimed at realizing "plug and play" of special function IP with a die. For example, for some core processor IPs, the die may be a graphics processor (graphics processing unit, GPU) IP, a neural-network unit (NPU) IP, a video processor (video processing unit, VPU) IP, a digital signal processor (DIGITAL SIGNAL processing, DSP) IP, an image signal processor (IMAGE SIGNAL processor, ISP) IP, a display processor IP, and so on. Furthermore, the die may also be digital-analog hybrid IP, radio frequency IP, etc.
The chiplet system of the present application may also be referred to as a chiplet system or a core particle system. I.e. the die may also be referred to as a chiplet or a die.
The chip system may be applied to a system-on-a-chip (SoC) with a plurality of dies integrated thereon, for example, the chip system includes a first die and a second die as shown in fig. 3, and fig. 3 is a schematic structural diagram of a chip system according to an embodiment of the present application. A first clock signal may be transmitted between the first die and the second die.
For example, a first clock signal of a first die may be used as a reference clock signal, the first die phase-controlling a first clock network based on the first clock signal, and a second die phase-controlling a second clock network based on the first clock signal to synchronize phases of the first clock network and the second clock network, thereby achieving phase alignment of clock signals of the respective dies in the chip system.
With the above chip system applied, the first die provided in the embodiment of the application is described below.
An embodiment of the present application provides a first die 40, as shown in fig. 4, and fig. 4 is a schematic structural diagram of the first die 40 according to an embodiment of the present application. The first die 40 includes a first clock network 41, a first phase adjustment circuit 42, a first clock source 43, a first input interface 44, and a first output interface 45. An output of the first clock source 43 is coupled to an input of the first output interface 45 and the first phase adjustment circuit 42 is coupled to an output of the first input interface 44.
The first clock source 43 may be, for example, a phase locked loop (phase locked loop, PLL) circuit. In the PLL circuit, the frequency and phase of an oscillation signal in a loop are controlled by an externally input reference signal, and the frequency of an input signal is automatically tracked by the frequency of an output signal. In addition, the first clock network 41 may be a clock tree structure, and after the first clock network 41 receives the clock signal, the clock signal is transmitted to each area of the first die 40. The first clock network 41 may be an H-tree, a spine-tree, or a general clock tree.
Illustratively, the first input interface 44 and the first output interface 45 may be input/output (I/O) interfaces, wherein the first input interface 44 may be set to an input state and the first output interface 45 may be set to an output state.
The first output interface 45 is configured to receive a first clock signal of the first clock source 43 when the first clock source 43 is used as a clock source of a reference clock, and send the first clock signal to the input interface of the at least one second die and the first input interface 44 through a reference network (golden mesh), where the first clock signal is used to clock the at least one second die with the first die 40, and the reference network is a signal path for communication between the at least one second die and the first die 40 and between the first output interface 45 and the first input interface 44.
Illustratively, a golden mesh may be a signal path composed of a high-level metal, which may be a metal level of an interposer or within a 3D stacked die. The golden mesh may be a symmetrical structure to ensure that the phases of the first clock signals sent through the golden mesh to the input interfaces of the individual die are consistent. Meanwhile, the golden mesh should be arranged in the central area of the chip system, so that the delay of the golden mesh is ensured to be small enough.
Golden mesh is considered to be less affected by changes in voltage and temperature. One of the factors is that since the path of the first clock signal from the first clock source 43 to the golden mesh is a common path, each die receives the first clock signal and then passes through the input interface, so that the delay of the overall path of the first clock signal is smaller. Another factor is that the golden mesh is a high-level metal, and the driving current of the input interface is relatively large, so that the golden mesh is also less affected by voltage and temperature. Thus, the input interface of at least one second die and the first clock signal received at the first input interface 44 may be considered to be the same phase clock signal.
Wherein the input of the input interface of the first die 40 and the at least one second die is coupled to the golden mesh and the output of the output interface of the first die 40 and the at least one second die is coupled to the golden mesh. I.e. the input of the first input interface 44 and the output of the first output interface 45 are coupled via a golden mesh, the output of the first output interface 45 is also coupled via a golden mesh and the input of the input interface of the at least one second die, and the first clock signal can be transmitted via the golden mesh to the input interface of the at least one second die and the first input interface 44.
Thus, for the first die 40, the first clock source 43 generates a first clock signal and transmits the first clock signal to the first output interface 45, and the first output interface 45 transmits the first clock signal to the golden mesh. After the first clock signal reaches the golden mesh, the golden mesh may be considered to transmit the first clock signal to both the input interface of the second die and the first input interface 44 due to the small delay of the golden mesh.
The first phase adjustment circuit 42 is configured to perform clock phase adjustment on the first clock network 41 according to the first clock signal.
For the first die 40, after the first input interface 44 receives the first clock signal, the first clock signal is phase-discriminated, i.e. the phase of the first clock network 41 is adjusted by comparing the phase of the end clock of the first clock network 41 with the phase of the first clock signal until the phase of the end clock of the first clock network 41 and the phase of the first clock signal are within an error range. In one example, the phase of the end clock of the first clock network 41 is the same as the phase of the first clock signal.
Therefore, the phases of the clock networks of all the bare chips in the chip system are the same as the phases of the first clock signals, and the phases of the clock networks of all the bare chips in the chip system can be considered to be the same, so that the full synchronization of the clock signals of all the bare chips in the chip system is realized.
The second die includes a second clock network, a second phase adjustment circuit, a second clock source, a second input interface, and a second output interface. An output of the second clock source is coupled to an input of the second output interface, and the second phase adjustment circuit is coupled to an output of the second input interface.
When the second clock source is used as the clock source of the reference clock, the first input interface 44 is configured to receive the second clock signal sent by the second output interface through the reference network, and send the second clock signal to the first phase adjustment circuit 42. The first phase adjustment circuit 42 is configured to perform clock phase adjustment on the first clock network 41 according to the second clock signal.
Illustratively, each die in the system-on-chip includes an independent clock source. In an embodiment of the present application, the first die 40 includes a first clock source 43, the second die includes a second clock source, and so on. The clock source of each die in the system-on-chip may be used as a reference clock, which may be set by those skilled in the art as desired.
If the second clock source is used as the clock source of the reference clock, the second clock signal generated by the second clock source is transmitted to the reference network, the first input interface 44 of the first die 40 transmits the second clock signal to the first phase adjustment circuit 42, and the first phase adjustment circuit 42 adjusts the phase of the clock signal of the first clock network 41 based on the phase of the second clock signal, so that the phase of the clock signal of the first clock network 41 is the same as the phase of the second clock signal. Other dies in the chip system may also do the same processing as the first die 40. For example, in the second die, after the second input interface receives the second clock signal, the second phase adjustment circuit performs clock phase control on the second clock network according to the second clock signal. Therefore, the phase of the clock network of each bare chip is the same as the second clock signal, and the clock signal full synchronization of the chip system is realized.
With continued reference to fig. 4, the first die 40 also includes a third input interface 46, a third output interface 47, and a multiplexer (Mux) 48. An output of the third input interface 46 is coupled to a multiplexer 48, an input of the third input interface 46 is coupled to a reference network, an input of the third output interface 47 is coupled to the first clock source 43, an output of the third output interface 47 is coupled to the reference network, and an output of the first phase adjustment circuit 42 and the first input interface 44 are coupled via the multiplexer 48.
Illustratively, to achieve a flip-up and flip-down, side-to-side, spliceable first die may be reserved with a third input interface 46, a third output interface 47, and a multiplexer 48, the multiplexer 48 may be used to select a combination of the first input interface 44 and the first output interface 45, or a combination of the third input interface 46 and the third output interface 47. The third output interface 47 can also be used to receive the first clock signal of the first clock source 43 and to transmit the first clock signal via the reference network to the input interface of the at least one second die and to the first input interface 44. The third input interface 46 may also be used to receive the first clock signal over the reference network.
At this time, the golden mesh sends the first clock signal to the first input interface 44 or the third input interface 46, and then selects one first clock signal to send to the first clock network 41 of the first die 40 through the multiplexer 48 for use. Since the delay to golden mesh is small enough and the input interface and multiplexer 48 is passed into each die, the clock network of each die has the same phase.
Optionally, the states of the first input interface 44, the first output interface 45, the third input interface 46, and the third output interface 47 include a high impedance state (HIGH IMPEDANCE). When the first clock source 43 is used as a clock source of the reference clock and the first input interface 44 and the first output interface 45 are used as transmission interfaces of the first clock signal, the states of the third input interface 46 and the third output interface 47 are in a high-impedance state.
Illustratively, a high impedance state is a state that is neither high nor low, and setting an input interface or an output interface to a high impedance state is equivalent to removing the effect of the input interface or the output interface from a subsequent circuit. In the embodiment of the present application, if the first input interface 44 and the first output interface 45 are selected as the transmission interfaces of the first clock signal, the states of the third input interface 46 and the third output interface 47 are set to be in the high-impedance state, and the third input interface 46 and the third output interface 47 may be considered to have no influence on the next stage circuit. Thus, the unused third input interface 46 and third output interface 47 are set to a high-impedance state, so that the influence of the reserved input/output interface on the chip system can be reduced.
Optionally, when the first clock source 43 is used as a clock source of the reference clock and the first input interface 44 and the first output interface 45 are used as transmission interfaces of the first clock signal, the output interface of the at least one second die is in a high impedance state.
Because the phase of the clock signal generated based on the clock source of one die is identified in the embodiment of the application, the phase of the clock network of each die in the chip system is adjusted. Thus, if the first clock source 43 is used as the reference clock and the first input interface 44 and the first output interface 45 are used as the transmission interfaces of the first clock signal, the states of the unused output interfaces in the chip system are all set to be in the high configuration except for the first output interface 45 of the first die 40, so that the influence of the unused output interfaces on the chip system can be reduced.
With continued reference to fig. 4, the first phase adjustment circuit 42 may include a digital Phase Detector (PD) 421, a phase alignment unit (PHASE ALIGNMENT, PA) 422, and a delay circuit 423, where an output of the digital phase detector 421 is coupled to the phase alignment unit 422, an output of the phase alignment unit 422 is coupled to the delay circuit 423, and the delay circuit 423 includes a plurality of delay units. The digital phase detector 421 is configured to compare a phase difference between the first clock signal and the clock signal of the first clock network 41, and output a digital control signal. The phase alignment unit 422 is used for adjusting the number of turned-on delay units in the delay circuit 423 based on the digital control signal to adjust the phase of the first clock signal.
The digital phase detector 421 may be a circuit that makes a certain relationship between the output level and the phase difference between the two input signals, that is, the digital control signal output by the digital phase detector 421 has a certain relationship with the phase difference between the first clock signal and the clock signal of the first clock network 41. In one example, the digital control signal may be low if there is a phase difference between the first clock signal and the clock signal of the first clock network 41. The digital control signal may be high if there is no phase difference between the first clock signal and the clock signal of the first clock network 41. The digital control signal may be high if there is a phase difference between the first clock signal and the clock signal of the first clock network 41. The digital control signal may be low if there is no phase difference between the first clock signal and the clock signal of the first clock network 41.
The phase of the first clock signal can be adjusted by adjusting the number of turns on of the delay cells. In one example, if the phase of the clock signal of the first clock network 41 is smaller than the phase of the first clock signal, the number of turns on of the delay unit is reduced. If the phase of the clock signal of the first clock network 41 is greater than the phase of the first clock signal, the number of turned-on delay units is increased.
When the first clock network 41 is affected due to the voltage and temperature changes, the first phase adjusting circuit 42 can adjust the phase of the clock signal of the first clock network 41 in real time to ensure that the phase of the clock signal of the first clock network 41 is the same as the phase of the first clock signal, so as to effectively reduce the influence of the on-die errors.
Fig. 5 is a schematic diagram of dicing a chip system according to another embodiment of the present application, as shown in fig. 5. Shown in fig. 5 is a four DIE tiled chip system, DIE0, DIE1, DIE2, and DIE3, respectively. Depending on the scene, a chip system spliced by two dies or a chip system spliced by three dies may also be implemented. The golden mesh is arranged in the central area of the four bare chips, so that the golden mesh is small enough, the time delay of the golden mesh is small as much as possible, and the quality of a clock signal is not attenuated. Since the golden mesh is symmetrically designed, arbitrary cutting can be realized, the internal circuit of each bare chip is symmetrically designed, and arbitrary splicing can be realized after rotation. One of the cutting schemes is shown in fig. 5, the cutting areas are DIE1 and DIE3, and the cut DIE0 and DIE2 can still realize clock synchronization. Another cutting scheme is shown in fig. 6, where the cutting area is DIE3, and the cut DIE0, DIE1, and DIE2 can still achieve clock synchronization.
In addition, the chip system provided by the embodiment of the application can also be applied to a 3D stacking scene, as shown in fig. 7, fig. 7 is a schematic structural diagram of the 3D stacking chip system provided by the embodiment of the application. One bottom DIE (bottom DIE) and two top DIEs (top DIE) are shown in fig. 7, and both the bottom DIE and the top DIE may be a one to four splice-able combination, or the bottom DIE and the top DIE may be a combination of different processes. The golden mesh distributes the first clock signal to each bottom DIE and top DIE, receives the first clock signal through the input interface of each DIE, and adjusts the phase of the clock signal of the clock network of each DIE through the phase adjusting circuit of each DIE so as to realize the clock full synchronization of each DIE.
As shown in fig. 8, fig. 8 is a flowchart of a clock synchronization method according to an embodiment of the present application. The method comprises the following flow.
In step 801, when the first clock source is used as a clock source of the reference clock, the execution device controls the first output interface to receive a first clock signal of the first clock source, and sends the first clock signal to the input interface and the first input interface of the at least one second die through the reference network, where the first clock signal is used for clock synchronization between the at least one second die and the first die, and the reference network is a signal path for communication between the at least one second die and the first die and between the first output interface and the first input interface.
Step 802, the execution device controls the first phase adjustment circuit to perform clock phase adjustment on the first clock network according to the first clock signal.
The first clock signal of the first clock source may be transmitted to the input interface of each die through the reference network, so that the first clock signal may perform phase discrimination, where phase discrimination may be understood as that the first phase adjusting circuit adjusts the clock signal of the first clock network of the first die based on the first clock signal, so that the phase of the clock network of each die in the chip system may be adjusted to be the same as the phase of the first clock signal, and full synchronization of the clock signals of the dies in the chip system may be achieved. The implementation of step 801 and step 802 may be found in the description of the first die above.
Step 803, when the second clock source is used as the clock source of the reference clock, the execution device controls the first input interface to receive the second clock signal sent by the second output interface through the reference network, and sends the second clock signal to the first phase adjustment circuit.
Step 804, the execution device controls the first phase adjustment circuit to perform clock phase adjustment on the first clock network according to the second clock signal.
In some embodiments, each die in the chip system includes an independent clock source, the first die includes a first clock source, the second die includes a second clock source, and so on. The clock source of each die in the chip system can be used as a reference clock, so that the dies in the chip system can be spliced or cut at will. The implementation of step 803 and step 804 may also be referred to the description of the first die above.
Step 802 may include, among other things: the execution device controls the digital phase detector to compare a phase difference between the first clock signal and the clock signal of the first clock network and output a digital control signal. The execution device controls the phase alignment unit to adjust the number of turned-on delay units in the delay circuit based on the digital control signal to adjust the phase of the first clock signal.
The embodiment of the application also provides a chip system, which comprises at least two bare chips, wherein the at least two bare chips comprise a first bare chip. When the first clock source of the first die is used as the clock source of the reference clock, the first die sends a first clock signal to the input interfaces of at least two dies through a reference network, the first clock signal is used for clock synchronization of the at least two dies, and the reference network is a signal path for communication between the at least two dies and between the output interface and the input interface of each die. The at least two dies adjust clock phases of the at least two dies according to the first clock signal.
The embodiment of the application also provides electronic equipment, which comprises a printed circuit board and a first bare chip, wherein the first bare chip is electrically connected with the printed circuit board.
Embodiments of the present application also provide a computer storage medium having stored therein computer instructions which, when executed on an electronic device, cause the electronic device to perform the above-described related method steps to implement the clock synchronization method of the above-described embodiments.
Embodiments of the present application also provide a computer program product which, when run on a computer, causes the computer to perform the above-described related steps to implement the clock synchronization method performed by the electronic device in the above-described embodiments.
It will be appreciated by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another apparatus, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and the parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a device (may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (14)
1. A first die comprising a first clock network, a first phase adjustment circuit, a first clock source, a first input interface, and a first output interface, an output of the first clock source coupled to an input of the first output interface, and an output of the first phase adjustment circuit coupled to the first input interface;
The first output interface is configured to receive a first clock signal of the first clock source when the first clock source is used as a clock source of a reference clock, and send the first clock signal to an input interface of at least one second die and the first input interface through a reference network, where the first clock signal is used for clock synchronization between the at least one second die and the first die, and the reference network is a signal path for communication between the at least one second die and the first die and between the first output interface and the first input interface;
The first phase adjustment circuit is used for adjusting the clock phase of the first clock network according to the first clock signal.
2. The first die of claim 1, wherein the second die comprises a second clock network, a second phase adjustment circuit, a second clock source, a second input interface, and a second output interface, an output of the second clock source coupled to an input of the second output interface, the second phase adjustment circuit coupled to an output of the second input interface;
When the second clock source is used as the clock source of the reference clock, the first input interface is used for receiving a second clock signal sent by the second output interface through the reference network and sending the second clock signal to the first phase adjustment circuit;
The first phase adjustment circuit is used for adjusting the clock phase of the first clock network according to the second clock signal.
3. The first die of claim 1 or 2, further comprising a third input interface, a third output interface, and a multiplexer, an output of the third input interface coupled to the multiplexer, an input of the third input interface coupled to the reference network, an input of the third output interface coupled to the first clock source, an output of the third output interface coupled to the reference network, and an output of the first phase adjustment circuit coupled to the first input interface via the multiplexer.
4. The first die of claim 3, wherein states of the first input interface, the first output interface, the third input interface, and the third output interface comprise a high impedance state;
when the first clock source is used as a clock source of a reference clock and the first input interface and the first output interface are used as transmission interfaces of first clock signals, the states of the third input interface and the third output interface are in the high-resistance state.
5. The first die of claim 4, wherein the state of the output interface of the at least one second die is a high impedance state when the first clock source is the clock source of the reference clock and the first input interface and the first output interface are the transmission interfaces of the first clock signal.
6. The first die of claim 1, wherein the first phase adjustment circuit comprises a digital phase detector, a phase alignment unit, and a delay circuit, an output of the digital phase detector being coupled to the phase alignment unit, an output of the phase alignment unit being coupled to the delay circuit, the delay circuit comprising a plurality of delay units;
the digital phase discriminator is used for comparing the phase difference between the first clock signal and the clock signal of the first clock network and outputting a digital control signal;
The phase alignment unit is used for adjusting the number of the turned-on delay units in the delay circuit based on the digital control signal so as to adjust the phase of the first clock signal.
7. A method of clock synchronization, the method being applied to a first die, the first die including a first clock network, a first phase adjustment circuit, a first clock source, a first input interface, and a first output interface, an output of the first clock source being coupled to an input of the first output interface, the first phase adjustment circuit being coupled to an output of the first input interface, the method comprising:
When the first clock source is used as a clock source of a reference clock, the first output interface is controlled to receive a first clock signal of the first clock source, and the first clock signal is sent to an input interface of at least one second die and the first input interface through a reference network, wherein the first clock signal is used for clock synchronization of the at least one second die and the first die, and the reference network is a signal path for communication between the at least one second die and the first die and between the first output interface and the first input interface;
and controlling the first phase adjustment circuit to perform clock phase adjustment on the first clock network according to the first clock signal.
8. The method of claim 7, wherein the second die comprises a second clock network, a second phase adjustment circuit, a second clock source, a second input interface, and a second output interface, an output of the second clock source coupled to an input of the second output interface, the second phase adjustment circuit coupled to an output of the second input interface, the method further comprising:
When the second clock source is used as the clock source of the reference clock, the first input interface is controlled to receive a second clock signal sent by the second output interface through the reference network, and the second clock signal is sent to the first phase adjustment circuit;
And controlling the first phase adjustment circuit to perform clock phase adjustment on the first clock network according to the second clock signal.
9. The method of claim 7 or 8, wherein the first die further comprises a third input interface, a third output interface, and a multiplexer, an output of the third input interface being coupled to the multiplexer, an input of the third input interface being coupled to the reference network, an input of the third output interface being coupled to the first clock source, an output of the third output interface being coupled to the reference network, and an output of the first phase adjustment circuit being coupled to the first input interface through the multiplexer.
10. The method of claim 9, wherein the states of the first input interface, the first output interface, the third input interface, and the third output interface comprise a high impedance state;
when the first clock source is used as a clock source of a reference clock and the first input interface and the first output interface are used as transmission interfaces of first clock signals, the states of the third input interface and the third output interface are in the high-resistance state.
11. The method of claim 10, wherein the state of the output interface of the at least one second die is a high impedance state when the first clock source is the clock source of the reference clock and the first input interface and the first output interface are the transmission interfaces of the first clock signal.
12. The method of claim 7, wherein the first phase adjustment circuit comprises a digital phase detector, a phase alignment unit, and a delay circuit, the output of the digital phase detector being coupled to the phase alignment unit, the output of the phase alignment unit being coupled to the delay circuit, the delay circuit comprising a plurality of delay units, the first phase adjustment circuit clocking the first clock network in accordance with the first clock signal comprising:
controlling the digital phase detector to compare the phase difference between the first clock signal and the clock signal of the first clock network and outputting a digital control signal;
The phase alignment unit is controlled to adjust the number of turned-on delay units in the delay circuit based on the digital control signal to adjust the phase of the first clock signal.
13. A chip system, the chip system comprising at least two dies, the at least two dies comprising a first die;
when a first clock source of the first die is used as a clock source of a reference clock, the first die sends the first clock signal to an input interface of at least two dies through a reference network, the first clock signal is used for clock synchronization of the at least two dies, and the reference network is a signal path for communication between the at least two dies and between an output interface and an input interface of each die;
the at least two dies perform clock phase adjustment on a clock network of the at least two dies according to the first clock signal.
14. An electronic device comprising a printed circuit board and the first die of any of claims 1 to 6, the first die being electrically connected to the printed circuit board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310073613.7A CN118331388A (en) | 2023-01-11 | 2023-01-11 | Bare chip and clock synchronization method |
| PCT/CN2023/119399 WO2024148847A1 (en) | 2023-01-11 | 2023-09-18 | Die and clock synchronization method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310073613.7A CN118331388A (en) | 2023-01-11 | 2023-01-11 | Bare chip and clock synchronization method |
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| CN202310073613.7A Pending CN118331388A (en) | 2023-01-11 | 2023-01-11 | Bare chip and clock synchronization method |
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| WO (1) | WO2024148847A1 (en) |
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| TWI449339B (en) * | 2010-12-13 | 2014-08-11 | Ind Tech Res Inst | Apparatus for clock skew compensation |
| US9030253B1 (en) * | 2012-05-30 | 2015-05-12 | Altera Corporation | Integrated circuit package with distributed clock network |
| US9413364B2 (en) * | 2014-07-09 | 2016-08-09 | Intel Corporation | Apparatus and method for clock synchronization for inter-die synchronized data transfer |
| US9577649B1 (en) * | 2016-03-14 | 2017-02-21 | Altera Corporation | Methods and apparatus for reducing power in clock distribution networks |
| CN114527831A (en) * | 2022-02-07 | 2022-05-24 | Oppo广东移动通信有限公司 | Chip, neural network processor and manufacturing method of chip |
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