CN118324092A - Sensor preparation method and sensor - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 238000000151 deposition Methods 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000008021 deposition Effects 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000007789 sealing Methods 0.000 claims abstract description 15
- 238000001465 metallisation Methods 0.000 claims abstract description 8
- 238000003466 welding Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000227 grinding Methods 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 19
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- -1 aluminum germanium Chemical compound 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 244000126211 Hericium coralloides Species 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Abstract
The application relates to a sensor preparation method and a sensor, wherein the method comprises the following steps: performing oxide deposition on the first wafer, and performing patterned etching on the oxide deposited on the first side of the first wafer; silicon deposition and doping are carried out on the first side of the first wafer to form a first polysilicon layer, so that the first polysilicon layer is used as a first conductive layer; oxide deposition is carried out on the first conductive layer, and the deposited oxide is subjected to graphical etching to obtain an insulating layer; performing silicon deposition and doping on the insulating layer to form a second polysilicon layer to serve as a second conductive layer; bonding the second wafer with the second conductive layer; carrying out metal deposition on the second side of the first wafer to obtain a metal layer; etching the second side of the first wafer to generate a sensitive structure, and releasing at least part of the sensitive structure; bonding the sealing cover layer with bonding points on the second side of the first wafer, and exposing welding spots. And a polycrystalline silicon epitaxial process is not needed, so that the process is simplified, and the preparation cost is reduced.
Description
The present application claims priority from China patent office filed on line 08 and 07 of 2023, application number 202310986069.5, and Chinese patent application entitled "sensor preparation method and sensor", the entire contents of which are incorporated herein by reference.
Technical Field
The application relates to the technical field of sensing, in particular to a sensor preparation method and a sensor.
Background
With the development of technology and the continuous progress of society, inertial sensors are increasingly classified, such as MEMS (Micro Electro MECHANICAL SYSTEM ) accelerometers, gyroscopes, IMUs (Inertial Measurement Unit ), and the like. The inertial sensor comprises a sensitive structure layer, a substrate and a sealing cover, wherein the sensitive structure layer is positioned between the substrate and the sealing cover. The sensitive structure layer needs to be robust, stable and reliable, so that the anchor point of the sensitive structure layer needs to be stably connected with the substrate.
The conventional sensor is manufactured by forming a polysilicon layer on an oxide layer by using an EPI (epitaxial) process, then forming a sensitive structure by using a deep silicon etching technique (DEEP REACTIVE ion etching, DRIE), and then releasing the sensitive structure by using silicon oxide etching to make it movable, thereby forming a sensitive structure layer. Sensitive structure layers due to the requirements on sensor sensitivity, weight of the mass, and device roughness, thicker polysilicon deposition is often required to build up the sensitive structure layer. But the EPI process has great process difficulty, difficult realization and high cost when depositing thicker polysilicon. The traditional sensor preparation method has the defect of high preparation cost.
Disclosure of Invention
In view of the above, it is desirable to provide a sensor manufacturing method and a sensor that can reduce manufacturing costs.
A method of manufacturing a sensor, comprising:
performing oxide deposition on a first wafer, and performing patterned etching on the oxide deposited on the first side of the first wafer;
Performing silicon deposition and doping on the first side of the first wafer to form a first polysilicon layer to serve as a first conductive layer; the first conductive layer is at least partially used for electrical connection;
performing oxide deposition on the first conductive layer, and performing patterned etching on the deposited oxide to obtain an insulating layer;
performing silicon deposition and doping on the insulating layer to form a second polysilicon layer to serve as a second conductive layer; the second conductive layer is at least partially used for electrical connection;
Bonding a second wafer to the second conductive layer; the second wafer is used for electric connection;
carrying out metal deposition on the second side of the first wafer to obtain a metal layer; the metal layer comprises welding spots and bonding points;
Etching the second side of the first wafer to generate a sensitive structure, and releasing at least part of the sensitive structure;
And bonding the sealing cover layer with the bonding point of the second side of the first wafer, and exposing the welding point.
In one embodiment, the bonding the second wafer to the second conductive layer includes: and grinding the second conductive layer, and bonding the second wafer and the ground second conductive layer.
In one embodiment, the thickness of the second conductive layer prior to polishing is greater than or equal to 0.5 microns.
In one embodiment, the roughness of the ground second conductive layer is less than or equal to 4 nanometers.
In one embodiment, the bonding the second wafer to the second conductive layer includes: and generating a first medium conducting layer on the second conducting layer, generating a second medium conducting layer on the second wafer, and bonding the second wafer with the second conducting layer through the first medium conducting layer and the second medium conducting layer.
In one embodiment, the depositing the metal on the second side of the first wafer to obtain a metal layer includes: and carrying out surface thinning on the second side of the first wafer, and then depositing metal to obtain a metal layer.
In one embodiment, the etching the second side of the first wafer to generate a sensitive structure and at least releasing a part of the sensitive structure includes: etching the second side of the first wafer to generate a comb electrode structure as a sensitive structure, corroding the exposed oxide of the first side of the first wafer, and releasing the movable electrode in the comb electrode structure.
In one embodiment, the insulating layer has a thickness greater than or equal to 0.3 microns.
In one embodiment, the metal layer is an aluminum layer or an aluminum germanium layer.
In one embodiment, the second conductive layer is for grounding and the second wafer is for grounding.
The sensor comprises a first wafer, a first conductive layer, an insulating layer, a second conductive layer, a second wafer, a metal layer and a sealing cover layer, and is prepared by the method.
According to the sensor preparation method and the sensor, oxide deposition is carried out on the first wafer, patterned etching is carried out on the oxide deposited on the first side of the first wafer, and then silicon deposition and doping are carried out on the first side of the first wafer to form the first polycrystalline silicon layer to serve as the first conducting layer. And performing oxide deposition on the first conductive layer, performing patterned etching on the deposited oxide to obtain an insulating layer, and performing silicon deposition and doping on the insulating layer to form a second polysilicon layer serving as the second conductive layer. After bonding the second wafer and the second conductive layer, performing metal deposition on the second side of the first wafer to obtain a metal layer, etching the second side of the first wafer to generate a sensitive structure, releasing at least part of the sensitive structure, bonding the sealing cover layer and bonding points of the second side of the first wafer, exposing welding spots, and completing the preparation of the sensor. After the second wafer and the second conductive layer are bonded, a metal layer can be manufactured on the first wafer after the wafer is turned over, a sensitive structure is generated, a polysilicon epitaxial process is not needed, the process is simplified, and the preparation cost is reduced.
Drawings
FIG. 1 is a flow chart of a method of manufacturing a sensor in one embodiment;
fig. 2 to 8 are schematic structural views of a sensor manufacturing process in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In one embodiment, as shown in fig. 1, there is provided a sensor manufacturing method comprising:
Step S110: and performing oxide deposition on the first wafer, and performing patterned etching on the oxide deposited on the first side of the first wafer. The oxide may be silicon oxide. As shown in fig. 2, the first Wafer a includes a first side and a second side opposite to the first side, and may be subjected to pretreatment, such as polishing, for example. Oxide deposition is then performed on the first Wafer a, which may be single-sided or double-sided. In this embodiment, the surface of the first Wafer a is polished on both sides, and then the silicon oxide is deposited on both sides of the first Wafer a, and patterning the silicon oxide deposited on the first side of the first Wafer A, etching away part of the silicon oxide, and taking the rear surface of the silicon oxide layer as a sacrificial layer.
Step S120: and carrying out silicon deposition and doping on the first side of the first wafer to form a first polysilicon layer to serve as a first conductive layer. Wherein the first conductive layer is at least partially used for electrical connection. As shown in fig. 3, conductivity is increased by performing silicon deposition on the first side of the first Wafer a while doping to form P-type polysilicon, or forming N-type polysilicon. The polysilicon is patterned, part of the polysilicon is etched and removed to form a first polysilicon layer poly1, so that the first polysilicon layer poly1 is used as the first conductive layer 11, the pattern is simplified, the process is simplified, and better conductive effect and structural strength can be achieved. By patterning the etching such that the first conductive layer 11 is divided into a plurality of parts, the sensitive structure layer of the subsequent sensor is connected to the external electrode for signal acquisition through the part of the first conductive layer 11 (i.e., the first polysilicon layer poly 1) for electrical connection. In addition, as shown in fig. 3, after the silicon oxide layer (i.e., the sacrificial layer) is patterned and etched in step S110, at least one notch is formed in the silicon oxide layer, and a part of the first conductive layer 11 is in contact with the first Wafer a through the notch, and another part is spaced apart from the first Wafer a through the silicon oxide layer. After the sensitive structure layer is formed by the subsequent first wafer A, the part, which is contacted with the sensitive structure layer, of the first conductive layer 11 plays an anchoring role on the sensitive structure layer, the part, which is arranged between the first conductive layer 11 and the sensitive structure layer, is opposite to the sensitive structure after the corresponding silicon oxide layer is removed, the sensitive structure is used as a movable electrode, and the part, which is opposite to the sensitive structure, of the first conductive layer 11 forms a fixed electrode. The first conductive layer 11 further has a portion for grounding, and the portion for grounding of the first conductive layer 11 can be connected to an external electrode for grounding through the portion for electrical connection of the first conductive layer 11.
Step S130: and performing oxide deposition on the first conductive layer, and performing patterned etching on the deposited oxide to obtain the insulating layer. Specifically, as shown in fig. 4, after the first conductive layer 11 is formed, a second layer of silicon oxide is deposited on the first conductive layer 11, and patterned and etched as the insulating layer 12. Referring to fig. 4 and 5, an insulating layer 12 is located between a first conductive layer 11 (i.e., a first polysilicon layer poly 1) formed in the previous step and a second conductive layer 13 (i.e., a second polysilicon layer poly 2) formed in the next step. After patterned etching, at least one notch is formed on the insulating layer 12, and a portion of the second conductive layer 13 is in contact with a portion of the first conductive layer 11 for grounding through the notch to form an electrical connection. The portion where there is no electrical connection between the first conductive layer 11 and the second conductive layer 13 may constitute a parasitic capacitance, and at this time, the thickness of the insulating layer 12 may be increased to increase the capacitance interval, thereby reducing the parasitic capacitance. It will be appreciated that the specific thickness of the insulating layer 12 may be selected according to practical needs, for example, the thickness of the insulating layer 12 may be greater than or equal to 0.3 μm.
Step S140: and carrying out silicon deposition and doping on the insulating layer to form a second polysilicon layer to serve as a second conductive layer. Wherein the second conductive layer is at least partially used for electrical connection. The second conductive layer may be directly connected to an external electrode, or may be connected to the first conductive layer and connected to an external electrode through the first conductive layer. In one embodiment, the second conductive layer is for grounding. The second conductive layer may be a ground electrode directly connected to the outside, or may be connected to the first conductive layer, and connected to an electrode for grounding from the outside through the first conductive layer. In combination with the foregoing, the second conductive layer 13 is partially in contact with the portion of the first conductive layer 11 for grounding through the notch to form an electrical connection, so that the portion of the first conductive layer 11 for grounding and the second conductive layer 13 can form a common potential, which is beneficial to interference resistance. As shown in fig. 5, a second polysilicon layer poly2 is formed by depositing silicon on the insulating layer 12, doping to form N-type polysilicon, or forming P-type polysilicon, to increase conductivity, as the second conductive layer 13.
Step S150: bonding the second wafer to the second conductive layer. Therein, as shown in fig. 6, a second Wafer B is used as a substrate for electrical connection. In one embodiment, the second Wafer B is used for a ground setting, for example, the second Wafer B may be grounded through the package substrate or grounded through the ASIC chip. Specifically, after the second conductive layer 13 is manufactured, the second conductive layer 13 and the second Wafer B are bonded, but the bonding mode is not limited to direct bonding, eutectic fusion bonding, and the like, after bonding, the whole body is turned over, and after turning over, as shown in fig. 6, a polysilicon layer with a thickness being prolonged outside polysilicon is not required, and a sensitive structural layer can be formed through the first Wafer a later. Considering that the first Wafer a is used to form the sensitive structure layer, the second Wafer B is used for the ground arrangement, the requirements for the resistivity of the first Wafer a and the second Wafer B are different, the resistivity of the first Wafer a is less than or equal to 0.01Ω cm, the resistivity of the second Wafer, wafer B, is less than or equal to 10Ω cm, preferably the resistivity of the second Wafer, wafer B, is 1-10Ω cm, as long as the grounding is ensured, the resistivity of the second Wafer B can be relatively high, and a middle-resistance Wafer is selected, so that the Wafer cost can be saved.
In one embodiment, step S150 includes: and grinding the second conductive layer, and bonding the second wafer and the ground second conductive layer. In order to enable the second conductive layer 13 (i.e., the second polysilicon layer poly 2) to be formed to be bonded to the second wafer B of the next step, the second conductive layer 13 is preferably grown to a certain thickness so that the second conductive layer 13 may be polished to have a flat surface and thus may be bonded to the second wafer B. The polishing method is not limited, and chemical mechanical polishing may be specifically used for the second conductive layer 13. Wherein the thickness of the second conductive layer 13 before grinding is greater than or equal to 0.5 μm, so that the notch of the insulating layer 12 in the previous step can be covered and a certain grinding allowance can be used for grinding. Further, the roughness of the second conductive layer 13 after grinding is less than or equal to 4 nm, which is advantageous for bonding.
In one embodiment, step S150 includes: and generating a first medium conducting layer on the second conducting layer, generating a second medium conducting layer on the second wafer, and bonding the second wafer with the second conducting layer through the first medium conducting layer and the second medium conducting layer. The material types of the first medium conductive layer and the second medium conductive layer are not unique, and one of the first medium conductive layer and the second medium conductive layer can be aluminum, and the other one can be germanium. By adding the first intermediate conductive layer and the second intermediate conductive layer between the second Wafer B and the second conductive layer 13, the bonding difficulty can be reduced.
Step S160: and carrying out metal deposition on the second side of the first wafer to obtain a metal layer. Wherein, as shown in fig. 7, the metal layer includes a PAD and a bonding point X. The entire flip may be performed after bonding the second Wafer B with the second conductive layer 13, and then metal deposition is performed on the second side of the first Wafer a. In one embodiment, step S160 includes: and carrying out surface thinning on the second side of the first wafer, and then depositing metal to obtain a metal layer. Specifically, chemical mechanical polishing may be performed on the second side of the first Wafer a, after the surface is thinned, metal deposition is performed to obtain a metal layer, and finally, patterning etching is performed to obtain a PAD and a bonding point X. The metal type adopted by the metal deposition is not the only type, and can be aluminum, aluminum germanium alloy or other metals for deposition, and the obtained metal layer can be an aluminum layer or an aluminum germanium layer correspondingly. The PAD on the metal layer is used for wire bonding to make electrical connection to the external electrode, and the bond point X is used for eutectic bonding or other bonding to make bonding with the sealing cap layer in a subsequent step.
Step S170: etching the second side of the first wafer to generate a sensitive structure, and releasing at least part of the sensitive structure. Specifically, a deep silicon etching technology may be used to etch the second side of the first Wafer a, so as to generate a comb electrode structure as a sensitive structure, and corrode the exposed oxide on the first side of the first Wafer, and release the movable electrode in the comb electrode structure. It will be appreciated that the sensitive structure may also be of other types, for example, also a movable mass. Compared with the method for growing the polycrystalline silicon by adopting the polycrystalline silicon epitaxial process, the method has the advantages that the uniformity of the monocrystalline silicon is relatively good, the resistivity of the monocrystalline silicon can be lower than that of the polycrystalline silicon, which is generally 1/2 or less, and the uniformity is much better by using the monocrystalline silicon as a sensitive structure layer through a deep silicon etching technology.
It will be appreciated that the manner in which the movable electrode in the comb electrode structure is released by etching the exposed oxide of the first side of the first wafer is not exclusive, and in one embodiment, etching the exposed oxide of the first side of the first wafer includes: the exposed oxide on the first side of the first wafer is etched by hydrogen fluoride gas phase etching or buffered oxide etching solution. It is understood that the oxide exposed at the first side of the first wafer refers to an oxide corresponding to the sensitive structure, and is exposed to the outside through the gap of the sensitive structure after the sensitive structure is formed.
After the comb-tooth electrode structure is formed, vapor phase etching with hydrogen fluoride may be used to etch the exposed silicon oxide layer (i.e., the sacrificial layer) on the first side of the first Wafer a, releasing the movable electrode in the comb-tooth electrode structure. When the hydrogen fluoride releasing movable electrode is adopted, the first conductive layer 11 formed by the first polysilicon layer poly1 is used as a stop layer for limiting the etching range of hydrogen fluoride, so that over etching is avoided, and the etchable part of the sacrificial layer is limited by the first conductive layer 11 instead of etching time. As can be seen from fig. 7, the hydrogen fluoride etches only the exposed sacrificial layer on the first side of the first Wafer a, and the first conductive layer 11 can protect the remaining sacrificial layer and the insulating layer 12 from being etched by the hydrogen fluoride. In other embodiments, the movable electrode may be released by etching the sacrificial layer using other means, such as BOE (Buffered Oxide Etch, buffered oxide etchant).
Step S180: bonding the sealing cover layer with bonding points on the second side of the first wafer, and exposing welding spots. After the comb electrode structure is created and the movable electrode is released, the sealing cap layer 14 is bonded to the bonding point X on the second side of the first Wafer a and the PAD is exposed for electrical connection, as shown in fig. 8. After the sealing cap layer 14 is bonded to the first Wafer a, a portion of the sealing cap layer 14 corresponding to the PAD may be removed by a deep silicon etching technique so that the PAD is exposed.
In one embodiment, there is also provided a sensor prepared by the method described above. The sensor includes a first Wafer, a first conductive layer, an insulating layer, a second conductive layer, a second Wafer, a metal layer, and a sealing cap layer, and as shown in fig. 8, the second Wafer B, the second conductive layer 13, the insulating layer 12, the first conductive layer 11, the first Wafer a, the metal layer, and the sealing cap layer 14 are stacked in this order. Further, the sensor further comprises an oxide layer, which may be a silicon oxide layer, disposed between the first Wafer a and the first conductive layer 11. Portions of the silicon oxide may be etched away by performing a silicon oxide deposition on the first Wafer a, and then patterning the silicon oxide deposited on the first side of the first Wafer a. In the subsequent process, the second side of the first Wafer a is etched to generate a sensitive structure, then the silicon oxide exposed on the first side of the first Wafer a is corroded, the movable electrode is released, and the remaining silicon oxide on the first side of the first Wafer a is used as a silicon oxide layer.
According to the sensor manufacturing method and the sensor, after the second Wafer B is bonded with the second conductive layer 13, the metal layer can be manufactured on the first Wafer A after the Wafer is turned over, and the sensitive structure is generated, so that a polysilicon epitaxial process is not needed, the process is simplified, the cost is lower, the stress is smaller, and the manufacturing cost is reduced. In addition, the thickness selectivity of the first Wafer a is high, and the first Wafer a with proper thickness can be selected according to actual requirements, so that a sensitive structure meeting the requirements can be prepared.
Furthermore, the first conductive layer 11, the second conductive layer 13 and the second Wafer B are conductive, the ground portion of the first conductive layer 11, the second conductive layer 13 and the second Wafer B are sequentially contacted to form an electrical connection, and the grounding part of the first conductive layer 11, the second conductive layer 13 and the second Wafer B are grounded respectively, so that the whole structure (except the sensitive structure layer) forms a common potential, which is beneficial to anti-interference.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A method of manufacturing a sensor, comprising:
performing oxide deposition on a first wafer, and performing patterned etching on the oxide deposited on the first side of the first wafer;
Performing silicon deposition and doping on the first side of the first wafer to form a first polysilicon layer to serve as a first conductive layer; the first conductive layer is at least partially used for electrical connection;
performing oxide deposition on the first conductive layer, and performing patterned etching on the deposited oxide to obtain an insulating layer;
performing silicon deposition and doping on the insulating layer to form a second polysilicon layer to serve as a second conductive layer; the second conductive layer is at least partially used for electrical connection;
Bonding a second wafer to the second conductive layer; the second wafer is used for electric connection;
carrying out metal deposition on the second side of the first wafer to obtain a metal layer; the metal layer comprises welding spots and bonding points;
Etching the second side of the first wafer to generate a sensitive structure, and releasing at least part of the sensitive structure;
And bonding the sealing cover layer with the bonding point of the second side of the first wafer, and exposing the welding point.
2. The method of claim 1, wherein bonding the second wafer to the second conductive layer comprises: and grinding the second conductive layer, and bonding the second wafer and the ground second conductive layer.
3. The method of claim 2, wherein the thickness of the second conductive layer prior to polishing is greater than or equal to 0.5 microns.
4. The method of claim 2, wherein the roughness of the ground second conductive layer is less than or equal to 4 nanometers.
5. The method of claim 1, wherein bonding the second wafer to the second conductive layer comprises: and generating a first medium conducting layer on the second conducting layer, generating a second medium conducting layer on the second wafer, and bonding the second wafer with the second conducting layer through the first medium conducting layer and the second medium conducting layer.
6. The method of claim 1, wherein the metal depositing the second side of the first wafer results in a metal layer comprising: and carrying out surface thinning on the second side of the first wafer, and then depositing metal to obtain a metal layer.
7. The method of claim 1, wherein etching the second side of the first wafer to create a sensitive structure and releasing at least a portion of the sensitive structure comprises: etching the second side of the first wafer to generate a comb electrode structure as a sensitive structure, corroding the exposed oxide of the first side of the first wafer, and releasing the movable electrode in the comb electrode structure.
8. The method of any of claims 1-7, wherein the insulating layer has a thickness greater than or equal to 0.3 microns.
9. The method of any of claims 1-7, wherein the second conductive layer is for grounding and the second wafer is for grounding.
10. A sensor comprising a first wafer, a first conductive layer, an insulating layer, a second conductive layer, a second wafer, a metal layer, and a sealing cap layer, the sensor being prepared by the method of any one of claims 1-9.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2023109860695 | 2023-08-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118324092A true CN118324092A (en) | 2024-07-12 |
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