CN118316769A - Verification method for multi-system code shift keying spread spectrum plus MSK transceiver FPGA - Google Patents

Abstract

The invention discloses a verification method of a multi-system code shift keying spread spectrum plus MSK transceiver FPGA, which relates to the technical field of FPGA verification test, and comprises the following steps: s1, designing a transmitter module; s2, double verification; s3, designing a DSP module. The verification method of the multi-system code shift keying spread spectrum plus MSK transceiver FPGA provides a complete set of soft environment verification architecture scheme, does not depend on actual hardware environment and related matched software, provides a powerful solution for repeated experiments in the FPGA design stage, continuously adjusts and modifies the technical scheme, can greatly improve the FPGA development efficiency, solves the verification environment problem that a third party FPGA verifier does not have physical hardware conditions, solves the problem of existence of verification environment, enables the soft environment verification technology to be a possible option, and greatly improves the verification efficiency.

Description

Verification method for multi-system code shift keying spread spectrum plus MSK transceiver FPGA

Technical Field

The invention relates to the technical field of FPGA verification test, in particular to a verification method of a multi-system code shift keying spread spectrum plus MSK transceiver FPGA.

Background

The transceiver FPGA designer usually has 3 testing methods, the first testing method is that the designer only performs unit testing of the design sub-module, and the designer writes some basic excitation codes; the second test method, the designer leads out the observed signal from FPGA pin interface through Debug interface, the third test method, the single-machine level or subsystem level hardware physical environment tests, the test is comparatively comprehensive;

The existing three test methods are incomplete in the first test, depend on the support of conditions such as a hardware environment signal source and the like, only perform local key point test, and depend on a single machine or subsystem hardware environment.

Therefore, in view of the above, research and improvement are performed on the existing structure and the existing defects, and a verification method of the multi-system code shift keying spread spectrum plus MSK transceiver FPGA is provided.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a verification method of a multi-system code shift keying spread spectrum plus MSK transceiver FPGA, which solves the problems in the background art.

In order to achieve the above purpose, the invention is realized by the following technical scheme: a verification method of a multi-system code shift keying spread spectrum plus MSK transceiver FPGA comprises the following steps:

s1, designing a transmitter module:

The transmitter module connected with the transceiver FPGA is realized by adopting a SystemVerilog language and consists of the following submodules: the system comprises an original data framing processing module, a multi-system RS coding processing module, a multi-system spread spectrum processing module, an IQ branching module and an MSK modulation module, wherein an RS decoding data receiving module is used for receiving demodulated and despread RS decoding data at a demodulation data output end of a transceiver FPGA;

S2, double verification:

The receiver module which is connected with the transceiver FPGA is characterized in that the MSK signal of the transmitting end of the transceiver FPGA is only subjected to weighting treatment and is not subjected to orthogonal carrier modulation, and meanwhile, the data after the IQ path data combination after the weighting treatment is output through the DA interface, so that 2 verification technical schemes are adopted, and the method specifically comprises the following steps:

First, the receiver module is implemented using the SystemVerilog language: the IQ weighted data separation module separates IQ two paths of signals, and after orthogonal carrier modulation is carried out by the MSK modulation module in the transmitter module, the signals are received and processed by the FPGA receiving end again, which is equivalent to looping back the signals of the FPGA transmitting end and then taking the receiving end of the transceiver FPGA as a verification receiver;

Secondly, a Matlab language is adopted to realize a receiver module, an IQ weighted data separation module separates IQ two paths of signals, the IQ weighted data separation module carries out orthogonal carrier modulation through an MSK modulation module in a transmitter module, and the IQ weighted data separation module is used as a signal source to be sent into the Matlab for receiving processing, and the IQ weighted data separation module comprises the following submodules: the system comprises an IQ branching interpolation module, a Matlab orthogonal down-conversion module, a Matlab de-weighting processing module, a Matlab low-pass filtering module and a Matlab sampling judgment module, wherein in addition, in order to observe the MSK signal processing process, an MSK signal spectrum analysis module, a Matlab multiplied by a coherent carrier signal spectrum analysis module, a low-pass filtered signal spectrum analysis module and a demodulation result drawing display module are sequentially added;

Meanwhile, the system Verilog language-implemented DSP_MOD module is connected with a control end signal of the transceiver FPGA and provides control instructions and original data required by a transmitting end for verification environment;

s3, designing a DSP module:

The system Verilog language realizes the DSP interface of the DSP_MOD module for continuously receiving and transmitting signals, the DSP transmits mode control instructions to the DUT, meanwhile, the original data of MSK modulation signals output by the transmitting end of the DUT are also transmitted to the DUT through the DSP, and the DSP_MOD designs DSP writing and reading functions by using task functions to complete data interaction with the DUT.

Further, in the step S1, the original data framing processing module: firstly, storing original data into data by defining a plurality of arrays by the SystemVerilog language number, dividing the original data into frame header area data and data area data, and carrying out subsequent RS coding processing on the data after grouping according to 5bit grouping in view of the fact that a direct-spreading mode is multi-system code shift keying spread spectrum;

A multi-system RS coding module: the RS code consists of 2 parts, namely a frame header RS code and a data area RS code, wherein the RS code can be expressed as RS (N, K), when the encoder receives a data information sequence, the data information sequence is divided into a plurality of information blocks with the length of K, each data information block is encoded into an encoded data block with the length of N through operation, the supervision bit of the RS encoder is N-k=2t, the minimum spacing is d=2t+1, and the frame header and the data area adopt different RS codes.

Further, in the step S1, the multi-system spreading module: the frame header RS codes and the data RS codes are respectively subjected to multi-system spread spectrum, the data are processed in a mode that each 5-bit spread spectrum is 32-bit, the spread spectrum codes are according to the 32-bit width, the data to be spread spectrum are stored in the dual-port RAM in advance according to the 5-bit width, therefore, serial-parallel conversion processing is not needed to be carried out on the data in the implementation process, the dual-port RAM is directly operated to read the data, first, each spread spectrum code is circularly shifted left to generate 32 new spread spectrum codes, then 32 spread spectrum code sequences and 0-31 of the 32 data to be spread spectrum establish a one-to-one correspondence, the spread spectrum process is a process of searching the map table, if the input is 0, the first PN sequence is directly output as a spread spectrum output result, if the input is 1, the second PN sequence is directly output as a spread spectrum output result, and the other steps are analogized to realize the data spread spectrum.

Further, in the step S1, the IQ splitting module: the data after spread spectrum is 32bit wide, the I path is in front, the Q path is in back, the IQ path is in branching, the data after branching is changed into 16bit wide, two paths of 16bit components are subjected to double interpolation to form 32bit, the code element width of the branch is ensured to be unchanged, the in-phase component and the quadrature component are obtained, and the delay of one code element period Tc exists between the two branches;

MSK modulation module: the IQ-split in-phase component P _I and quadrature component P _Q data are multiplied by mutually orthogonal weighted carrier functions cos (pi t/2 Ts) and sin (pi t/2 Ts) respectively to finish weighting processing, P _I cos (pi t/2 Ts) and P _Q sin (pi t/2 Ts) are obtained, quadrature carrier signals cos (W _C t) and sin (W _C t) are multiplied respectively to obtain quadrature up-conversion signals P _Icos(πt/2Ts)cos(W_C t) and P _Qsin(πt/2Ts)sin(W_C t), and the two signals after quadrature carrier modulation are subtracted and overlapped to be combined to finish MSK modulation, and finally the signals are input into a transceiver FPGA through an AD interface of a DUT receiving end.

Further, in the step S1, the MSK signal spectrum analysis module: MSK signals generated by a transmitter module or a receiver module are required to be analyzed through the module, whether the frequency interval of +1 and-1 code element data after MSK modulation is 1/2Ts or not is confirmed, whether the modulation index is 0.5 or not is calculated, and a spectrum analysis core implementation code is that a matlab fast Fourier transform FFT function is used for obtaining the spectrum and drawing and displaying the spectrum;

And the RS decoding data receiving module is used for: the data waveforms after demodulation, despreading and RS decoding processing of the DUT, namely the receiving end of the transceiver FPGA, are printed and stored and compared with the original data, if the FPGA is processed correctly, the data comparison of the front and back original frames corresponds to the coincidence, otherwise, the data comparison is inconsistent.

Further, in the step S2, in the first verification technical solution, the receiver module is composed of the following sub-modules: the IQ weighted data separation module, the IQ weighted data interpolation module, the MSK modulation module, the DUT and the MSK spectrum analysis module are used for analyzing a transmitting end signal and an RS decoding data receiving module;

The IQ weighted data separation module is used for: receiving MSK data output by a DA interface of a transmitting end of a DUT (field programmable gate array), namely a transceiver FPGA, wherein the MSK data is only subjected to weighting treatment, and the IQ data after combination is separated to form I, Q paths of data with a bit width of 16 bits;

An IQ weighted data interpolation module: the IQ separated data is 16bit wide, the I path is in front, the Q path is in back, two paths of 16bit components are subjected to double interpolation to form 32 bits, the code element width of the branch is ensured to be unchanged, the in-phase component P_I and the quadrature component P_Q are obtained, and a code element period Tc is delayed between the two branches;

MSK modulation module: the IQ weighted data is interpolated and then sent to an MSK modulation module for carrying out orthogonal carrier up-conversion treatment to finish MSK modulation, wherein the MSK modulation signal is divided into 2 paths for subsequent treatment, 1 path is sent to a DUT (DUT, namely a receiving end of a transceiver FPGA), and the other 1 path is sent to a Matlab receiver;

DUT: and finishing the receiving processing of the signal loop of the transmitting end of MSK modulation, performing MSK demodulation, despreading and RS decoding.

Further, the MSK spectrum analysis module: the received signal is an MSK signal output by the transmitting end of the transceiver FPGA, the purpose is to observe the spectrum result of the complete MSK modulated signal formed after orthogonal carrier modulation, make a preliminary judgment on the signal of the transmitting end, observe whether the frequency interval of +1 and-1 code element data after MSK modulation is 1/2Ts, and calculate whether the modulation index is 0.5;

And the RS decoding data receiving module is used for: the data after demodulation, despreading and decoding processing of the DUT, namely the receiving end of the transceiver FPGA, is printed and stored and compared with the original data, if the FPGA is processed correctly, the data comparison of the front and back original frames corresponds to the coincidence, otherwise, the data comparison is inconsistent.

Further, in the step S2, in the second verification technical scheme, the receiver module is composed of the following sub-modules: the system comprises an IQ branching interpolation module, a Matlab orthogonal down-conversion module, a Matlab de-weighting processing module, a Matlab low-pass filtering module, a Matlab sampling judgment module and a Matlab demodulation result drawing display module;

IQ splitting interpolation module: the IQ separated data is 16bit wide, the I path is in front, the Q path is behind, two paths of 16bit components are subjected to double interpolation to form 32 bits, the code element width of a branch is ensured to be unchanged, an in-phase component P_I and a quadrature component P_Q are obtained, a code element period Tc delay exists between the two branches, a transmitting end MSK modulation signal generated by the IQ separated data is obtained, I, Q paths of signals are split through an interpolation method, the code element width is kept unchanged through the interpolation method, and I, Q paths of data msk_datai and msk_ dataq are obtained;

Matlab quadrature down-conversion module: the module belongs to a first step of coherent demodulation, which uses orthogonal carrier signals to carry out down-conversion processing on input I, Q paths of MSK signals, calculates carrier frequency fc according to MSK signal intermediate frequency IF and sampling frequency Fs, fc=sampling frequency Fs-signal intermediate frequency IF, calculates duration t, t=0:1/Fs according to IQ path signal length Len loaded by matlab, and finally obtains orthogonal carriers cfc =cos (2 pi fc..t) and sfc=sin (2 pi fc..t);

And multiplying the coherent carrier signal module by Matlab: the down-conversion back IQ path signal strips the carrier signal, the waveform of the carrier signal is matched with the weighted waveform, and Matlab is multiplied by a coherent carrier signal spectrum analysis module: after the down-conversion IQ path signal has stripped the carrier signal, the spectrum is the signal spectrum after weighting treatment, the middle is the baseband signal spectrum, and the two sides are the residual carrier spectrum;

The operation procedure of multiplying the coherent carrier wave is as follows: de_i=msk_datai.. cfc, de_q=msk_ dataq..sfc.

Further, in the step S2, the Matlab de-weighting processing module: the module belongs to a third step of coherent demodulation, which uses orthogonal weighting function signals to carry out de-weighting processing on I, Q paths of MSK signals after down-conversion, shifts the frequency spectrum to near zero frequency, designs the frequency f _c1 of the orthogonal weighting function, and obtains the symbol width after spread as T _b, which is known by an angular frequency formula = 2 x pi x fc, and then according to the MSK modulation principle, W _c1=π/2T_b= 2*π* f_c1,=1/4T_b, thus the frequency of the weighting function is known to be 1/4 of the current symbol frequency, and finally orthogonal weighting carriers cfc1 = cos (2 x pi x _c1 x T) and sfc1 = sin (2 x pi x _c1 x T);

the whole operation process of coherent demodulation is as follows: demodi=msk_datai.. cfc.. cfc, demodq=msk_ dataq sfc..sfc 1;

Matlab low pass filter module: according to the current sampling frequency Fs and the signal bandwidth Ps, designing a cut-off frequency of a low-pass filter, namely b=fir1 (30, ps/Fs), wherein the low-pass filter can filter residual high-frequency components in the IQ path baseband signal after coherent demodulation, and the low-pass filtered signal module is as follows: the module is used for displaying the result of low-pass filtering of a signal after being multiplied by coherent carrier, according to the current filter b, the frequency response of a low-pass filter fir is obtained through [ h, w ] = freqz (b, 1,512), three parameters of a freqz function are respectively coefficients of a molecular polynomial of a filter system function, the coefficients of a denominator polynomial of the fir filter are respectively 1 and the number of sampling points is default to 512, and then a matlab function fftfilt (), I, Q paths of filtered signal waveforms lvbo _i= fftfilt (b, de_i) and lvbo _q= fftfilt (b, de_q) are respectively obtained, the filtered waveforms are further provided with weighting function waveforms, and the low-pass filtered signal spectrum analysis module: according to the current IQ-path filtered signal waveforms, lvbo _i= fftfilt (b, de_i) and lvbo _q= fftfilt (b, de_q), and performing fast fourier transform to obtain a filtered signal spectrum, so as to obtain dmfi= fftshift (abs (fft (lvbo _i))) and dmfq = fftshift (abs (fft (lvbo _q)), where the low-pass filtered signal spectrum has filtered out residual carrier frequencies, and only baseband signal frequencies remain.

Further, in the step S2, the Matlab sampling decision module:

Sampling and judging f_i and f_q after coherent demodulation, wherein when f_i signal vector value is greater than 0, the judgment result is set to +1, otherwise, the judgment result is set to +1, and when f_q signal vector value is greater than 0, the judgment result is set to +1;

a demodulation result drawing display module: and displaying the signal waveforms before and after the sampling decision, and comparing the sampling decision result with the SystemVerilog receiver result in order to verify the correctness of matlab processing.

The invention provides a verification method of a multi-system code shift keying spread spectrum plus MSK transceiver FPGA, which has the following beneficial effects:

The verification method of the multi-system code shift keying spread spectrum plus MSK transceiver FPGA provides a complete set of soft environment verification architecture scheme, does not depend on an actual hardware environment and related matched software, provides a powerful solution for repeated experiments in the FPGA design stage and continuously adjusts and modifies the technical scheme, can greatly improve the FPGA development efficiency, and provides a verification soft environment architecture scheme based on SystemVerilog and Matlab language under the condition that a third party FPGA verifier does not have a physical hardware environment at all, so that the verification environment problem that the third party FPGA verifier does not have the physical hardware condition is solved, the problem of the verification environment is solved, the soft environment verification technology becomes a possible option, and the verification efficiency is greatly improved.

Drawings

FIG. 1 is a general diagram of a multi-system code shift keying spread spectrum plus MSK modem transceiver FPGA verification process based on SystemVerilog and Matlab;

FIG. 2 is a diagram of the MSK modulation process based on SystemVerilog of the present invention;

FIG. 3 is a diagram of a Matlab-based MSK signal spectrum analysis of the present invention;

fig. 4 is a signal diagram of the Matlab-based MSK signal multiplied by a coherent carrier wave according to the present invention;

FIG. 5 is a graph of the signal spectrum of the Matlab-based MSK signal multiplied by the coherent carrier;

FIG. 6 is a low pass filtered signal plot based on Matlab in accordance with the present invention;

FIG. 7 is a graph of a low pass filtered signal spectrum based on Matlab in accordance with the present invention;

FIG. 8 is a diagram of the result of Matlab-based MSK coherent demodulation in the present invention;

FIG. 9 is a signal diagram of the DUT receiver MSK signal after demodulation;

FIG. 10 is a simulation waveform of the frame header RS decoding at the receiving end of the DUT of the present invention;

FIG. 11 is a simulation waveform of the RS decoding of the data at the receiving end of the DUT according to the present invention.

Detailed Description

Embodiments of the present invention are described in further detail below with reference to the accompanying drawings and examples. The following examples are illustrative of the invention but are not intended to limit the scope of the invention.

As shown in fig. 1 to 11, the present invention provides the following technical solutions: the verification method of the multi-system code shift keying spread spectrum plus MSK transceiver FPGA comprises the following steps:

s1, designing a transmitter module:

The transmitter module connected with the transceiver FPGA is realized by adopting a SystemVerilog language and consists of the following submodules: the system comprises an original data framing processing module, a multi-system RS coding processing module, a multi-system spread spectrum processing module, an IQ branching module and an MSK modulation module, wherein an RS decoding data receiving module is used for receiving demodulated and despread RS decoding data at a demodulation data output end of a transceiver FPGA;

S2, double verification:

The receiver module which is connected with the transceiver FPGA is characterized in that the transmitting end MSK signal of the transceiver FPGA only carries out weighting treatment (see figure 2 in detail) and does not carry out orthogonal carrier modulation, and meanwhile, the data after the weighting treatment after the IQ path data combination is output through the DA interface, so that 2 verification technical schemes are adopted, and the method comprises the following steps:

First, the receiver module is implemented using the SystemVerilog language: the IQ weighted data separation module separates IQ two paths of signals, and after orthogonal carrier modulation is carried out by the MSK modulation module in the transmitter module, the signals are received and processed by the FPGA receiving end again, which is equivalent to looping back the signals of the FPGA transmitting end and then taking the receiving end of the transceiver FPGA as a verification receiver;

Secondly, a Matlab language is adopted to realize a receiver module, an IQ weighted data separation module separates IQ two paths of signals, the IQ weighted data separation module carries out orthogonal carrier modulation through an MSK modulation module in a transmitter module, and the IQ weighted data separation module is used as a signal source to be sent into the Matlab for receiving processing, and the IQ weighted data separation module comprises the following submodules: the system comprises an IQ branching interpolation module, a Matlab orthogonal down-conversion module, a Matlab de-weighting processing module, a Matlab low-pass filtering module and a Matlab sampling judgment module, wherein in addition, in order to observe the MSK signal processing process, an MSK signal spectrum analysis module, a Matlab multiplied by a coherent carrier signal spectrum analysis module, a low-pass filtered signal spectrum analysis module and a demodulation result drawing display module are sequentially added;

Meanwhile, the system Verilog language-implemented DSP_MOD module is connected with a control end signal of the transceiver FPGA and provides control instructions and original data required by a transmitting end for verification environment;

s3, designing a DSP module:

The system Verilog language realizes the DSP interface of the DSP_MOD module for continuously receiving and transmitting signals, the DSP transmits mode control instructions to the DUT, meanwhile, the original data of MSK modulation signals output by the transmitting end of the DUT are also transmitted to the DUT through the DSP, and the DSP_MOD designs DSP writing and reading functions by using task functions to complete data interaction with the DUT.

The direct spread spectrum sequence is added with MSK modulation, the direct spread spectrum is selected by a multi-system code shift keying spread spectrum mode, and compared with the common serial direct spread spectrum sequence, the multi-system spread spectrum transmits n information bits for each spread spectrum code, so that the transmission efficiency is improved, the spread spectrum processing gain is improved, and the lower signal bandwidth is kept. MSK modulation has the characteristics of constant envelope, concentrated energy, strong interference resistance, high spectrum utilization rate and insensitivity to nonlinear distortion, so that the MSK modulation is most suitable for being adopted in a high dynamic environment;

The multi-system code shift keying implementation principle: the serial-parallel converter divides the input data into code groups with the length of n bits to form M= ⁿ system information, then each code group corresponds to a unique code sequence in M code sequence matrixes with the length of L, and finally the code groups select sequences and then send the sequences to the modulator for modulation;

The representation of a binary Minimum Shift Keying (MSK) signal can be written as:

SMSK(t)=cos(W_ct+ +Φk) (equation 1)

Where kT _b≤t≤（k+1）T_b, T is time, W _c is carrier angular frequency, T _b is symbol width, b _k is data in the kth symbol (takes a value of ±1), Φ _k is phase constant in the kth symbol, Φ _k =0 or pi (modulo 2pi), which remains unchanged in time kT _b≤t≤（k+1）T_b, it is known from the formula that when b _k =1, frequency ƒ 2= (W _c +) ; When b _k = -1, the frequency of the signal ƒ 1 =（W_c -），

This gives a frequency spacing Δ ƒ = ƒ 2- ƒ 1 =Modulation index h=Δ ƒ T _b =0.5.

The equation 1 is expanded as follows:

SMSK(t)=cos(+Φ_k) cosW_ct-sin( +Φ _k)sinW_c t (equation 2)

So the MSK signal can be seen as two orthogonal carriers cosW _c t and sinW _c t respectively divided by the function cos+Phi _k) and sin%+Φ _k), Φ _k =0 or 2pi (modulo 2pi), the MSK modulation principle is shown in fig. 2.

In step S1, the original data framing processing module: firstly, storing original data into data by defining a plurality of arrays by the SystemVerilog language number, dividing the original data into frame header area data and data area data, and carrying out subsequent RS coding processing on the data after grouping according to 5bit grouping in view of the fact that a direct-spreading mode is multi-system code shift keying spread spectrum;

A multi-system RS coding module: the RS code consists of 2 parts, namely a frame header RS code and a data area RS code, wherein the RS code can be expressed as RS (N, K), when the encoder receives a data information sequence, the data information sequence is divided into a plurality of information blocks with the length of K, each data information block is encoded into an encoded data block with the length of N through operation, the supervision bit of the RS encoder is N-k=2t, the minimum spacing is d=2t+1, and the frame header and the data area adopt different RS codes, for example, the frame header RS code realizes that each K pieces of 5bit data are encoded into N pieces of 5bit data.

In step S1, the multi-system spread spectrum module: the frame header RS codes and the data RS codes are respectively subjected to multi-system spread spectrum, the data are processed in a mode that each 5-bit spread spectrum is 32-bit, the spread spectrum codes are according to the 32-bit width, the data to be spread spectrum are stored in the dual-port RAM in advance according to the 5-bit width, therefore, serial-parallel conversion processing is not needed to be carried out on the data in the implementation process, the dual-port RAM is directly operated to read the data, first, each spread spectrum code is circularly shifted left to generate 32 new spread spectrum codes, then 32 spread spectrum code sequences and 0-31 of the 32 data to be spread spectrum establish a one-to-one correspondence, the spread spectrum process is a process of searching the map table, if the input is 0, the first PN sequence is directly output as a spread spectrum output result, if the input is 1, the second PN sequence is directly output as a spread spectrum output result, and the other steps are analogized to realize the data spread spectrum.

In step S1, the IQ splitting module: the data after spread spectrum is 32bit wide, the I path is in front, the Q path is in back, the IQ path is in branching, the data after branching is changed into 16bit wide, two paths of 16bit components are subjected to double interpolation to form 32bit, the code element width of the branch is ensured to be unchanged, the in-phase component and the quadrature component are obtained, and the delay of one code element period Tc exists between the two branches;

MSK modulation module: the IQ-split in-phase component P _I and quadrature component P _Q data are multiplied by mutually orthogonal weighted carrier functions cos (pi t/2 Ts) and sin (pi t/2 Ts) respectively to finish weighting processing, P _I cos (pi t/2 Ts) and P _Q sin (pi t/2 Ts) are obtained, quadrature carrier signals cos (W _c t) and sin (W _c t) are multiplied respectively to obtain quadrature up-conversion signals P _Icos(πt/2Ts)cos(W_c t) and P _Qsin(πt/2Ts)sin(W_c t), the two signals after quadrature carrier modulation are subtracted and overlapped to be combined to finish MSK modulation, and finally the MSK modulation process is detailed in the accompanying figure 2 through an AD interface input transceiver FPGA of a DUT receiving end.

In step S1, the MSK signal spectrum analysis module: the MSK signals generated by the transmitter module or the receiver module are all required to analyze the frequency spectrums thereof by the module, confirm whether the frequency interval of the MSK modulated +1 and-1 code element data is 1/2Ts, calculate whether the modulation index is 0.5, and obtain the frequency spectrums thereof by using matlab FFT function and display the frequency spectrums in a drawing way, and see the figure 3 in detail;

And the RS decoding data receiving module is used for: the data waveforms after demodulation, despreading and RS decoding processing of the DUT, namely the receiving end of the transceiver FPGA, are printed and stored and compared with the original data, if the FPGA is processed correctly, the data comparison of the front and back original frames corresponds to the coincidence, otherwise, the data comparison is inconsistent, and the details are shown in fig. 10 and 11.

In step S2, in the first verification technical solution, the receiver module is composed of the following sub-modules: the IQ weighted data separation module, the IQ weighted data interpolation module, the MSK modulation module, the DUT and the MSK spectrum analysis module are used for analyzing a transmitting end signal and an RS decoding data receiving module;

The IQ weighted data separation module is used for: receiving MSK data output by a DA interface of a transmitting end of a DUT (field programmable gate array), namely a transceiver FPGA, wherein the MSK data is only subjected to weighting treatment, and the IQ data after combination is separated to form I, Q paths of data with a bit width of 16 bits;

An IQ weighted data interpolation module: the IQ separated data is 16bit wide, the I path is in front, the Q path is in back, two paths of 16bit components are subjected to double interpolation to form 32 bits, the code element width of the branch is ensured to be unchanged, the in-phase component P_I and the quadrature component P_Q are obtained, and a code element period Tc is delayed between the two branches;

MSK modulation module: the IQ weighted data is interpolated and then sent to an MSK modulation module for carrying out orthogonal carrier up-conversion treatment to finish MSK modulation, wherein the MSK modulation signal is divided into 2 paths for subsequent treatment, 1 path is sent to a DUT (DUT, namely a receiving end of a transceiver FPGA), and the other 1 path is sent to a Matlab receiver;

DUT: and finishing the receiving processing of the signal loop of the transmitting end of MSK modulation, performing MSK demodulation, despreading and RS decoding.

MSK spectrum analysis module: the received signal is an MSK signal output by the transmitting end of the transceiver FPGA, the purpose is to observe the spectrum result of the complete MSK modulated signal formed after orthogonal carrier modulation, make a preliminary judgment on the signal of the transmitting end, observe whether the frequency interval of +1 and-1 code element data after MSK modulation is 1/2Ts, and calculate whether the modulation index is 0.5;

And the RS decoding data receiving module is used for: the data after demodulation, despreading and decoding processing of the DUT, namely the receiving end of the transceiver FPGA, is printed and stored and compared with the original data, if the FPGA is processed correctly, the data comparison of the front and back original frames corresponds to the coincidence, otherwise, the data comparison is inconsistent, and the details are shown in figures 10 and 11.

In step S2, in the second verification technical solution, the receiver module is composed of the following sub-modules: the system comprises an IQ branching interpolation module, a Matlab orthogonal down-conversion module, a Matlab de-weighting processing module, a Matlab low-pass filtering module, a Matlab sampling judgment module and a Matlab demodulation result drawing display module;

IQ splitting interpolation module: the IQ separated data is 16bit wide, the I path is in front, the Q path is behind, two paths of 16bit components are subjected to double interpolation to form 32 bits, the code element width of a branch is ensured to be unchanged, an in-phase component P_I and a quadrature component P_Q are obtained, a code element period Tc delay exists between the two branches, a transmitting end MSK modulation signal generated by the IQ separated data is obtained, I, Q paths of signals are split through an interpolation method, the code element width is kept unchanged through the interpolation method, and I, Q paths of data msk_datai and msk_ dataq are obtained;

Matlab quadrature down-conversion module: the module belongs to a first step of coherent demodulation, which uses orthogonal carrier signals to carry out down-conversion processing on input I, Q paths of MSK signals, calculates carrier frequency fc according to MSK signal intermediate frequency IF and sampling frequency Fs, fc=sampling frequency Fs-signal intermediate frequency IF, calculates duration t, t=0:1/Fs according to IQ path signal length Len loaded by matlab, and finally obtains orthogonal carriers cfc =cos (2 pi fc..t) and sfc=sin (2 pi fc..t);

And multiplying the coherent carrier signal module by Matlab: the waveform of the down-converted IQ-path signal stripped carrier signal is identical with the waveform after weighting treatment, see fig. 4 for details, matlab multiplied by a coherent carrier signal spectrum analysis module: after the down-conversion IQ path signal has stripped the carrier signal, the spectrum is the weighted signal spectrum, the middle is the baseband signal spectrum, and the two sides are the residual carrier spectrum, see figure 5;

The operation procedure of multiplying the coherent carrier wave is as follows: de_i=msk_datai.. cfc, de_q=msk_ dataq..sfc.

In step S2, the Matlab de-weighting processing module: the module belongs to a third step of coherent demodulation, which uses orthogonal weighting function signals to carry out de-weighting processing on I, Q paths of MSK signals after down-conversion, shifts the frequency spectrum to near zero frequency, designs the frequency f _c1 of the orthogonal weighting function, and obtains the symbol width after spread as T _b, which is known by an angular frequency formula = 2 x pi x fc, and then according to the MSK modulation principle, W _c1=π/2T_b= 2*π*f_c1,=1/4T_b, thus the frequency of the weighting function is known to be 1/4 of the current symbol frequency, and finally orthogonal weighting carriers cfc1 = cos (2 x pi x _c1 x T) and sfc1 = sin (2 x pi x _c1 x T);

the whole operation process of coherent demodulation is as follows: demodi=msk_datai.. cfc.. cfc, demodq=msk_ dataq sfc..sfc 1;

Matlab low pass filter module: according to the current sampling frequency Fs and the signal bandwidth Ps, designing a cut-off frequency of a low-pass filter, namely b=fir1 (30, ps/Fs), wherein the low-pass filter can filter residual high-frequency components in the IQ path baseband signal after coherent demodulation, and the low-pass filtered signal module is as follows: the module is to obtain the frequency response of the low-pass filter fir through [ h, w ] = freqz (b, 1,512) according to the current filter b, wherein three parameters of the freqz function are coefficients of a numerator polynomial of the filter system function, the denominator coefficient of the fir filter is 1 and the sampling point is default to 512, and then the matlab function fftfilt (), so as to obtain I, Q filtered signal waveforms lvbo _i= fftfilt (b, de_i) and lvbo _q= fftfilt (b, de_q), the filtered waveforms are further provided with weighting function waveforms, as shown in fig. 6, and the low-pass filtered signal spectrum analysis module: according to the current IQ-filtered signal waveforms, lvbo _i= fftfilt (b, de_i) and lvbo _q= fftfilt (b, de_q), and performing fast fourier transform to obtain the filtered signal spectrum, to obtain dmfi= fftshift (abs (fft (lvbo _i))) and dmfq = fftshift (abs (fft (lvbo _q)), where the low-pass filtered signal spectrum is compared with fig. 5, it is known that the residual carrier frequency is filtered, and only the baseband signal frequency remains, as shown in fig. 7.

In step S2, matlab sampling decision module:

Sampling and judging f_i and f_q after coherent demodulation, wherein when f_i signal vector value is greater than 0, the judgment result is set to +1, otherwise, the judgment result is set to +1, and when f_q signal vector value is greater than 0, the judgment result is set to +1;

A demodulation result drawing display module: the signal waveform before sampling decision is shown in figure 8, the result waveform after sampling decision is shown in figure 8, the signal waveform before and after sampling decision can be displayed more intuitively, and meanwhile, in order to verify the correctness of matlab processing, the result after sampling decision is compared with the result of a SystemVerilog receiver, the result after MSK demodulation is consistent with the result after matlab sampling decision, and the detail is shown in figures 8 and 9.

Aiming at a transceiver FPGA realized based on the FPGA, an FPGA developer needs to verify whether a receiving end can correctly demodulate, despread and RS decode a direct-spread MSK signal or not in time, and verify whether the direct-spread MSK signal generated by a transmitting end can be correctly demodulated, despread and RS decoded by a receiver of the opposite side after being transmitted.

Aiming at the condition that a third party FPGA verifier does not have a physical hardware environment at all, the invention provides a verification soft environment architecture scheme based on SystemVerilog and Matlab languages, which solves the verification environment problem that the third party FPGA verifier does not have a physical hardware condition, solves the problem of existence of the verification environment, enables a soft environment verification technology to be a possible option, and greatly improves the verification efficiency.

The transceiver software architecture has the following characteristics of the FPGA verification model of the subclass transceiver, and is specifically as follows:

the intermediate frequency of the transmitter model can be modified, the intermediate frequency can be adjusted at any time according to the intermediate frequency received by different transceiver FPGAs, and the intermediate frequency has strong adaptability;

the multi-system spread spectrum sequence is provided from the outside and stored in the ROM file, the ROM file can be encrypted, the architecture can be read only according to the address, and the user can update the spread spectrum sequence at any time according to the requirement, thereby being beneficial to the confidentiality of user data;

the multi-system RS code can be updated at any time according to the algorithm, and if encryption is needed, the user can encrypt the algorithm module and then embed the algorithm module into the verification framework in a netlist form;

the original data frame structure has universality, and the frame header plus data area is a basic structure of the original data frame structure and can be adjusted at any time according to an actual data protocol so as to adapt to different frame structures;

In summary, the architecture can adapt to the changes in the main design parameters and algorithms of the present subclass transceiver FPGA.

The embodiments of the invention have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims (10)

1. A verification method of a multi-system code shift keying spread spectrum plus MSK transceiver FPGA is characterized in that: the verification method of the multi-system code shift keying spread spectrum plus MSK transceiver FPGA comprises the following steps:

s1, designing a transmitter module:

The transmitter module connected with the transceiver FPGA is realized by adopting a SystemVerilog language and consists of the following submodules: the system comprises an original data framing processing module, a multi-system RS coding processing module, a multi-system spread spectrum processing module, an IQ branching module and an MSK modulation module, wherein an RS decoding data receiving module is used for receiving demodulated and despread RS decoding data at a demodulation data output end of a transceiver FPGA;

S2, double verification:

The receiver module which is connected with the transceiver FPGA is characterized in that the MSK signal of the transmitting end of the transceiver FPGA is only subjected to weighting treatment and is not subjected to orthogonal carrier modulation, and meanwhile, the data after the IQ path data combination after the weighting treatment is output through the DA interface, so that 2 verification technical schemes are adopted, and the method specifically comprises the following steps:

First, the receiver module is implemented using the SystemVerilog language: the IQ weighted data separation module separates IQ two paths of signals, and after orthogonal carrier modulation is carried out by the MSK modulation module in the transmitter module, the signals are received and processed by the FPGA receiving end again, which is equivalent to looping back the signals of the FPGA transmitting end and then taking the receiving end of the transceiver FPGA as a verification receiver;

Secondly, a Matlab language is adopted to realize a receiver module, an IQ weighted data separation module separates IQ two paths of signals, the IQ weighted data separation module carries out orthogonal carrier modulation through an MSK modulation module in a transmitter module, and the IQ weighted data separation module is used as a signal source to be sent into the Matlab for receiving processing, and the IQ weighted data separation module comprises the following submodules: the system comprises an IQ branching interpolation module, a Matlab orthogonal down-conversion module, a Matlab de-weighting processing module, a Matlab low-pass filtering module and a Matlab sampling judgment module, wherein in addition, in order to observe the MSK signal processing process, an MSK signal spectrum analysis module, a Matlab multiplied by a coherent carrier signal spectrum analysis module, a low-pass filtered signal spectrum analysis module and a demodulation result drawing display module are sequentially added;

Meanwhile, the system Verilog language-implemented DSP_MOD module is connected with a control end signal of the transceiver FPGA and provides control instructions and original data required by a transmitting end for verification environment;

s3, designing a DSP module:

The system Verilog language realizes the DSP interface of the DSP_MOD module for continuously receiving and transmitting signals, the DSP transmits mode control instructions to the DUT, meanwhile, the original data of MSK modulation signals output by the transmitting end of the DUT are also transmitted to the DUT through the DSP, and the DSP_MOD designs DSP writing and reading functions by using task functions to complete data interaction with the DUT.

2. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S1, the original data framing processing module: firstly, storing original data into data by defining a plurality of arrays by the SystemVerilog language number, dividing the original data into frame header area data and data area data, and carrying out subsequent RS coding processing on the data after grouping according to 5bit grouping in view of the fact that a direct-spreading mode is multi-system code shift keying spread spectrum;

A multi-system RS coding module: the RS code consists of 2 parts, namely a frame header RS code and a data area RS code, wherein the RS code can be expressed as RS (N, K), when the encoder receives a data information sequence, the data information sequence is divided into a plurality of information blocks with the length of K, each data information block is encoded into an encoded data block with the length of N through operation, the supervision bit of the RS encoder is N-k=2t, the minimum spacing is d=2t+1, and the frame header and the data area adopt different RS codes.

3. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S1, the multi-system spreading module: the frame header RS codes and the data RS codes are respectively subjected to multi-system spread spectrum, the data are processed in a mode that each 5-bit spread spectrum is 32-bit, the spread spectrum codes are according to the 32-bit width, the data to be spread spectrum are stored in the dual-port RAM in advance according to the 5-bit width, therefore, serial-parallel conversion processing is not needed to be carried out on the data in the implementation process, the dual-port RAM is directly operated to read the data, first, each spread spectrum code is circularly shifted left to generate 32 new spread spectrum codes, then 32 spread spectrum code sequences and 0-31 of the 32 data to be spread spectrum establish a one-to-one correspondence, the spread spectrum process is a process of searching the map table, if the input is 0, the first PN sequence is directly output as a spread spectrum output result, if the input is 1, the second PN sequence is directly output as a spread spectrum output result, and the other steps are analogized to realize the data spread spectrum.

4. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S1, the IQ splitting module: the data after spread spectrum is 32bit wide, the I path is in front, the Q path is in back, the IQ path is in branching, the data after branching is changed into 16bit wide, two paths of 16bit components are subjected to double interpolation to form 32bit, the code element width of the branch is ensured to be unchanged, the in-phase component and the quadrature component are obtained, and the delay of one code element period Tc exists between the two branches;

MSK modulation module: the IQ-split in-phase component P _I and quadrature component P _Q data are multiplied by mutually orthogonal weighted carrier functions cos (pi t/2 Ts) and sin (pi t/2 Ts) respectively to finish weighting processing, P _I cos (pi t/2 Ts) and P _Q sin (pi t/2 Ts) are obtained, quadrature carrier signals cos (w _c t) and sin (w _c t) are multiplied respectively to obtain quadrature up-conversion signals P _Icos(πt/2Ts)cos(w_c t) and P _Qsin(πt/2Ts)sin(w_c t), and the two signals after quadrature carrier modulation are subtracted and overlapped to be combined to finish MSK modulation, and finally the signals are input into a transceiver FPGA through an AD interface of a DUT receiving end;

where T is time, w _c is carrier angular frequency, and Ts is symbol width.

5. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S1, the MSK signal spectrum analysis module: MSK signals generated by a transmitter module or a receiver module are required to be analyzed through the module, whether the frequency interval of +1 and-1 code element data after MSK modulation is 1/2Ts or not is confirmed, whether the modulation index is 0.5 or not is calculated, and a spectrum analysis core implementation code is that a matlab fast Fourier transform FFT function is used for obtaining the spectrum and drawing and displaying the spectrum;

And the RS decoding data receiving module is used for: the data waveforms after demodulation, despreading and RS decoding processing of the DUT, namely the receiving end of the transceiver FPGA, are printed and stored and compared with the original data, if the FPGA is processed correctly, the data comparison of the front and back original frames corresponds to the coincidence, otherwise, the data comparison is inconsistent.

6. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S2, in the first verification technical scheme, the receiver module is composed of the following sub-modules: the IQ weighted data separation module, the IQ weighted data interpolation module, the MSK modulation module, the DUT and the MSK spectrum analysis module are used for analyzing a transmitting end signal and an RS decoding data receiving module;

The IQ weighted data separation module is used for: receiving MSK data output by a DA interface of a transmitting end of a DUT (field programmable gate array), namely a transceiver FPGA, wherein the MSK data is only subjected to weighting treatment, and the IQ data after combination is separated to form I, Q paths of data with a bit width of 16 bits;

An IQ weighted data interpolation module: the IQ separated data is 16bit wide, the I path is in front, the Q path is in back, two paths of 16bit components are subjected to double interpolation to form 32 bits, the code element width of the branch is ensured to be unchanged, the in-phase component P_I and the quadrature component P_Q are obtained, and a code element period Tc is delayed between the two branches;

MSK modulation module: the IQ weighted data is interpolated and then sent to an MSK modulation module for carrying out orthogonal carrier up-conversion treatment to finish MSK modulation, wherein the MSK modulation signal is divided into 2 paths for subsequent treatment, 1 path is sent to a DUT (DUT, namely a receiving end of a transceiver FPGA), and the other 1 path is sent to a Matlab receiver;

DUT: and finishing the receiving processing of the signal loop of the transmitting end of MSK modulation, performing MSK demodulation, despreading and RS decoding.

7. The method for verifying the FPGA of the spread spectrum plus MSK multi-ary code shift keying transceiver of claim 6, wherein: the MSK spectrum analysis module: the received signal is an MSK signal output by the transmitting end of the transceiver FPGA, the purpose is to observe the spectrum result of the complete MSK modulated signal formed after orthogonal carrier modulation, make a preliminary judgment on the signal of the transmitting end, observe whether the frequency interval of +1 and-1 code element data after MSK modulation is 1/2Ts, and calculate whether the modulation index is 0.5;

And the RS decoding data receiving module is used for: the data after demodulation, despreading and decoding processing of the DUT, namely the receiving end of the transceiver FPGA, is printed and stored and compared with the original data, if the FPGA is processed correctly, the data comparison of the front and back original frames corresponds to the coincidence, otherwise, the data comparison is inconsistent.

8. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S2, in the second verification technical solution, the receiver module is composed of the following sub-modules: the system comprises an IQ branching interpolation module, a Matlab orthogonal down-conversion module, a Matlab de-weighting processing module, a Matlab low-pass filtering module, a Matlab sampling judgment module and a Matlab demodulation result drawing display module;

IQ splitting interpolation module: the IQ separated data is 16bit wide, the I path is in front, the Q path is behind, two paths of 16bit components are subjected to double interpolation to form 32 bits, the code element width of a branch is ensured to be unchanged, an in-phase component P_I and a quadrature component P_Q are obtained, a code element period Tc delay exists between the two branches, a transmitting end MSK modulation signal generated by the IQ separated data is obtained, I, Q paths of signals are split through an interpolation method, the code element width is kept unchanged through the interpolation method, and I, Q paths of data msk_datai and msk_ dataq are obtained;

Matlab quadrature down-conversion module: the module belongs to a first step of coherent demodulation, which uses orthogonal carrier signals to carry out down-conversion processing on input I, Q paths of MSK signals, calculates carrier frequency fc according to MSK signal intermediate frequency IF and sampling frequency Fs, fc=sampling frequency Fs-signal intermediate frequency IF, calculates duration t, t=0:1/Fs according to IQ path signal length Len loaded by matlab, and finally obtains orthogonal carriers cfc =cos (2 pi fc..t) and sfc=sin (2 pi fc..t);

And multiplying the coherent carrier signal module by Matlab: the down-conversion back IQ path signal strips the carrier signal, the waveform of the carrier signal is matched with the weighted waveform, and Matlab is multiplied by a coherent carrier signal spectrum analysis module: after the down-conversion IQ path signal has stripped the carrier signal, the spectrum is the signal spectrum after weighting treatment, the middle is the baseband signal spectrum, and the two sides are the residual carrier spectrum;

The operation procedure of multiplying the coherent carrier wave is as follows: de_i=msk_datai.. cfc, de_q=msk_ dataq..sfc.

9. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S2, the Matlab de-weighting processing module: the module belongs to a third step of coherent demodulation, which uses an orthogonal weighting function signal to carry out de-weighting processing on I, Q paths of MSK signals after down-conversion, shifts the frequency spectrum to near zero frequency, and designs the frequency f _c1 of the orthogonal weighting function, wherein the width of a code element after the frequency spreading is T _b, which is known by an angular frequency formula=2×pi×fc, and then is known by an MSK modulation principle, w _c1=π/2T_b= 2*π* f_c1,=1/4T_b, so that the frequency of the weighting function is 1/4 of the current code element frequency, and finally orthogonal weighting carriers cfc < 1 > = cos (2×pi× _c1..t) and sfc1=sin (2×pi× _c1.);

the whole operation process of coherent demodulation is as follows: demodi=msk_datai.. cfc.. cfc, demodq=msk_ dataq sfc..sfc 1;

Matlab low pass filter module: according to the current sampling frequency Fs and the signal bandwidth Ps, designing a cut-off frequency of a low-pass filter, namely b=fir1 (30, ps/Fs), wherein the low-pass filter can filter residual high-frequency components in the IQ path baseband signal after coherent demodulation, and the low-pass filtered signal module is as follows: the module is used for displaying the result of low-pass filtering of a signal after being multiplied by coherent carrier, according to the current filter b, the frequency response of a low-pass filter fir is obtained through [ h, w ] = freqz (b, 1,512), three parameters of a freqz function are respectively coefficients of a molecular polynomial of a filter system function, the coefficients of a denominator polynomial of the fir filter are respectively 1 and the number of sampling points is default to 512, and then a matlab function fftfilt (), I, Q paths of filtered signal waveforms lvbo _i= fftfilt (b, de_i) and lvbo _q= fftfilt (b, de_q) are respectively obtained, the filtered waveforms are further provided with weighting function waveforms, and the low-pass filtered signal spectrum analysis module: according to the current IQ-path filtered signal waveforms, lvbo _i= fftfilt (b, de_i) and lvbo _q= fftfilt (b, de_q), and performing fast fourier transform to obtain a filtered signal spectrum, so as to obtain dmfi= fftshift (abs (fft (lvbo _i))) and dmfq = fftshift (abs (fft (lvbo _q)), where the low-pass filtered signal spectrum has filtered out residual carrier frequencies, and only baseband signal frequencies remain.

10. The method for verifying the multi-system code shift keying spread spectrum plus MSK transceiver FPGA of claim 1, wherein: in the step S2, the Matlab sampling judgment module:

Sampling and judging f_i and f_q after coherent demodulation, wherein when f_i signal vector value is greater than 0, the judgment result is set to +1, otherwise, the judgment result is set to +1, and when f_q signal vector value is greater than 0, the judgment result is set to +1;

a demodulation result drawing display module: and displaying the signal waveforms before and after the sampling decision, and comparing the sampling decision result with the SystemVerilog receiver result in order to verify the correctness of matlab processing.