CN118316403A

CN118316403A - Operational amplifier circuit, operational amplifier, chip and electronic device

Info

Publication number: CN118316403A
Application number: CN202410405943.6A
Authority: CN
Inventors: 胡梦莹; 蒋佳君; 郑胜群; 黄家赓
Original assignee: Suzhou Novosense Microelectronics Co ltd; Shanghai Naxi Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd; Shanghai Naxi Microelectronics Co ltd
Priority date: 2024-04-03
Filing date: 2024-04-03
Publication date: 2024-07-09

Abstract

The application provides an operational amplifier circuit, an operational amplifier, a chip and an electronic device, wherein the operational amplifier circuit comprises: the first stage circuit is an input stage of the operational amplifier and is used for receiving and amplifying an input signal; the second stage circuit is an output stage of the operational amplifier and is used for driving the signal amplified by the first stage circuit to generate an output signal; and one end of the impedance device is connected with the output node of the first stage circuit, the other end of the impedance device is connected with the input node of the second stage circuit so as to isolate the output node from the input node, and a voltage drop is generated between the output node and the input node when a path of current is input to the input node, and the voltage drop enables the voltage of the output node to be higher than the voltage of the input node so that the first stage circuit provides gain enhancement. The application can ensure that the first stage circuit realizes the effect of gain enhancement.

Description

Operational amplifier circuit, operational amplifier, chip and electronic device

Technical Field

The present application relates to the field of signal processing technologies, and in particular, to an operational amplifier circuit, an operational amplifier, a chip, and an electronic device.

Background

Operational amplifiers, which are analog circuits, play an important role in mixed signal processing. The signal amplifying, filtering and accurate adjusting functions can be realized through high gain and multifunction. However, the output voltage swing and dc gain needs to be considered when designing an operational amplifier. This results in a reduced dc gain due to the fact that the output voltage needs to be close to the supply rail in practice. It is therefore a problem to be solved how to achieve high output swing and large driving capability while maintaining high gain. Common solutions include two-stage op amp structures, complementary input pair folded cascode structures, CLASS-AB output stages, and the like. However, a problem with these approaches is that the first stage output node voltage margin is insufficient, affecting the gain and signal accuracy of the operational amplifier.

Disclosure of Invention

The application provides an operational amplifier circuit, an operational amplifier, a chip and electronic equipment, which are used for solving the problem of how to realize gain enhancement of the operational amplifier.

In a first aspect, the present application provides an operational amplification circuit comprising:

The first stage circuit is an input stage of the operational amplifier and is used for receiving and amplifying an input signal;

The second stage circuit is an output stage of the operational amplifier and is used for driving the signal amplified by the first stage circuit to generate an output signal;

And one end of the impedance device is connected with the output node of the first stage circuit, the other end of the impedance device is connected with the input node of the second stage circuit so as to isolate the output node from the input node, and a voltage drop is generated between the output node and the input node when a path of current is input to the input node, and the voltage drop enables the voltage of the output node to be higher than the voltage of the input node so that the first stage circuit provides gain enhancement.

In an embodiment of the present application, the first stage circuit includes at least one layer of a first transistor having a cascode structure and a second transistor corresponding to the first transistor for forming the current, the second stage circuit includes a third transistor having a CLASS-AB structure, and the first transistor, the second transistor, and the third transistor are grounded in a cascode manner.

In an embodiment of the present application, when the current is input at the input node, the current generates a voltage drop between the output node and the input node by using the gate terminal of the third transistor in an off state, the voltage drop increases the voltage of the output node to V _gsn +Δv, where V _gsn represents the gate-source voltage of the third transistor, Δv represents the voltage drop, where Δv=r ₀*I₀,R₀ represents the impedance value of the impedance device, and I ₀ represents the current.

In one embodiment of the present application, the first stage circuit includes at least one layer of first transistors of a cascode structure for providing a tail current source; when the current is input at the input node, the voltage of the output node is increased by delta V after the current flows through the impedance device; the current is configured to be less than a bias current I _sn generated by the tail current source, and an equivalent output impedance of the current at the input node is greater than a total impedance of the output impedance of the first stage circuit and the impedance device.

In an embodiment of the present application, the gain of the first stage circuit is:

A_v1＝(g_mr_out)ⁿ；

Wherein A _v1 represents the gain of the first stage circuit, g _mr_out represents the gain of each layer of transistor with the cascode structure, and n represents the total number of layers of the cascode structure.

In an embodiment of the present application, the first stage circuit further includes a fourth transistor corresponding to the second transistor, and a current flowing through the fourth transistor and the second transistor respectively originates from the same bias circuit for canceling current noise.

In an embodiment of the application, the operational amplifier circuit further comprises a capacitor connected in parallel with the impedance device, the capacitor being used to adjust a pole-zero inside the operational amplifier circuit.

In one embodiment of the application, the magnitude of the one current is in the range of μA to nA.

In an embodiment of the present application, a drain of the first transistor is connected to the output node of the first stage circuit, the input node of the second stage circuit is connected to a drain of the second transistor and a gate of the third transistor, respectively, and a drain of the third transistor is an output terminal of the operational amplifier circuit.

In an embodiment of the application, the first stage circuit is used to provide gain enhancement, and the second stage circuit is a fixed gain and is used to provide a large output swing or a strong driving capability.

In a second aspect, the present application also provides an operational amplifier comprising an operational amplifier circuit as claimed in any one of the first aspects.

In a third aspect, the application also provides a chip comprising an operational amplifier as described in the second aspect.

In a fourth aspect, the application also provides an electronic device comprising an operational amplifier as described in the second aspect.

The application provides an operational amplifier circuit, an operational amplifier, a chip and electronic equipment, wherein the operational amplifier circuit comprises an input stage and an output stage, the input stage is used for receiving and amplifying an input signal, and the output stage is used for driving an output signal. In order to realize the problem of gain enhancement of the operational amplifier circuit, an impedance device is introduced. One end of the impedance device is connected with the output node of the first-stage circuit, and the other end of the impedance device is connected with the input node of the second-stage circuit. The circuit has the function of isolating the output node from the input node and generating voltage drop when the input node inputs current, wherein the voltage drop enables the voltage of the output node to be higher than that of the input node, so that the effect of gain enhancement of the first-stage circuit is ensured.

Drawings

In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a circuit diagram of a two-stage folded cascode operational amplifier architecture;

FIG. 2 is a schematic circuit diagram of an operational amplifier circuit;

FIG. 3 is a schematic circuit diagram of another operational amplifier circuit;

FIG. 4 is a schematic circuit diagram of an operational amplifier circuit provided by the present application;

FIG. 5 is a circuit diagram of an operational amplifier circuit according to a first embodiment of the present application;

fig. 6 is a circuit diagram of an operational amplifier circuit according to a second embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein.

The following is a description of terms related to the present application.

Operational amplifier (Operational amplifier, abbreviated Op-Amp): is an analog circuit device. It is typically composed of a plurality of integrated circuit transistors having two inputs (a non-inverting input and an inverting input) and one output. The main function of the operational amplifier is to amplify an input signal and output a signal having a linear relationship with the input.

Gain: representing the proportional relationship between the output signal and the input signal. In particular, it represents the degree to which an operational amplifier amplifies an input signal.

High output swing: it means that the operational amplifier can obtain a larger voltage range when outputting a signal. This means that the operational amplifier can output a signal amplitude that approaches or reaches the maximum or minimum value of the supply voltage.

Large driving capability: meaning that the op amp output stage is capable of providing more current or power to drive the load circuit. The strong driving capability means that the output stage can provide enough current or power to propel the load to operate properly.

Voltage margin: refers to the difference or margin between the output voltage and the supply voltage in the circuit design. It shows how far the output voltage allowed by the system deviates from the supply voltage under actual operating conditions. In operational amplifier designs, it is important to have sufficient voltage margin. Since there may be fluctuations or instabilities in the supply voltage, in this case the output voltage should not be too close to the supply rails (e.g. positive and negative supply). Otherwise, once the output voltage approaches the power rail, a problem will occur in that the voltage cannot be further amplified, resulting in output distortion or unsatisfactory signal processing. Therefore, to ensure that the operational amplifier can maintain high gain and normal output under different operating conditions, it is necessary to have a sufficient voltage margin. Thus, even if the power supply voltage fluctuates or is unstable, the output voltage still has enough margin and cannot approach the power supply rail, so that higher gain and signal precision are maintained.

From the structural point of view of the operational amplifier, different amplifier designs can achieve high gain through different gain multiplication techniques. However, a single-level op-amp is limited in its limited output range and thus cannot meet certain application requirements. To optimize the output swing, a multistage cascade of amplifier structures may be employed. This configuration can provide a larger output range by performing signal amplification at a plurality of levels. However, multistage cascaded amplifiers also have problems including higher power consumption and difficulty in ensuring system stability.

In contrast, a two-stage operational amplifier adopts a more widely used structure, and referring to fig. 1, fig. 1 is a circuit diagram of a two-stage folded cascode operational amplifier structure. The folded cascode structure formed by the complementary input pairs is adopted in fig. 1, and the folded cascode structure has the characteristics of realizing the input signal swing exceeding the range of a power supply and high gain. Meanwhile, the output signal swing close to the power supply voltage can be realized by combining the CLASS-AB output stage.

The complementary input pair folding cascode structure is an operational amplifier input stage circuit structure. By adopting the complementary input pair, the capability of the input signal swing exceeding the range of the power supply can be realized. The folded cascode structure design also provides high gain characteristics so that the signal can be effectively amplified at the input stage.

While the CLASS-AB output stage may help achieve an output signal swing that is close to the supply voltage. The CLASS-AB output stage is a special output stage circuit design that is capable of maintaining low power consumption in small signal conditions and providing large output drive capability in large signal conditions. By using such an output stage circuit, the swing of the output signal can be controlled within a range close to the power supply voltage, so as to meet the requirement of the output signal range in practical application.

As shown in fig. 1, in order to ensure that the operational amplifier has a high gain, the output stage transistor needs to be in the saturation region, i.e. the input signal needs to meet the following conditions:

V_gsn,p<V_dsn,p+V_thn,p。

Where V _gsn,p denotes the gate-source voltage of the input transistor (pMOS), which refers to the difference between the gate voltage and the source voltage of the pMOS transistor under the action of an input signal. V _dsn,p denotes the drain-source voltage of the output stage transistor (pMOS), which refers to the difference between the source voltage and the drain voltage of the output stage pMOS transistor. The parameter is indicative of the drain voltage of the output stage transistor during processing of the signal. V _thn,p denotes the threshold voltage of the output stage transistor (pMOS), which is the voltage required when the gate-source voltage of the pMOS transistor reaches the critical point.

When the output node V _out of the op-amp is at the peak of the sine wave (V _x and V _y), the source-drain voltages (V _dsn,p) of the output stage transistors M _p and M _n are greatly compressed, while the threshold voltage V _thn,p is largely determined by the process parameters, and remains substantially unchanged, so a small input voltage V _gsn,p is required to ensure high gain over the entire signal range.

Meanwhile, in order to realize large output driving capability, a CLASS-AB output stage is adopted in a second stage of the operational amplifier, and higher output capability can be obtained through smaller static bias current I _D. According to a current-voltage relation formula of the MOS transistor:

where μ _n,p denotes mobility (carrier mobility) of the transistor, which is a parameter measuring a moving speed of charge carriers in the field effect transistor, μ _n,p denotes mobility of a forward operation region, W denotes a channel width of the transistor, L denotes a channel length of the transistor, n, p denotes a channel depth coefficient (CHANNEL DEPTH factor) of the transistor, which is a parameter measuring an influence of channel depth on mobility, V _gsn,p denotes a gate-to-source voltage (gate-to-source voltage) of the transistor, i.e., a difference between the gate voltage and the source voltage, and V _thn,p denotes a threshold voltage (threshold voltage) of the transistor, i.e., when the gate-to-source voltage exceeds the threshold voltage, the transistor starts to be turned on.

As can be obtained from the above formula, increasing the width-to-length ratio (W/L) _n,p of the output stage can improve the driving capability of the output stage under the condition that the static bias current I _D is fixed. However, this results in the input voltage V _gsn,p being compressed.

Thus, to achieve a high output voltage swing or large driving capability, the input voltage V _gsn,p of the output stage transistors M _n and M _p of the operational amplifier is greatly reduced, which results in an insufficient voltage range between the first stage output nodes V _an and V _ap and ground/power, resulting in the first stage cascode transistors (M ₁ to M ₄) exiting the saturation region and a sharp drop in the equivalent output impedance R _out1. Therefore, the gain of the operational amplifier is affected, and the accuracy of the processed signal is lowered.

From this, it is known how to achieve a high output swing or a large driving capability while maintaining the high gain characteristic of the operational amplifier is an urgent problem to be solved. That is, while increasing the output voltage swing and driving capability can meet specific requirements, it can also negatively impact the gain and signal processing accuracy of the operational amplifier. Therefore, appropriate measures are required to overcome these problems to achieve a balance of high output swing, large driving capability, and high gain.

One solution is to use gain multiplication techniques, which essentially keep the first stage output swing unchanged, i.e. the voltage margin between the output nodes (V _an and V _ap) and ground/supply, while achieving high voltage gain by introducing a high gain op amp a _gb. Specific circuit implementation as shown in fig. 2, fig. 2 is a schematic circuit diagram of an operational amplifier circuit.

Specifically, an additional large gain operational amplifier a _gb is introduced between the gate-sources of the output stage transistor M ₃. The characteristic of the input dummy short of the operational amplifier is utilized to form a feedback loop to forcedly lock the drain terminal of the transistor M ₄ at a fixed value. Such control reduces the effect of the change in the drain voltage of transistor M ₃ on the output impedance of transistor M ₄, meaning that the current of the tail current source formed by transistor M ₄ remains substantially constant, thus exhibiting a higher output impedance. In other words, the output impedance of the first stage NMOS current mirror is multiplied to a _gb*R_n at this time by the original R _n. Thus, a higher low frequency gain can be achieved in this way.

That is, the gain multiplication technique may achieve higher voltage gain by introducing a large gain op amp a _gb and using feedback to keep the first stage output swing unchanged. The technique can improve gain characteristics of an operational amplifier in a low frequency range.

The introduction of gain multiplication techniques in the design faces some of the following problems:

First, since a loop formed by the operational amplifier a _gb is added, the influence of the stability of the loop on the entire operational amplifier needs to be considered. In order to maintain stability, it is necessary to design the unity gain Bandwidth (Unit Gain Bandwidth, GBW) of the operational amplifier a _gb to be consistent with the Bandwidth (Bandwidth) of the original cascode amplifier. If the unity gain bandwidths do not match, pole-zero pairs are created, compromising the stability of the system and limiting the performance of the op-amp at high frequencies.

Second, the mismatch of op amp a _gb is also translated to an input pair through output stage transistor M ₃ to form an offset voltage. Therefore, the input pair size of the operational amplifier a _gb also needs to be large enough to ensure matching. This means that additional power consumption and increased chip area are required to achieve such a structure.

Thus, the design complexity involved in introducing the gain multiplication technique in fig. 2 requires not only consideration of loop stability and maintenance of unity gain bandwidth, but also the handling of bias current and additional power consumption due to mismatch and the cost overhead of chip area. In summary, these factors make gain multiplication techniques less friendly in terms of low power design and chip cost.

Another solution is to use a gain multiplication technique of a serial output stage structure, which naturally increases the equivalent minimum feature size L of the output tube, thereby facilitating the increase of the output impedance, and further realizing gain enhancement by adjusting the substrate-source voltage V _bs of the output device. Specific circuits are shown in fig. 3, and fig. 3 is a schematic circuit diagram of another operational amplifier circuit.

Specifically, the transistor M _na and the transistor M _nb are connected in series to form a transistor M _n. Typically, transistor M _na is located in the saturation region and transistor M _nb is located in the linear region. By adjusting the substrate voltage V _bsa of transistor M _na, in accordance with the current-voltage relationship of the MOS device, in the case of a fixed bias current, when V _bsa is positive, V _gsn decreases while V _dsnb increases, resulting in transistor M _nb gradually entering the saturation region, and the output impedance of the output stage increases accordingly. When V _bsa is negative, V _gsn increases, resulting in a voltage increase of V _an, and V _ds of transistors M ₃ and M ₄ increases, resulting in an increase in the output impedance of the first stage, achieving a gain enhancement effect.

In short, this gain multiplication technique achieves gain enhancement by adjusting the substrate-source voltage V _bsa of the output device through a series-connected output stage structure. In the structure, the equivalent minimum characteristic size of the output pipe is amplified, so that the output impedance is effectively improved, the output pipe is in different working states by adjusting the substrate-source voltage, the output impedance is further changed, and the effect of gain enhancement is realized.

It can thus be seen that the circuit shown in fig. 3, due to the output stage structure with two transistors in series, results in an increase in the equivalent minimum feature size L (in micrometers μm), thus reducing the driving capability of the output stage. In addition, in the case where the substrate-source voltage V _bsa is positive, it is necessary to ensure that the PN junction of the substrate-source does not conduct forward under process and temperature deviations to improve the robustness of the design.

In summary, the main disadvantages of the gain multiplication technique introduced in fig. 2 are as follows:

Design complexity increases: the need to take into account loop stability and unity of unity gain bandwidth and handle bias currents caused by mismatch adds complexity to the design.

Additional power consumption: the use of gain multiplication techniques results in additional power consumption overhead.

Chip area increases: to implement the gain multiplication technique, additional circuit components are required, increasing the area overhead of the chip.

Is not suitable for low-power consumption design: the gain multiplication technique is less friendly for low power designs because it introduces additional power consumption.

The main disadvantages of the output stage structure of two transistors in series in fig. 3 are as follows:

output stage drive capability decreases: this structure results in an increase in the equivalent minimum feature size, thereby reducing the driving capability of the output stage.

The robustness requirement is high: under the condition that the substrate-source voltage is positive, the PN junction of the substrate-source cannot be conducted forward under the conditions of process and temperature deviation, and higher requirements are placed on the robustness of the design.

The application aims to enhance the DC gain of an operational amplifier on the basis of keeping the high output swing or large driving capacity of the operational amplifier. According to the analysis, the direct current gain in the application scene is limited by a lower V _gsn,p (peak voltage of an input signal), so that the cascode structure formed by the first-stage transistor exits from a saturation region and cannot work normally, and further, the gain is attenuated.

The core idea of the application is thus to achieve an enhancement of the dc gain by increasing the voltage margin of the first stage output nodes V _an and V _ap to ground/supply while keeping the input signal peak voltage V _gsn,p unchanged. Thus, the limitation of the saturation region of the first-stage transistor can be overcome, and the overall gain performance is improved.

That is, the present application enhances the DC gain of the operational amplifier while maintaining a high output swing or large driving capability. The limitation of the saturation region of the first-stage transistor is overcome by increasing the voltage margin from the output node of the first stage to the ground/power supply, so that the gain is improved.

In some embodiments of the present application, please refer to fig. 4, fig. 4 is a schematic circuit diagram of an operational amplifier circuit according to the present application. An operational amplification circuit includes a first stage circuit 401, a second stage circuit 402, and an impedance device 403.

Illustratively, the first stage 401 is an input stage of an operational amplifier for receiving and amplifying an input signal. Specifically, the first stage circuit 401 may be a tail current source constituting an input stage of the operational amplifier for realizing high output impedance of the input stage.

In particular, the operational amplifier may be composed of a plurality of stages, wherein the first stage circuit 401 (input stage) functions to receive an input signal and amplify it. The first stage 401 is responsible for amplifying the input signal before passing it to a subsequent stage for further processing. Thus, the gain and the driving capability of the input signal can be ensured, and stable and high-quality output can be provided for the whole operational amplifier.

The second stage circuit 402 is an output stage of an operational amplifier, and is used for driving a signal amplified by the first stage circuit 401 to generate an output signal.

Specifically, the operational amplifier is generally composed of a plurality of stages, wherein the second stage circuit 402 (output stage) is responsible for further amplifying and driving the signal processed by the previous stage, and finally generating an output signal. The output stage circuit amplifies the input signal to meet the application requirements and provides sufficient output current and output power to drive an external load.

Illustratively, the impedance device 403 (i.e., R ₀) has one end connected to the output node V _an of the first stage 401 and the other end connected to the input node V _bn of the second stage 402 to isolate the output node V _an from the input node V _bn, and when a current I ₀ is input to the input node V _bn, a voltage drop of Δv is generated between the output node V _an and the input node V _bn, where the voltage drop of Δv makes the voltage of the output node V _an higher than the voltage of the input node V _bn to ensure that the first stage 401 achieves gain enhancement. Where Δv=r ₀*I₀,R₀ denotes the impedance value of the impedance device.

Therefore, the present application can generate a certain voltage drop on the impedance device R ₀ by inserting the impedance device R ₀ between the output node V _an of the first stage circuit 401 and the input node V _bn of the second stage circuit 402 and introducing a current I ₀ to the impedance device R ₀ near the input node V _bn of the second stage circuit 402. In this way, the first stage circuit 401 can maintain a high output voltage margin even when a process with a low threshold voltage is employed. By ensuring that the output voltage of the first stage 401 has sufficient margin, the first stage 401 can be placed in a better saturation state and the gain of the first stage 401 can be increased. The saturated state means that the transistor is in its most saturated operating region, and higher voltage amplification can be achieved.

Illustratively, the impedance device R ₀ may employ a passive device or a transistor in a linear operating region. Passive devices refer to devices in a circuit that do not require an external power source to power, and may include resistors, capacitors, inductors, and the like. Thus, in the present application, the impedance device R ₀ may be implemented using a passive device. Resistors are a common passive device that can achieve a desired voltage drop by adjusting the resistance value. Another implementation is to use transistors that operate in the linear region. The transistor can be operated in the linear region by means of the voltage signal, i.e. the voltage-current relationship of the transistor is now the same as the linear resistance. Thus, by using such a transistor, it can be used as an impedance device R ₀ to achieve a desired voltage drop.

Illustratively, the first stage circuit 401 includes at least one layer of a first transistor 4011 of a cascode structure and a second transistor 4012 in combination with the first transistor 4011 for forming the current, and the second stage circuit 402 includes a third transistor 4021 (i.e., M _n) of a CLASS-AB structure. The first transistor 4011, the second transistor 4012, and the third transistor 4021 are commonly grounded.

Wherein CLASS-AB is a mode of operation of the power amplifier. In a CLASS-AB amplifier, two complementary on transistors may be employed to provide the amplifying function. One is a P-type transistor responsible for amplifying the positive half cycle input signal and the other is an N-type transistor responsible for amplifying the negative half cycle input signal. The CLASS-AB amplifier is characterized in that only one of the transistors is in operation and the other is off when the input signal is small. Thus, static power consumption can be reduced and efficiency can be improved. When the input signal amplitude exceeds a certain threshold, the two transistors will operate simultaneously to ensure that the output signal is amplified completely.

Specifically, as shown in fig. 4, when a current I ₀ is input at the input node V _bn, the current I ₀ generates a voltage drop of Δv between the output node V _an and the input node V _bn by using the gate terminal of the third transistor 4021 in an off state, and the voltage drop of Δv increases the voltage of the output node V _an to V _gsn +Δv, where V _gsn represents the gate-source voltage of the third transistor 4021. In this way, the voltage margin at the output terminal of the first stage circuit 401 increases, and the first transistor 4011 can be in a more saturated state, resulting in an increase in output impedance, thereby achieving gain enhancement of the operational amplifier.

That is, the output node V _an of the first stage circuit 401 is isolated from the input node V _bn of the second stage circuit 402 by the introduction of the lateral current I ₀ and the impedance device R ₀. Current I ₀ is then input at input node V _bn of the second stage circuit 402, and the third transistor 4021 exhibits an off characteristic, resulting in a voltage drop of Δv between output node V _an and input node V _bn. The voltage drop of the DeltaV increases the voltage from V _an to ground, so that the voltage margin of the output end of the first stage circuit 401 is improved, the output end reaches a more saturated state, the output impedance is increased, and the gain is enhanced.

It should be noted that, a current I ₀ is input at the input node V _bn, and the current I ₀ can be replicated in an equal proportion manner by using a current bias function in the operational amplifier and a corresponding circuit design.

Illustratively, the first stage circuit is for achieving gain enhancement, and the second stage circuit is for achieving a fixed gain and for achieving a large output swing or a strong driving capability.

Specifically, the first stage circuit is designed to enhance the gain of the signal. It may employ different amplifier configurations and structures to provide higher amplification and to enhance the strength of the input signal. By enhancing the output by the gain of the first stage, the amplitude of the signal can be increased and the sensitivity of the circuit increased. And the second stage circuit is used for providing fixed gain. Its main purpose is to achieve a large output swing or strong driving capability. That is, the second stage circuit can provide a sufficient amplification factor so that the input signal can have a larger amplitude after being amplified and the external load can be driven at a larger amplitude. The output capability is stronger, and the requirement on large output swing or strong driving capability can be met. This combined design allows the circuit to have both high gain and large output capability.

The operational amplifier circuit of the present application will be specifically described by way of examples.

Embodiment one:

Referring to fig. 5, fig. 5 is a circuit diagram of an operational amplifier circuit according to an embodiment of the application. The first stage circuit 401 includes at least one layer of a first transistor 4011 of a cascode structure for implementing the tail current source I _sn. The drain of the first transistor 4011 is connected to the output node V _an of the first stage 401, the input node V _bn of the second stage 402 is connected to the drain of the second transistor 4012 and the gate of the third transistor 4021, and the drain of the third transistor 4021 (i.e., M _n) is the output terminal V _out.

When a current I ₀ is input at the input node V _bn, the current I ₀ flows through the impedance device R ₀ to increase the voltage at the output node V _an by Δv. Since current I ₀ is configured to be much smaller than the bias current I _sn generated by the tail current source, the equivalent output impedance R _comp of current I ₀ at input node V _bn is much greater than the total impedance of the output impedance R _n of the first stage circuit and the impedance device R ₀.

Specifically, fig. 5 shows a tail current source I _sn (which can also be understood as an introduced static bias current source) implemented by the first transistor 4011 of the two-layer cascode structure. The first transistor 4011 includes a first layer transistor M ₃ (base voltage V _b2) and a second layer transistor M ₄ (base voltage V _b1). The second transistor 4012 corresponding to the first transistor 4011 is used to form a current I ₀. The number of layers of the second transistor 4012 is the same as that of the first transistor 4011, that is, two layers, and the base voltage corresponding to the two layers is V _b2、V_b1.

First, current I ₀ is associated with tail current source I _sn by adjusting the proportional relationship of current I ₀ and tail current source I _sn (e.g., the proportional relationship of current I ₀ and tail current source I _sn may be set to 1:10). And inputs a current I ₀ at an input node V _bn.

Current I ₀ then passes through an impedance device R _o in the circuit, causing the voltage of output node V _an to ground to increase by Δv (for example, Δv can be set to 100-500 mV). Since current I ₀ is much smaller than tail current source I _sn, the equivalent output impedance R _comp of current I ₀ is much greater than the total impedance of the output impedance R _n of the first stage circuit and the impedance device R _o at input node V _bn. Wherein, R _n is the output impedance of the first layer transistor M ₃ and the second layer transistor M ₄ connected in series, and the output impedance R _n is connected in series with the impedance device R _o.

When the equivalent output impedance R _comp is in parallel with the output impedance R _n, the overall equivalent output impedance is still determined by R _n, and the output of the first stage circuit 401 is in a more saturated operating state due to the increase of the voltage V _ds between the source and drain of the first layer transistor M ₃ and the second layer transistor M ₄, thereby increasing the output impedance R _n of the first stage circuit 401. This achieves a gain boost because the increased R _n affects the output characteristics of the overall circuit, enhancing the output signal.

Therefore, the circuit shown in fig. 5 uses the tail current source I _sn and the additional current I ₀ to adjust the voltage of the output node V _an, so as to achieve the gain improvement of the whole circuit. By setting proper current proportion and impedance adjustment, the enhancement effect of the circuit output is realized.

In some embodiments of the present application, the above scheme may be further extended to a cascade of multiple layers (e.g., three or more layers) of the first stage circuit to achieve higher gain. The gain A _v1 of the first stage circuit is as follows:

A_v1＝(g_mr_out)ⁿ；

Where g _mr_out represents the gain of each layer of cascode transistors and n represents the total number of layers of the cascode. Wherein, the transistors of each layer of the cascode structure can be connected in series.

For example, assuming a three-layer cascode configuration, the gain of the first stage circuit, a _v1＝(g_mr_out)³, is achieved. At this time, the voltage of the output node V _an can also meet the overdrive voltage of the three-layer cascade cascode structure to ensure that the overdrive voltages are in the saturation region, thereby realizing high gain.

Therefore, the first-stage circuit of the application can adopt a multi-layer cascode structure, thereby realizing higher output impedance. In a transistor circuit, the cascode structure is an amplifier structure. It consists of a common source portion between the source and drain, and a common gate portion between the gate and drain. This structure has the characteristics of low input impedance and high output impedance. By adopting a multi-layer cascode structure, the output impedance can be further improved. The multi-layer structure comprises a cascade combination of multiple levels, each level being responsible for respective amplification and output. By cascading multiple levels of outputs, a higher output impedance may be achieved. A higher output impedance means that the circuit can provide a higher impedance value at the output port, reducing the impact on the external load and thus better maintaining the linearity of the circuit. This is useful for certain applications, such as where complex loads need to be driven or where output impedance matching is required.

Embodiment two:

Referring to fig. 6, fig. 6 is a circuit diagram of an operational amplifier circuit according to a second embodiment of the application. Fig. 6 shows a first transistor 4011 of a three-layer cascode structure. The base voltages corresponding to the three-layer cascode structure are V _b1、V_b2 and V _b3, respectively. The second transistor 4012 corresponding to the first transistor 4011 is used to form a current I ₀. The number of layers of the second transistor 4012 is the same as that of the first transistor 4011, that is, three layers, and base voltages corresponding to the three layers are V _b1、V_b2 and V _b3.

Since the input current I ₀ at the input node V _bn introduces some current noise, and this noise is transconductively converted by the input stage and is presented to the input. The noise of the current source I ₀ comes mainly from its bias circuit.

In order to achieve the optimization in the low noise operational amplifier, a specific design scheme is proposed as shown in fig. 6, that is, the first stage circuit 401 further includes a fourth transistor 4013 configured on the other side and corresponding to the second transistor 4012, and a path of current flowing through the fourth transistor 4013 and the second transistor 4012 respectively comes from the same bias circuit for canceling the current noise mutually.

Specifically, this scheme is achieved by inserting the same current source I ₀ as V _bn at the other end V' _bn of the op amp, and the two current sources are generated from the same bias circuit. By such a design, the noise generated by the two I ₀ inserted into the output node V _an of the first stage circuit 401 is the same in magnitude, i.e., common mode noise. Thus, common mode noise is not reflected at the input end of the operational amplifier, thereby avoiding the deterioration of the noise index of the operational amplifier.

That is, by inserting the same current source I ₀ at the other end V' _bn of the op amp as at V _bn and ensuring that the two current sources are generated by the same bias circuit, the noise introduced by the two I ₀ at the first stage output node V _an can be made the same, i.e., common mode noise. The design method ensures that common mode noise cannot be transmitted to the input end of the operational amplifier, thereby effectively avoiding the influence on noise performance and realizing the optimization of the low-noise operational amplifier.

In some embodiments of the application, the magnitude of the current I ₀ is on the order of μa (microamperes) to nA (nanoamps).

In particular, the magnitude level of the one-way current I ₀ may be selected between the order of microamps to nanoamps. This means that the current is typically between 10 ^-6 and 10 ^-9 amps in magnitude. The specific current values may vary depending on design requirements and choice of circuit parameters.

In some embodiments of the present application, the operational amplifier circuit further comprises a capacitor C ₀, the capacitor C ₀ is connected in parallel with the impedance device R ₀, and the capacitor C ₀ is used to adjust a pole-zero inside the operational amplifier circuit to ensure loop stability of the operational amplifier circuit.

Specifically, in the operational amplification circuit, the pole-zero refers to a special frequency point in the amplitude-frequency response, wherein the numerator of the transfer function is zero, and the denominator is a pole. Adjusting the position of these pole-zeroes can affect the frequency response and stability of the operational amplifier circuit.

By connecting the capacitor C ₀ in parallel with the impedance device R ₀, a compensation element can be introduced in the feedback path of the operational amplifier circuit. This compensation element includes a capacitor C ₀ and an impedance device R ₀. By properly selecting the values of capacitor C ₀ and impedance device R ₀, the pole-zero position of the op-amp circuit can be adjusted.

Adjusting the position of the pole-zero may improve the frequency response and stability of the operational amplifier circuit. Particularly in a high-gain or high-frequency environment, unstable oscillation or phase delay problems of the operational amplifier circuit can be avoided by properly adjusting the values of C ₀ and R ₀, so that the stability and the performance of the circuit are ensured.

For example, in low noise and low power designs, the current I ₀ is typically on the order of microamps or even nanoamps. To achieve a Δv voltage drop on the order of hundred millivolts, an impedance device R ₀ on the order of 10 ⁵ Ω needs to be used. But such resistance values will change the non-dominant pole location of the op-amp. To maintain system stability, adjustment can be made by adjusting compensation capacitor C ₀. The compensation capacitor C ₀ is used to compensate for instability due to non-dominant pole point position variation caused by using high resistance to achieve good system stability.

In summary, the operational amplifier circuit provided by the application improves the gain of the operational amplifier circuit based on a large output swing or a strong output driving capability. And the operational amplifier circuit has lower complexity, and obviously reduces the power consumption and the chip area so as to meet the requirements of the current mixed signal processing chip.

In addition, the operational amplifier circuit can ensure good system stability under process deviation and temperature variation, and has good robustness. This means that reliable performance and stability can be maintained even when there is some error in the process manufacturing process or when the chip operating temperature changes.

In addition, the operational amplifier circuit can be applied to chip application with severe working environment requirements, such as industrial field or vehicle rule field. It can be operated stably under these severe conditions and is robust enough.

Besides, the operational amplifier circuit is suitable for the design of operational amplifiers with large output swing or strong output driving capability, and is also suitable for the design of low-noise operational amplifiers. Therefore, the operational amplifier circuit has wide application range and can play a role in different application scenes.

In further embodiments of the application, the application also provides an operational amplifier comprising an operational amplifier circuit as described in any of the embodiments above.

In particular, the operational amplifier can be used as an independent module for various applications such as signal processing, feedback control and the like.

In further embodiments of the application, the application also provides a chip comprising an operational amplifier as described in any of the embodiments above.

Specifically, the chip is based on the design and layout of the operational amplifier circuit, and the operational amplifier circuit is realized on one chip through the integrated circuit technology. Such chips may be used for integration into a variety of electronic systems and devices to accomplish specific tasks and functions.

In further embodiments of the application, the application further provides an electronic device comprising an operational amplifier as described in any of the embodiments above.

Specifically, the electronic device includes the aforementioned operational amplifier, which may be a stand-alone module or embedded in other circuit boards or devices. The electronic device may be used in various applications, such as in the fields of audio amplifiers, sensor signal processing, automatic control, etc.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An operational amplification circuit, characterized in that the operational amplification circuit comprises:

2. The operational amplifier circuit of claim 1, wherein the first stage circuit comprises at least one layer of a first transistor of a cascode structure and a second transistor corresponding to the first transistor for forming the current, the second stage circuit comprises a third transistor of a CLASS-AB structure, and the first transistor, the second transistor, and the third transistor are cascode grounded.

3. The operational amplifier circuit of claim 2, wherein when the current is input at the input node, the current generates a voltage drop between the output node and the input node with the gate terminal of the third transistor in an off state, the voltage drop boosting the voltage of the output node to V _gsn +Δv, where V _gsn represents a gate-source voltage of the third transistor, Δv represents the voltage drop, where Δv = R ₀*I₀,R₀ represents an impedance value of the impedance device, and I ₀ represents the current.

4. The operational amplifier circuit of claim 2, wherein the first stage circuit comprises at least one layer of first transistors of a cascode configuration for providing a tail current source; increasing the voltage at the output node by Δv when the current is input at the input node after the current flows through the impedance device, wherein Δv represents the voltage drop; the current is configured to be less than a bias current generated by the tail current source, an equivalent output impedance of the current at the input node being greater than a total impedance of the output impedance of the first stage circuit and the impedance device.

5. The operational amplifier circuit of claim 2, wherein the gain of the first stage circuit is:

A_v1＝(g_mr_out)ⁿ；

6. The operational amplifier circuit of claim 2, wherein the first stage circuit further comprises a fourth transistor corresponding to the second transistor, and a path of current flowing through the fourth transistor and the second transistor, respectively, is derived from the same bias circuit for canceling current noise from each other.

7. The operational amplifier circuit of claim 1, further comprising a capacitor connected in parallel with the impedance device, the capacitor for adjusting a pole-zero inside the operational amplifier circuit.

8. The operational amplifier circuit of claim 1, wherein the magnitude of the current is on the order of μa to nA.

9. The operational amplifier circuit of claim 2, wherein a drain of the first transistor is connected to the output node of the first stage circuit, the input node of the second stage circuit is connected to a drain of the second transistor and a gate of the third transistor, respectively, and a drain of the third transistor is an output terminal of the operational amplifier circuit.

10. An operational amplifier circuit according to claim 3, wherein the first stage circuit is configured to provide gain enhancement and the second stage circuit is configured to provide a fixed gain and to provide a large output swing or a strong driving capability.

11. An operational amplifier comprising an operational amplifier circuit as claimed in any one of claims 1 to 10.

12. A chip comprising the operational amplifier of claim 11.

13. An electronic device comprising the operational amplifier of claim 11.