CN118315291A - Capacitive isolator and preparation method thereof - Google Patents
Capacitive isolator and preparation method thereof Download PDFInfo
- Publication number
- CN118315291A CN118315291A CN202410706029.5A CN202410706029A CN118315291A CN 118315291 A CN118315291 A CN 118315291A CN 202410706029 A CN202410706029 A CN 202410706029A CN 118315291 A CN118315291 A CN 118315291A
- Authority
- CN
- China
- Prior art keywords
- chip
- transmitter
- receiver
- silicon
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 169
- 239000010703 silicon Substances 0.000 claims abstract description 169
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 160
- 239000003990 capacitor Substances 0.000 claims abstract description 152
- 238000002955 isolation Methods 0.000 claims abstract description 94
- 238000004519 manufacturing process Methods 0.000 claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000010410 layer Substances 0.000 claims description 102
- 238000000034 method Methods 0.000 claims description 55
- 239000011521 glass Substances 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005452 bending Methods 0.000 abstract description 5
- 238000005137 deposition process Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000005336 cracking Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 241000724291 Tobacco streak virus Species 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000013467 fragmentation Methods 0.000 description 2
- 238000006062 fragmentation reaction Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a capacitor isolator and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The preparation method of the capacitor isolator comprises the following steps: preparing an isolation capacitor chip, a transmitter chip and a receiver chip respectively, wherein the transmitter chip and/or the receiver chip are provided with through silicon vias; and respectively bonding the transmitter chip and the receiver chip with the isolation capacitor chip to obtain the capacitor isolator. The voltage resistance of the capacitor is not limited by the thickness of the metal interconnection layer at the rear end of the integrated circuit, the voltage resistance of the capacitor is improved, larger mechanical stress on the silicon substrate in the deposition process of the intermetallic insulating layer can be avoided, and the risks of bending or cracking of the substrate and failure of the device are reduced, so that the reliability of the device is improved. By converting the traditional two-dimensional integrated circuit into the three-dimensional integrated circuit, the area rate utilization rate of the chip is improved, better circuit connection is provided, the risk of failure of the device caused by stress is reduced, and the reliability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a capacitor isolator and a preparation method of the capacitor isolator.
Background
The capacitive isolator comprises a parallel plate capacitor with upper and lower polar plates as metal layers, insulating materials with silicon dioxide as main dielectrics are filled between the two polar plates, and besides the capacitor, the capacitive isolator further comprises two separated circuit modules: the transmitter circuit and the receiver circuit respectively comprise independent capacitor modules, and the two circuit modules are not directly electrically connected, and the capacitors in the two modules are connected only through bonding wires.
The current capacitive isolator mainly uses the rear end metal interconnection layer in the transmitter circuit and the receiver circuit as the upper and lower polar plates of the parallel plate capacitor, and the metal insulating layer as the dielectric layer of the capacitor. In integrated circuit fabrication processes, the intermetal insulating layer is typically prepared by Chemical Vapor Deposition (CVD) techniques, and if the thickness of the insulating layer is too thick, mechanical stresses may be generated on the silicon substrate. Such mechanical stress may cause bending or cracking of the silicon substrate, thereby affecting the performance and reliability of the device, and an excessively thick insulating layer may increase capacitance between metal wires, resulting in a slow signal transmission speed, and at the same time, may increase power consumption, and may also cause electrical short-circuit or disconnection between metal wires, thereby causing failure of the device.
Thus, existing capacitive isolators suffer from the problem of underlying device failure caused by too thick a dielectric layer.
Disclosure of Invention
The embodiment of the invention aims to provide a capacitor isolator and a preparation method of the capacitor isolator, which can avoid larger mechanical stress to a silicon substrate in the deposition process of an intermetallic insulating layer, reduce the risks of bending or cracking of the substrate and failure of a device, and further improve the reliability of the device.
In order to achieve the above object, a first aspect of the present application provides a method for manufacturing a capacitive separator, including:
Preparing an isolation capacitor chip, a transmitter chip and a receiver chip respectively, wherein the transmitter chip and/or the receiver chip are/is provided with a through silicon via;
Under the condition that the transmitter chip or the receiver chip is provided with a through silicon via, bonding one of the transmitter chip and the receiver chip with the through silicon via with the isolation capacitor chip, and bonding the other with the isolation capacitor chip through a metal layer on the top layer of the other to obtain a capacitor isolator;
And under the condition that the transmitter chip and the receiver chip are provided with through silicon vias, bonding the transmitter chip and the receiver chip with the isolation capacitor chip through the through silicon vias respectively to obtain the capacitor isolator.
In an embodiment of the present application, preparing a transmitter chip or preparing a receiver chip includes:
Preparing a silicon substrate, and manufacturing a silicon through hole on the silicon substrate by adopting a silicon through hole process to obtain the silicon substrate with the silicon through hole;
on the silicon substrate with the through silicon via, a CMOS manufacturing process is adopted to manufacture a CMOS device,
A back-end interconnection line is manufactured above the CMOS device by adopting a CMOS back-end process, and a first initial chip is obtained;
And carrying out wafer thinning treatment on the first initial chip to obtain a transmitter chip or a receiver chip.
In an embodiment of the present application, preparing a transmitter chip or preparing a receiver chip includes:
preparing a silicon substrate, and manufacturing a CMOS device on the silicon substrate by adopting a CMOS manufacturing process;
And manufacturing a back-end interconnection line above the CMOS device by adopting a CMOS back-end process, and manufacturing a first electrode plate on a metal layer on the top layer of the back-end interconnection line to obtain a transmitter chip or a receiver chip.
In the embodiment of the present application, when the transmitter chip and the receiver chip are both provided with through silicon vias, the preparation of the isolation capacitor chip includes:
preparing a glass substrate, and respectively manufacturing electrode plates on the upper surface and the lower surface of the glass substrate to form a first electrode plate and a second electrode plate so as to obtain the isolated capacitor chip.
In an embodiment of the present application, when the transmitter chip or the receiver chip is provided with a through silicon via, preparing an isolation capacitor chip includes:
preparing a glass substrate, manufacturing an electrode plate on any one of the upper surface and the lower surface of the glass substrate, and forming a second electrode plate to obtain the isolated capacitor chip.
In an embodiment of the present application, the bonding the transmitter chip and the receiver chip with the isolation capacitor chip through silicon vias to obtain a capacitor isolator includes:
The transmitter chip and the receiver chip are respectively arranged at two sides of the isolation capacitor chip; wherein the rear end interconnection lines of the transmitter chip and the receiver chip are far away from the isolation capacitor chip;
and bonding any one of the transmitter chip and the receiver chip with a first electrode plate on the isolation capacitor chip through a silicon through hole, and bonding the other one with a second electrode plate on the isolation capacitor chip through the silicon through hole to obtain the capacitor isolator.
In an embodiment of the present application, the bonding one of the transmitter chip and the receiver chip having a through silicon via to the isolation capacitor chip and the other to the isolation capacitor chip through a metal layer on a top layer thereof to obtain a capacitor isolator includes:
The transmitter chip and the receiver chip are respectively arranged at two sides of the isolation capacitor chip; wherein a back-end interconnect line of one of the transmitter chip and the receiver chip having a through-silicon via is distant from the isolation capacitance chip, and a back-end interconnect line of the other is close to the isolation capacitance chip;
And bonding one of the transmitter chip and the receiver chip, which is provided with the through silicon via, with the second electrode plate on the isolation capacitor chip through the through silicon via, and bonding the other one of the transmitter chip and the receiver chip, which is not provided with the electrode plate, with one end of the isolation capacitor chip through the first electrode plate on the metal layer of the top layer of the second electrode plate, so as to obtain the capacitor isolator.
In the embodiment of the application, the back-end interconnection line is manufactured above the CMOS device by adopting a CMOS back-end process, and the method comprises the following steps:
Depositing an interlayer medium above the CMOS device, and manufacturing a contact hole on the interlayer medium, wherein the contact hole is used for being connected with the CMOS device;
Depositing an inter-metal insulating layer above the interlayer dielectric, and manufacturing a first metal layer on the inter-metal insulating layer;
depositing an intermetallic insulating layer above the current metal layer, sequentially manufacturing a through hole and a metal layer on the newly deposited intermetallic insulating layer, wherein the metal layer is positioned above the through hole; this step is repeated a plurality of times to form a plurality of metal layers to obtain the back-end interconnect.
The second aspect of the present application provides a capacitive isolator, which is manufactured by the method for manufacturing a capacitive isolator, comprising: the device comprises an isolation capacitor chip, a transmitter chip and a receiver chip, wherein the transmitter chip and the receiver chip are respectively positioned at two sides of the isolation capacitor chip;
in the case that the transmitter chip or the receiver chip is provided with a through silicon via, one of the transmitter chip and the receiver chip having the through silicon via is connected with the isolation capacitor chip, and the other is connected with the isolation capacitor chip through a metal layer on the top layer thereof;
And under the condition that the transmitter chip and the receiver chip are both provided with through silicon vias, the transmitter chip and the receiver chip are respectively connected with the isolation capacitor chip through the through silicon vias.
In the embodiment of the application, under the condition that the transmitter chip and the receiver chip are both provided with the through silicon vias, the isolation capacitor chip is provided with the first electrode plate and the second electrode plate, any one of the transmitter chip and the receiver chip is connected with the first electrode plate through the through silicon vias, and the other one is connected with the second electrode plate through the through silicon vias.
In the embodiment of the application, when the transmitter chip or the receiver chip is provided with the through silicon vias, the isolation capacitor chip is provided with the second electrode plate, one of the transmitter chip and the receiver chip without the through silicon vias is provided with the first electrode plate on the metal layer on the top layer, one of the transmitter chip and the receiver chip with the through silicon vias is connected with the second electrode plate through the through silicon vias, and the other is connected with one end of the isolation capacitor chip without the electrode plate through the first electrode plate.
Through the technical scheme, the isolation capacitor chip, the transmitter chip and the receiver chip are respectively prepared, and the transmitter chip and/or the receiver chip are/is provided with the through silicon vias; and respectively bonding the transmitter chip and the receiver chip with the isolation capacitor chip to obtain a capacitor isolator. Through the separation manufacturing of the isolation capacitor chip, the transmitter chip and the receiver chip in the capacitor isolator, the separated chips are integrated together in a bonding mode, so that when the size of the isolator is reduced, the size of the transmitter chip and the size of the receiver chip can be reduced, the thickness of an intermetallic medium can be ensured, the voltage resistance of the capacitor is not limited by the thickness of a metal interconnection layer at the rear end of an integrated circuit, the voltage resistance of the capacitor is improved, and larger mechanical stress on a silicon substrate in the deposition process of the intermetallic insulating layer can be avoided, the risks of bending or fragmentation of the substrate and failure of a device are reduced, and the reliability of the device is improved. By converting the traditional two-dimensional integrated circuit into the three-dimensional integrated circuit, the area rate utilization rate of the chip is improved, better circuit connection is provided, the risk of failure of the device caused by stress is reduced, the reliability of the device is improved, and the manufacturing cost is reduced.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 schematically illustrates a flow chart of a method of fabricating a capacitive isolator according to an embodiment of the application;
FIG. 2 schematically illustrates a through silicon via process flow diagram according to an embodiment of the application;
FIG. 3 schematically illustrates a schematic diagram of a CMOS process flow in accordance with an embodiment of the application;
FIG. 4 schematically illustrates a schematic flow diagram 1 of a through-silicon-via CMOS back-end-of-line process in accordance with an embodiment of the application;
Fig. 5 schematically illustrates a CMOS back-end-of-line process flow diagram 2 with through silicon vias according to an embodiment of the application;
fig. 6 schematically illustrates a CMOS back-end-of-line process flow diagram 1 without through silicon vias, in accordance with an embodiment of the application;
fig. 7 schematically illustrates a CMOS back-end-of-line process flow diagram 2 without through silicon vias, in accordance with an embodiment of the application;
Fig. 8 schematically illustrates a CMOS back-end-of-line process flow diagram 3 without through silicon vias, in accordance with an embodiment of the application;
FIG. 9 schematically illustrates a process flow diagram of an isolated capacitor chip in accordance with an embodiment of the present application;
FIG. 10 schematically illustrates another isolation capacitor chip schematic according to an embodiment of the application;
FIG. 11 schematically illustrates a capacitive isolator according to an embodiment of the application;
fig. 12 schematically illustrates another capacitive isolator according to an embodiment of the application.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present application, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
Referring to fig. 1, fig. 1 schematically shows a flow chart of a method for manufacturing a capacitive isolator according to an embodiment of the application. The embodiment provides a preparation method of a capacitor isolator, which is based on a three-dimensional Silicon Via (TSV) technology, and bonds a circuit module and a capacitor module separated in the capacitor isolator together, so that the voltage resistance of the capacitor is not limited by the thickness of a metal interconnection layer at the rear end of an integrated circuit, and the problem of failure of a bottom device caused by an excessively thick dielectric layer is not required to be considered. The preparation method of the capacitor isolator comprises the following steps:
Step 210: preparing an isolation capacitor chip, a transmitter chip and a receiver chip respectively, wherein the transmitter chip and/or the receiver chip are/is provided with a through silicon via;
In this embodiment, the main structure of the capacitive isolator is a parallel plate capacitor with upper and lower plates as metal layers, and an insulating material with silicon dioxide as a main dielectric medium is filled between the two plates, and the capacitive isolator includes two separate circuit modules besides the capacitor: the transmitter chip and the receiver chip can be prepared separately. At least one of the transmitter chip and the receiver chip is provided with a through silicon via, namely the transmitter chip or the receiver chip is provided with the through silicon via, or the transmitter chip and the receiver chip are simultaneously provided with the through silicon via.
The through silicon vias are through silicon vias prepared by adopting a TSV technology, wherein vertical through holes are manufactured between chips and between wafers, and the through silicon vias are conductive through filling of conductive substances such as copper, tungsten, polysilicon and the like. This technology is a vertical electrical interconnection technology, which is one of the key technologies for implementing 3D advanced packaging. Because the through silicon vias can provide shorter electrical connection paths, the traditional two-dimensional integrated circuit can be converted into a three-dimensional integrated circuit, the area rate utilization rate of the chip is improved, and the device performance is improved.
In some embodiments, in the case of providing through silicon vias in a transmitter chip or receiver chip, one of the receiver chip or transmitter chip is fabricated using TSVs, the steps of preparing the transmitter chip or preparing the receiver chip are the same, comprising the steps of:
Firstly, preparing a silicon substrate, and manufacturing a silicon through hole on the silicon substrate by adopting a silicon through hole process to obtain the silicon substrate with the silicon through hole;
In this embodiment, referring to fig. 2, fig. 2 schematically illustrates a process flow of a through silicon via according to an embodiment of the present application, a through silicon via may be etched on a silicon substrate, then an insulating layer is deposited by using a Chemical vapor deposition (Chemical VaporDeposition, CVD) or a thermal oxidation process, and then copper is filled in the through silicon via by using a physical vapor deposition (Physical Vapor Deposition, PVD ) process, so as to obtain a silicon substrate with a through silicon via.
Then, on the silicon substrate with the through silicon via, a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) manufacturing process is adopted to manufacture a CMOS device;
In this embodiment, please refer to fig. 3, fig. 3 schematically illustrates a CMOS process flow diagram according to an embodiment of the present application. The CMOS device manufactured by the CMOS manufacturing process comprises the following steps: shallow Trench Isolation (STI) is formed on a substrate with through silicon vias, then ions are implanted between the shallow trench isolation to form P/N wells, gate oxide is formed through thermal oxidation, a polysilicon gate and a side wall are formed, finally an active region is formed through ion implantation, and finally the CMOS device manufacturing is completed.
Then, a back-end interconnection line is manufactured above the CMOS device by adopting a CMOS back-end process, and a first initial chip is obtained;
In this embodiment, the back-end interconnect is fabricated for connection to an external chip, please refer to fig. 4-5, fig. 4 schematically showing a CMOS back-end process flow diagram 1 with through silicon vias according to an embodiment of the present application; fig. 5 schematically illustrates a CMOS back-end-of-line process flow diagram 2 with through silicon vias according to an embodiment of the application. Specifically, the CMOS back-end process manufacturing process includes the following steps:
depositing an interlayer medium above the CMOS device, and manufacturing a contact hole on the interlayer medium, wherein the contact hole is used for being connected with the CMOS device;
in this embodiment, an interlayer dielectric is deposited over the CMOS device and contact holes are etched and filled with metal tungsten, which are used to connect the source, gate, drain, substrate, etc. of the CMOS device. And in the case of a through silicon via, the contact hole is connected with the through silicon via.
A second step of depositing an inter-metal insulating layer above the interlayer dielectric and manufacturing a first metal layer on the inter-metal insulating layer;
In this embodiment, after the contact hole is made, an inter-metal insulating layer is deposited over the interlayer dielectric and the first metal layer is etched, and the first metal layer is filled with metallic copper.
Thirdly, depositing an intermetallic insulating layer above the current metal layer, and sequentially manufacturing a through hole and a metal layer on the newly deposited intermetallic insulating layer, wherein the metal layer is positioned above the through hole; this step is repeated a plurality of times to form a plurality of metal layers to obtain the back-end interconnect.
In this embodiment, after the first metal layer is obtained, an intermetallic insulating layer is deposited over the first metal layer, the first through hole and the second metal layer are etched, metal copper is used to fill the first through hole and the second metal layer, the current metal layer is the second metal layer, then the intermetallic insulating layer is deposited over the second metal layer, corresponding through holes and metal layers are manufactured according to the process of manufacturing the first through hole and the second metal layer, after a plurality of times of circulation, the nth metal layer is completed, and finally the rear-end interconnection line is obtained.
And finally, carrying out wafer thinning treatment on the first initial chip to obtain a transmitter chip or a receiver chip.
Through the silicon through hole technology on the silicon substrate, the area rate utilization rate of the transmitter chip or the receiver chip is improved, and the device performance is improved.
In some embodiments, in the case that no through silicon vias are provided in the transmitter chip or the receiver chip, the steps of preparing the transmitter chip or preparing the receiver chip are the same, please refer to fig. 6-8, fig. 6 schematically illustrates a CMOS back-end process flow diagram 1 without through silicon vias according to an embodiment of the present application, fig. 7 schematically illustrates a CMOS back-end process flow diagram 2 without through silicon vias according to an embodiment of the present application, and fig. 8 schematically illustrates a CMOS back-end process flow diagram 3 without through silicon vias according to an embodiment of the present application. The method specifically comprises the following steps:
firstly, preparing a silicon substrate, and manufacturing a CMOS device on the silicon substrate by adopting a CMOS manufacturing process;
in this embodiment, the process of fabricating the CMOS device by using the CMOS fabrication process is the same as the process of fabricating the through silicon via in the transmitter chip or the receiver chip, and will not be described herein.
And then, manufacturing a back-end interconnection line above the CMOS device by adopting a CMOS back-end process, and manufacturing a first electrode plate on a metal layer on the top layer of the back-end interconnection line to obtain a transmitter chip or a receiver chip.
In this embodiment, the fabrication process of fabricating the back-end interconnect above the CMOS device by using the CMOS back-end process is the same as that in the case of providing the through-silicon via in the transmitter chip or the receiver chip, and will not be described herein again. Since the back-end interconnect includes multiple metal layers, after the back-end interconnect is obtained, the first electrode plate may be disposed on the metal layer on the topmost layer, so that the transmitter chip or the receiver chip includes the first electrode plate.
It should be noted that, in the implementation, the first mode may be that one of the receiver chip or the transmitter chip is manufactured by using the TSV, and the first electrode plate is manufactured on top of the other receiver chip or the transmitter chip, so that the process cost for forming the TSV can be reduced. The second mode can be that the receiver chip and the transmitter chip are manufactured by adopting TSVs, so that the receiver chip and the transmitter chip can be formed simultaneously in the same process flow, the TSV compatibility is better, and the process flow is simplified.
In some embodiments, where the transmitter chip and the receiver chip are both provided with through silicon vias, preparing an isolation capacitor chip includes: preparing a glass substrate, and respectively manufacturing electrode plates on the upper surface and the lower surface of the glass substrate to form a first electrode plate and a second electrode plate so as to obtain the isolated capacitor chip.
In this embodiment, referring to fig. 10, fig. 10 schematically illustrates another isolated capacitor chip according to an embodiment of the application. A glass (SiO 2) substrate is prepared, and a first electrode plate and a second electrode plate are respectively formed on the upper surface and the lower surface of the glass substrate by etching.
Accordingly, in the case where the transmitter chip or the receiver chip is provided with a through silicon via, preparing an isolation capacitor chip includes: preparing a glass substrate, manufacturing an electrode plate on any one of the upper surface and the lower surface of the glass substrate, and forming a second electrode plate to obtain the isolated capacitor chip.
In this embodiment, please refer to fig. 9, fig. 9 schematically illustrates a manufacturing flow chart of an isolation capacitor chip according to an embodiment of the application. In the case where one of the transmitter chip and the receiver chip is provided with a through-silicon via, the other one is provided with the first electrode plate on the metal layer of the top layer, so that the electrode plate is only fabricated on one side when the capacitor chip is fabricated.
After the transmitter chip, the receiver chip and the isolation capacitor are manufactured respectively, the transmitter chip, the receiver chip and the isolation capacitor can be connected in a bonding mode to obtain the capacitor isolator.
Step 220: and under the condition that the transmitter chip or the receiver chip is provided with the through silicon vias, bonding one of the transmitter chip and the receiver chip with the through silicon vias with the isolation capacitor chip through the through silicon vias, and bonding the other with the isolation capacitor chip through a metal layer on the top layer of the other to obtain the capacitor isolator.
In some embodiments, in a case that the transmitter chip or the receiver chip is provided with a through silicon via, bonding one of the transmitter chip and the receiver chip having the through silicon via with the isolation capacitor chip, and bonding the other with the isolation capacitor chip through a metal layer on a top layer thereof to obtain a capacitor isolator, including the following steps:
Firstly, respectively arranging the transmitter chip and the receiver chip on two sides of the isolation capacitor chip; wherein a back-end interconnect line of one of the transmitter chip and the receiver chip having a through-silicon via is distant from the isolation capacitance chip, and a back-end interconnect line of the other is close to the isolation capacitance chip;
And then, bonding one of the transmitter chip and the receiver chip with the through silicon via with the second electrode plate on the isolation capacitor chip, and bonding the other with one end of the isolation capacitor chip, which is not provided with the electrode plate, through the first electrode plate on the metal layer of the top layer of the second electrode plate, so as to obtain the capacitor isolator.
In this embodiment, one of the transmitter chip and the receiver chip has a through silicon via, and in the case that the other has no through silicon via, by bonding, one of the through silicon vias is connected to the second electrode plate of the isolation capacitor chip through the through silicon via, and the first electrode plate of the other is connected to one end of the isolation capacitor chip, which has no electrode plate, to obtain the capacitor isolator.
Through set up the through-silicon via at transmitter chip or receiver chip, one is through-silicon via bonding, and another is through first electrode plate bonding for the capacitive isolator is three-dimensional integrated circuit, provides better circuit connection, has improved chip area rate utilization, reduces the risk that stress causes the device to become invalid, improves the device reliability, compares the condition that both set up the through-silicon via, and the technology cost of the TSV of this scheme is lower.
Step 230: and under the condition that the transmitter chip and the receiver chip are provided with through silicon vias, bonding the transmitter chip and the receiver chip with the isolation capacitor chip through the through silicon vias respectively to obtain the capacitor isolator.
In some embodiments, in a case where the transmitter chip and the receiver chip are both provided with through silicon vias, the bonding the transmitter chip and the receiver chip with the isolation capacitor chip through the through silicon vias respectively, to obtain a capacitor isolator includes the following steps:
Firstly, respectively arranging the transmitter chip and the receiver chip on two sides of the isolation capacitor chip; wherein the rear end interconnection lines of the transmitter chip and the receiver chip are far away from the isolation capacitor chip;
And then, bonding any one of the transmitter chip and the receiver chip with a first electrode plate on the isolation capacitor chip through a silicon through hole, and bonding the other one with a second electrode plate on the isolation capacitor chip through the silicon through hole to obtain the capacitor isolator.
In this embodiment, the transmitter chip and the receiver chip each include a through silicon via, and may be connected to the isolation capacitor chip through the through silicon via, and the rear-end interconnection lines of the transmitter chip and the receiver chip are used for external connection.
Through the transmitter chip and the receiver chip are provided with the through silicon holes, the through silicon holes are bonded with the isolation capacitor chip, so that the capacitor isolator is a three-dimensional integrated circuit, better circuit connection is provided, the area rate utilization rate of the chip is improved, the risk of failure of a device caused by stress is reduced, the reliability of the device is improved, and the manufacturing cost is reduced.
In the implementation process, the isolation capacitor chip, the transmitter chip and the receiver chip are respectively prepared, and the transmitter chip and/or the receiver chip are/is provided with a through silicon via; and respectively bonding the transmitter chip and the receiver chip with the isolation capacitor chip to obtain a capacitor isolator. Through the separation manufacturing of the isolation capacitor chip, the transmitter chip and the receiver chip in the capacitor isolator, the separated chips are integrated together in a bonding mode, so that when the size of the isolator is reduced, the size of the transmitter chip and the size of the receiver chip can be reduced, the thickness of an intermetallic medium can be ensured, the voltage resistance of the capacitor is not limited by the thickness of a metal interconnection layer at the rear end of an integrated circuit, the voltage resistance of the capacitor is improved, and larger mechanical stress on a silicon substrate in the deposition process of the intermetallic insulating layer can be avoided, the risks of bending or fragmentation of the substrate and failure of a device are reduced, and the reliability of the device is improved. By converting the traditional two-dimensional integrated circuit into the three-dimensional integrated circuit, the area rate utilization rate of the chip is improved, better circuit connection is provided, the risk of failure of the device caused by stress is reduced, the reliability of the device is improved, and the manufacturing cost is reduced.
The embodiment provides a capacitor isolator, which is manufactured by adopting the manufacturing method of the capacitor isolator, and comprises the following steps: the device comprises an isolation capacitor chip, a transmitter chip and a receiver chip, wherein the transmitter chip and the receiver chip are respectively positioned at two sides of the isolation capacitor chip; in the case that the transmitter chip or the receiver chip is provided with a through silicon via, one of the transmitter chip and the receiver chip having the through silicon via is connected with the isolation capacitor chip, and the other is connected with the isolation capacitor chip through a metal layer on the top layer thereof; and under the condition that the transmitter chip and the receiver chip are both provided with through silicon vias, the transmitter chip and the receiver chip are respectively connected with the isolation capacitor chip through the through silicon vias.
In this embodiment, the transmitter chip and the receiver chip are respectively connected to the isolation capacitor chip by bonding.
In the implementation process, the isolation capacitor chip, the transmitter chip and the receiver chip are integrated together, so that the traditional two-dimensional integrated circuit can be converted into the three-dimensional integrated circuit, the area rate utilization rate of the chip is improved, better circuit connection is provided, the risk of failure of a stress-induced device is reduced, the reliability of the device is improved, and the manufacturing cost is reduced.
In some embodiments, in the case that the transmitter chip or the receiver chip is provided with a through silicon via, the isolation capacitor chip is provided with a second electrode plate, one of the transmitter chip and the receiver chip without the through silicon via is provided with a first electrode plate on a metal layer on a top layer thereof, one of the transmitter chip and the receiver chip with the through silicon via is connected with the second electrode plate on the isolation capacitor chip, and the other one is connected with one end of the isolation capacitor chip without the electrode plate via the first electrode plate on the metal layer on the top layer thereof.
In this embodiment, please refer to fig. 12, fig. 12 schematically illustrates another capacitive isolator according to an embodiment of the application. One of the transmitter chip and the receiver chip is provided with a through silicon hole, and under the condition that the other one is not provided with the through silicon hole, the one with the through silicon hole is connected with the second electrode plate of the isolation capacitor chip through the through silicon hole, and the first electrode plate of the other one is connected with one end of the isolation capacitor chip without the electrode plate, so that the capacitor isolator is obtained.
Through set up the silicon through-hole at transmitter chip or receiver chip for the capacitive isolator is three-dimensional integrated circuit, provides more excellent circuit connection, has improved chip area rate utilization, reduces stress and causes the risk of device inefficacy, improves the device reliability, compares the two circumstances that set up the silicon through-hole, and the technology cost of TSV of this scheme is lower.
In some embodiments, in a case where the transmitter chip and the receiver chip are both provided with through silicon vias, a first electrode plate and a second electrode plate are provided on the isolation capacitor chip, any one of the transmitter chip and the receiver chip is connected with the first electrode plate through the through silicon vias, and the other is connected with the second electrode plate through the through silicon vias.
In this embodiment, please refer to fig. 11, fig. 11 schematically illustrates a capacitive isolator according to an embodiment of the present application. The transmitter chip and the receiver chip both comprise through silicon vias, and can be connected with the isolation capacitor chip through the through silicon vias, and rear-end interconnection lines of the transmitter chip and the receiver chip are used for being connected with the outside.
Through the silicon through holes are formed in the transmitter chip and the receiver chip, the capacitor isolator is a three-dimensional integrated circuit, better circuit connection is provided, the area rate utilization rate of the chip is improved, the risk of failure of the device caused by stress is reduced, the reliability of the device is improved, and the manufacturing cost is reduced.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (11)
1. A method of making a capacitive separator, comprising:
Preparing an isolation capacitor chip, a transmitter chip and a receiver chip respectively, wherein the transmitter chip and/or the receiver chip are/is provided with a through silicon via;
Under the condition that the transmitter chip or the receiver chip is provided with a through silicon via, bonding one of the transmitter chip and the receiver chip with the through silicon via with the isolation capacitor chip, and bonding the other with the isolation capacitor chip through a metal layer on the top layer of the other to obtain a capacitor isolator;
And under the condition that the transmitter chip and the receiver chip are provided with through silicon vias, bonding the transmitter chip and the receiver chip with the isolation capacitor chip through the through silicon vias respectively to obtain the capacitor isolator.
2. The method of manufacturing a capacitive isolator as claimed in claim 1, wherein manufacturing a transmitter chip or manufacturing a receiver chip includes:
Preparing a silicon substrate, and manufacturing a silicon through hole on the silicon substrate by adopting a silicon through hole process to obtain the silicon substrate with the silicon through hole;
on the silicon substrate with the through silicon via, a CMOS manufacturing process is adopted to manufacture a CMOS device,
A back-end interconnection line is manufactured above the CMOS device by adopting a CMOS back-end process, and a first initial chip is obtained;
And carrying out wafer thinning treatment on the first initial chip to obtain a transmitter chip or a receiver chip.
3. The method of manufacturing a capacitive isolator as claimed in claim 1, wherein manufacturing a transmitter chip or manufacturing a receiver chip includes:
preparing a silicon substrate, and manufacturing a CMOS device on the silicon substrate by adopting a CMOS manufacturing process;
And manufacturing a back-end interconnection line above the CMOS device by adopting a CMOS back-end process, and manufacturing a first electrode plate on a metal layer on the top layer of the back-end interconnection line to obtain a transmitter chip or a receiver chip.
4. The method of manufacturing a capacitive isolator according to claim 1, wherein, in a case where the transmitter chip and the receiver chip are each provided with a through silicon via, manufacturing an isolated capacitive chip includes:
preparing a glass substrate, and respectively manufacturing electrode plates on the upper surface and the lower surface of the glass substrate to form a first electrode plate and a second electrode plate so as to obtain the isolated capacitor chip.
5. A method of manufacturing a capacitive isolator as claimed in claim 3, wherein, in the case where the transmitter chip or the receiver chip is provided with a through silicon via, manufacturing an isolated capacitive chip includes:
preparing a glass substrate, manufacturing an electrode plate on any one of the upper surface and the lower surface of the glass substrate, and forming a second electrode plate to obtain the isolated capacitor chip.
6. The method for manufacturing a capacitive isolator according to claim 4, wherein bonding the transmitter chip and the receiver chip to the isolated capacitive chip through-silicon vias, respectively, to obtain the capacitive isolator comprises:
The transmitter chip and the receiver chip are respectively arranged at two sides of the isolation capacitor chip; wherein the rear end interconnection lines of the transmitter chip and the receiver chip are far away from the isolation capacitor chip;
and bonding any one of the transmitter chip and the receiver chip with a first electrode plate on the isolation capacitor chip through a silicon through hole, and bonding the other one with a second electrode plate on the isolation capacitor chip through the silicon through hole to obtain the capacitor isolator.
7. The method for manufacturing a capacitor isolator according to claim 5, wherein bonding one of the transmitter chip and the receiver chip having a through silicon via to the isolated capacitor chip and bonding the other to the isolated capacitor chip through a metal layer on a top layer thereof to obtain the capacitor isolator comprises:
The transmitter chip and the receiver chip are respectively arranged at two sides of the isolation capacitor chip; wherein a back-end interconnect line of one of the transmitter chip and the receiver chip having a through-silicon via is distant from the isolation capacitance chip, and a back-end interconnect line of the other is close to the isolation capacitance chip;
And bonding one of the transmitter chip and the receiver chip, which is provided with the through silicon via, with the second electrode plate on the isolation capacitor chip through the through silicon via, and bonding the other one of the transmitter chip and the receiver chip, which is not provided with the electrode plate, with one end of the isolation capacitor chip through the first electrode plate on the metal layer of the top layer of the second electrode plate, so as to obtain the capacitor isolator.
8. A method of fabricating a capacitive isolator as claimed in claim 2 or 3, wherein fabricating a back-end interconnect over the CMOS device using a CMOS back-end process comprises:
Depositing an interlayer medium above the CMOS device, and manufacturing a contact hole on the interlayer medium, wherein the contact hole is used for being connected with the CMOS device;
Depositing an inter-metal insulating layer above the interlayer dielectric, and manufacturing a first metal layer on the inter-metal insulating layer;
depositing an intermetallic insulating layer above the current metal layer, sequentially manufacturing a through hole and a metal layer on the newly deposited intermetallic insulating layer, wherein the metal layer is positioned above the through hole; this step is repeated a plurality of times to form a plurality of metal layers to obtain the back-end interconnect.
9. A capacitive separator manufactured by the manufacturing method of any one of claims 1 to 8, comprising: the device comprises an isolation capacitor chip, a transmitter chip and a receiver chip, wherein the transmitter chip and the receiver chip are respectively positioned at two sides of the isolation capacitor chip;
in the case that the transmitter chip or the receiver chip is provided with a through silicon via, one of the transmitter chip and the receiver chip having the through silicon via is connected with the isolation capacitor chip, and the other is connected with the isolation capacitor chip through a metal layer on the top layer thereof;
And under the condition that the transmitter chip and the receiver chip are both provided with through silicon vias, the transmitter chip and the receiver chip are respectively connected with the isolation capacitor chip through the through silicon vias.
10. The capacitive isolator of claim 9, wherein in the case where the transmitter chip and the receiver chip are each provided with a through silicon via, a first electrode plate and a second electrode plate are provided on the isolated capacitive chip, either one of the transmitter chip and the receiver chip is connected to the first electrode plate through the through silicon via, and the other is connected to the second electrode plate through the through silicon via.
11. The capacitive isolator according to claim 9, wherein in the case where the transmitter chip or the receiver chip is provided with a through silicon via, a second electrode plate is provided on the isolated capacitive chip, one of the transmitter chip and the receiver chip having no through silicon via is provided with a first electrode plate on a metal layer on a top layer thereof, one of the transmitter chip and the receiver chip having a through silicon via is connected to the second electrode plate through the through silicon via, and the other is connected to an end of the isolated capacitive chip having no electrode plate provided thereon through the first electrode plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410706029.5A CN118315291A (en) | 2024-06-03 | 2024-06-03 | Capacitive isolator and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410706029.5A CN118315291A (en) | 2024-06-03 | 2024-06-03 | Capacitive isolator and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118315291A true CN118315291A (en) | 2024-07-09 |
Family
ID=91729418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410706029.5A Pending CN118315291A (en) | 2024-06-03 | 2024-06-03 | Capacitive isolator and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118315291A (en) |
-
2024
- 2024-06-03 CN CN202410706029.5A patent/CN118315291A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5340923B2 (en) | Semiconductor integrated circuit device having high-Q wafer backside capacitor (integrated circuit device and method of forming integrated circuit device) | |
| US9793340B2 (en) | Capacitor structure | |
| US8421238B2 (en) | Stacked semiconductor device with through via | |
| CN102420210B (en) | Device with through-silicon via (tsv) and method of forming the same | |
| US8987137B2 (en) | Method of fabrication of through-substrate vias | |
| US20100164062A1 (en) | Method of manufacturing through-silicon-via and through-silicon-via structure | |
| CN103545275A (en) | Through silicon via package structure and forming method | |
| CN105514093A (en) | Semiconductor capacitor based on through-silicon via technology and manufacturing method and packaging structure thereof | |
| CN101789390A (en) | Manufacturing method of silicon through hole and silicon through hole structure | |
| CN103378057B (en) | Semiconductor chip with and forming method thereof | |
| CN115497936A (en) | Integrated circuit and method of construction thereof | |
| CN111508963A (en) | Peripheral circuit, three-dimensional memory and preparation method thereof | |
| CN109712953B (en) | Manufacturing method of semiconductor device and semiconductor device | |
| US11211348B2 (en) | First wafer, fabricating method thereof and wafer stack | |
| TW202211486A (en) | On-chip capacitor structure in semiconductor element | |
| KR20150019089A (en) | Semiconductor devices having through vias and methods for fabricating the same | |
| US20220336356A1 (en) | Semiconductor Device and Method of Manufacture | |
| CN118315291A (en) | Capacitive isolator and preparation method thereof | |
| CN102751172B (en) | Integrated passive device and manufacture method thereof | |
| CN112542378B (en) | Method for manufacturing semiconductor device and semiconductor device | |
| US20120049349A1 (en) | Semiconductor chips and methods of forming the same | |
| CN115312493A (en) | Semiconductor structure and forming method thereof | |
| EP2793254B1 (en) | Semiconductor device with through-substrate via of enhanced conductivity and corresponding fabrication method | |
| US20070041680A1 (en) | Process for assembling passive and active components and corresponding integrated circuit | |
| US11488840B2 (en) | Wafer-to-wafer interconnection structure and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication |