CN118311405A - Wafer-level chip failure detection method - Google Patents
Wafer-level chip failure detection method Download PDFInfo
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- CN118311405A CN118311405A CN202410376644.4A CN202410376644A CN118311405A CN 118311405 A CN118311405 A CN 118311405A CN 202410376644 A CN202410376644 A CN 202410376644A CN 118311405 A CN118311405 A CN 118311405A
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- 238000001514 detection method Methods 0.000 title claims abstract description 26
- 230000032683 aging Effects 0.000 claims abstract description 50
- 238000012360 testing method Methods 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims description 18
- 238000009826 distribution Methods 0.000 claims description 11
- 239000000523 sample Substances 0.000 claims description 8
- 238000001931 thermography Methods 0.000 claims description 7
- 230000035882 stress Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 claims description 5
- 238000003331 infrared imaging Methods 0.000 claims description 5
- 238000003466 welding Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 claims description 3
- 238000012216 screening Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 4
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Abstract
A wafer-level chip failure detection method belongs to the technical field of wafer-level burn-in test, and comprises the following steps: determining that the aging electrical parameter data belong to a first range according to the aging electrical parameter data of each chip of the wafer; determining that the temperature data belong to a second range according to the temperature data of each chip of the wafer; judging the temperature data and/or the aging electrical parameter data, and determining the chip which is not failed; the invention has the beneficial effects that the chips with potential failure risks are further screened out on the premise of not increasing the aging test duration, and the screening rate of the failed chips is improved so as to improve the quality and reliability of subsequent packaged finished products.
Description
Technical Field
The invention relates to the technical field of wafer-level burn-in testing, in particular to a wafer-level chip failure detection method.
Background
In vehicle-scale SiC power chip products, wafer-level burn-in testing (WAFER LEVEL burn in test) is often used to screen out potentially failure-risk chips due to material defects of the SiC itself and process anomalies during chip fabrication. The wafer level burn-in test is critical to detect early failure (infant mortality) of the SiC chip, thereby improving reliability of subsequent package components, but since the wafer level burn-in test itself is a high stress accelerated electrical test, the test time cannot be too long (typically less than 12 hours are required) to avoid damaging the life of the chip.
Due to the limitation of the wafer level burn-in test duration, a portion of potentially failing chips may still pass the wafer level burn-in electrical test, which may pose a risk to the reliability of the subsequent package assembly product. Therefore, a new method is needed to further screen out SiC chips with potential failure risk without damaging the service life of the chips, and the screening rate of the failed chips is improved, so as to improve the reliability of subsequent SiC packaging finished products.
In the prior art, the method for performing wafer-level burn-in test on a semiconductor device comprises the following steps: establishing electrical connection and performing initial test by the pressure welding of the semiconductor devices on the wafer contacted with the test probes; applying voltage stress to each semiconductor device on the wafer through a test probe according to the set burn-in test rule, and respectively performing a monitoring test; judging whether the measured relevant electrical parameters of each semiconductor device on the wafer accord with the set corresponding aging judgment standards, and determining that the accordant wafer is good and the aging grade is the judgment standard; and determining that the non-conforming wafer fails. The application performs the aging test on the wafer by a plurality of aging test rules and standards, and has long test duration, low efficiency and influences the service life of the chip.
Disclosure of Invention
In order to solve the technical problems, the invention provides a wafer-level chip failure detection method, which can further screen out chips with potential failure risks on the premise of not increasing the aging test duration, and can improve the screening rate of failed chips so as to improve the quality and reliability of subsequent packaged finished products.
In order to achieve the above purpose, the technical scheme adopted by the invention for solving the technical problems is as follows: the wafer-level chip failure detection method comprises the following steps:
Determining that the aging electrical parameter data belong to a first range according to the aging electrical parameter data of each chip of the wafer;
Determining that the temperature data belong to a second range according to the temperature data of each chip of the wafer;
and judging the temperature data and/or the aging electrical parameter data, and determining the chip which is not failed.
The method for determining the aging electrical parameter data comprises the following steps:
establishing electrical connection between the test probes and the pressure welding points of the chips on the wafer;
and applying voltage stress to each chip on the wafer through the test probe to determine the aging electrical parameter data.
And determining the test voltage of the aging electrical parameter data as the limit voltage of the device, wherein the test time is 6-12 hours.
The aging electrical parameters include turn-on voltage, on-resistance, reverse breakdown voltage, gate leakage current, and reverse leakage current.
The method for determining the temperature data of each chip of the wafer comprises the following steps: the temperature data is determined by detecting infrared radiant energy of the wafer.
And detecting infrared radiant energy on the surface of the wafer after the electric test is finished.
Infrared imaging detection instruments are used to detect infrared radiant energy at the wafer surface.
The specific method for determining the temperature data through the infrared radiant energy of the wafer comprises the following steps: and converting infrared radiant energy obtained by detection on the surface of the wafer into an electric signal, obtaining an infrared thermal imaging distribution diagram containing coordinate marks through a display screen, and deriving temperature data at each coordinate position.
The method for determining that the temperature data belongs to the second range comprises the following steps:
Determining an average value of the temperature data of each of the chips And standard deviation sigma;
Determining the highest temperature T max of each chip;
Determination of Wherein k is more than or equal to 2 and less than or equal to 4.
Wherein k has a value of 3.
The beneficial effects of the invention are as follows:
according to the method, the wafer-level aging electrical parameter test is carried out, the temperature distribution of the surfaces of all chips in the wafer is obtained by utilizing the thermal imaging principle, the surface temperature distribution data and the aging electrical parameter data result are combined with each other, and the failure risk of the corresponding chip is judged as long as one data is not met.
Drawings
The contents of the drawings and the marks in the drawings of the present specification are briefly described as follows:
FIG. 1 is a flow chart of a wafer level chip failure detection method of the present invention;
FIG. 2 is a flow chart of the specific detection method of FIG. 1;
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention, and the following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
In the prior art, the wafer level burn-in test is itself a high stress accelerated electrical test, so the test time cannot be too long (generally less than 12 hours are required) to avoid damaging the service life of the chip. Due to the limitation of the wafer level burn-in test duration, a portion of potentially failing chips may still pass the wafer level burn-in electrical test, which may pose a risk to the reliability of the subsequent package assembly product.
In order to solve the above technical problems, the present invention provides a wafer level chip failure detection method, as shown in fig. 1 and fig. 2, comprising the following steps:
step 1: and simultaneously applying an electrical test to each chip of the wafer to obtain aging electrical parameter data, and determining that the aging electrical parameter data belongs to a first range, wherein the first range refers to an aging electrical parameter data range meeting an aging judgment standard.
The specific operation method comprises the following steps: 1) Establishing electrical connection between the test probes and the pressure welding points of the chips on the wafer; 2) Applying voltage stress to each chip on the wafer through a test probe, wherein the test voltage is the limit voltage of the device, the test time is 6-12 hours, and related aging electrical parameter data including starting voltage, on-resistance, reverse breakdown voltage, gate leakage current and reverse leakage current are measured. And comparing the values of the parameters with the first range, and determining aging electrical parameter data in the first range.
Step 2: and determining that the temperature data belong to a second range according to the temperature data of each chip of the wafer.
The method for determining the temperature data of each chip of the wafer comprises the following steps: temperature data is determined by detecting infrared radiant energy of the wafer. The method comprises the following steps of 1) detecting infrared radiant energy on the surface of the wafer by using an infrared imaging detection instrument after electric test is finished, ensuring enough heat accumulation and measuring accuracy, wherein the infrared imaging detection instrument is non-contact measuring equipment and has the advantages of high sensitivity, comprehensive coverage range and the like, and the accuracy and precision of infrared radiant energy detection are further improved. 2) The infrared imaging detection instrument converts the detected infrared energy on the surface of the wafer into an electric signal, and then an infrared thermal imaging distribution diagram containing the coordinate marks is obtained through the display screen, so that the position of the chip containing the problem data can be intuitively obtained. 3) Temperature data at each coordinate position are derived, so that later failure judgment of the chip is facilitated.
The method for determining that the above temperature data belongs to the second range includes: determining an average value of temperature data of each chipAnd standard deviation sigma; determining the highest temperature T max of each chip; determination ofWherein, k is more than or equal to 2 and less than or equal to 4, and preferably, k is 3. If a chip fails in aging, the chip will be at a significantly higher temperature than other normal chips during electrical testing. The present invention employs the 3σ criterion to define the upper temperature limit of the chip. The 3 sigma criterion, also called the Laida criterion, is a mathematical principle that is based on a normal distribution concept. The 3 sigma principle refers to three times of standard deviation, i.e. from the average value of normal distribution #, of) Initially, a range of 3 standard deviations (σ) extends to both sides. The core idea of the 3σ principle is that in a normally distributed dataset, the data points fall onTo the point ofThe probability in the range between is approximately 99.7%, i.e., 99.7% of the data points are all within 3σ. If it isIndicating that the chip temperature is not exceeded.
Of course, the order of obtaining the aging electrical parameter data and the temperature data is not particularly specified, and thus, the order of the above steps 1 and 2 is interchangeable.
Step 3: and judging the temperature data and/or the aging electrical parameter data, and determining the chip which is not failed. And combining the obtained temperature data with the aging electrical parameter data to judge the chip with failure risk.
The specific judging method comprises the following steps:
judging the highest temperature T max and the highest temperature of each chip In the relation of (1)And the aging electrical parameter data accords with the aging judgment standard, the corresponding chip is determined to not fail, namely, when the temperature of the corresponding chip is judged not to exceed the limit) Then, according to the coordinate positions on the infrared thermal imaging distribution diagram, the aging electrical parameter data of the chip corresponding to the coordinate positions are found out, and if the aging electrical parameter data meets the aging judgment standard, the corresponding chip is determined to not fail; or after judging that the aging electrical parameter data of the corresponding chip accords with the aging judgment standard, finding out the temperature data of the corresponding coordinate position on the infrared thermal imaging distribution diagram according to the coordinate position of the corresponding chip, if the temperature is not out of limit) It is determined that the corresponding chip has not failed.
If it isOr the aging electrical parameter data does not meet the aging judgment standard, orAnd determining that the corresponding chip fails if the aging electrical parameter data does not meet the aging judgment standard.
The aging judgment standard is that the aging electrical parameter value of the electrical test exceeds the parameter range specified by the product.
In summary, the invention utilizes the thermal imaging principle to obtain the temperature distribution of the surfaces of chips in the wafer while carrying out the wafer-level aging electrical parameter test, and combines the surface temperature distribution data and the aging electrical parameter data results with each other, so long as one of the data is not satisfied, the corresponding chip is judged to have failure risk.
The foregoing is provided by way of illustration of the principles of the present invention, and is not intended to be limited to the specific constructions and applications illustrated herein, but rather to all modifications and equivalents which may be utilized as fall within the scope of the invention as defined in the claims.
Claims (10)
1. The wafer-level chip failure detection method is characterized by comprising the following steps of:
Determining that the aging electrical parameter data belong to a first range according to the aging electrical parameter data of each chip of the wafer;
Determining that the temperature data belong to a second range according to the temperature data of each chip of the wafer;
and judging the temperature data and/or the aging electrical parameter data, and determining the chip which is not failed.
2. The wafer-level chip failure detection method according to claim 1, wherein: the method for determining the aging electrical parameter data comprises the following steps:
establishing electrical connection between the test probes and the pressure welding points of the chips on the wafer;
and applying voltage stress to each chip on the wafer through the test probe to determine the aging electrical parameter data.
3. The wafer-level chip failure detection method according to claim 1, wherein: and determining the test voltage of the aging electrical parameter data as the limit voltage of the device, wherein the test time is 6-12 hours.
4. The wafer-level chip failure detection method according to claim 1, wherein: the aging electrical parameters include turn-on voltage, on-resistance, reverse breakdown voltage, gate leakage current, and reverse leakage current.
5. The wafer-level chip failure detection method according to claim 1, wherein: the method for determining the temperature data of each chip of the wafer comprises the following steps: the temperature data is determined by detecting infrared radiant energy of the wafer.
6. The wafer-level chip failure detection method according to claim 5, wherein: and detecting infrared radiant energy on the surface of the wafer after the electric test is finished.
7. The wafer-level chip failure detection method according to claim 5, wherein: infrared imaging detection instruments are used to detect infrared radiant energy at the wafer surface.
8. The wafer-level chip failure detection method according to claim 5, wherein: the specific method for determining the temperature data through the infrared radiant energy of the wafer comprises the following steps: and converting infrared radiant energy obtained by detection on the surface of the wafer into an electric signal, obtaining an infrared thermal imaging distribution diagram containing coordinate marks through a display screen, and deriving temperature data at each coordinate position.
9. The wafer-level chip failure detection method according to claim 1, wherein: the method for determining that the temperature data belongs to the second range comprises the following steps:
Determining an average value of the temperature data of each of the chips And standard deviation sigma;
Determining the highest temperature T max of each chip;
Determination of Wherein k is more than or equal to 2 and less than or equal to 4.
10. The wafer level chip failure detection method according to claim 9, wherein: wherein k has a value of 3.
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| CN202410376644.4A CN118311405A (en) | 2024-03-29 | 2024-03-29 | Wafer-level chip failure detection method |
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| CN202410376644.4A CN118311405A (en) | 2024-03-29 | 2024-03-29 | Wafer-level chip failure detection method |
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