CN118298761A

CN118298761A - Pixel circuit, detection method and display device

Info

Publication number: CN118298761A
Application number: CN202410584959.8A
Authority: CN
Inventors: 黄耀; 朱莉; 杨栋芳; 刘佳
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2024-05-11
Filing date: 2024-05-11
Publication date: 2024-07-05

Abstract

The embodiment of the disclosure provides a pixel circuit, a detection method and a display device, relates to the technical field of display, and is used for repairing the pixel circuit in time so as to reduce the preparation cost of the display device. The driving sub-circuit is configured to control conduction of the second node and the third node in response to the potential of the first node in a first phase; the first sub-circuit is configured to, in a first stage, transfer a first signal received at the first signal terminal to a node coupled to the first sub-circuit in response to a scan signal received at the at least one scan signal terminal; the detection sub-circuit is coupled with the other of the second node and the third node, the second scanning signal end and the data signal end; the detection sub-circuit is configured to transfer, in a first stage, a signal received at a node coupled to the detection sub-circuit to the data signal terminal in response to a second scan signal received at the second scan signal terminal, the pixel circuit being for use in a display panel.

Description

Pixel circuit, detection method and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel circuit, a detection method and a display device.

Background

With the development of display technology, display devices (such as mobile phones, notebook computers or tablet computers) are increasingly used in the life of people. Among them, an Organic Light-Emitting Diode (OLED) display device has the advantages of active Light emission, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-Light weight, etc., and thus is receiving attention.

Disclosure of Invention

An embodiment of the disclosure aims to provide a pixel circuit, a detection method and a display device, which are used for repairing the pixel circuit in time so as to reduce the preparation cost of the display device.

In order to achieve the above object, the embodiments of the present disclosure provide the following technical solutions:

In one aspect, a pixel circuit is provided. The pixel circuit includes a driving sub-circuit, a first sub-circuit, a data writing sub-circuit, and a detecting sub-circuit. The driving sub-circuit is coupled with the first node, the second node and the third node; the drive sub-circuit is configured to control conduction of the second node and the third node in response to a potential of a first node in the first phase; the first sub-circuit is coupled with one of the second node and the third node, a first signal terminal and at least one scanning signal terminal; the data writing sub-circuit is coupled with the first node, the first scanning signal end and the data signal end; the first sub-circuit is coupled with the first signal end and the scanning signal end; the first sub-circuit is also coupled with one of the second node and the third node; the first sub-circuit is configured to, in the first stage, transfer a first signal received at the first signal terminal to a first target node in response to a scan signal received at the scan signal terminal; wherein the first target node is a node coupled to the first sub-circuit of the second node and the third node; the detection sub-circuit is coupled with the second scanning signal end and the data signal end; the detection subcircuit is also coupled with the other of the second node and the third node; the detection subcircuit is configured to, in the first phase, pass signals received at a second target node to the data signal terminal in response to second scan signals received at a second scan signal terminal; wherein the second target node is a node of the second node and the third node coupled to the detection subcircuit.

In the pixel circuit, the first signal may be transferred to the data signal terminal through the first sub-circuit, the driving sub-circuit and the detecting sub-circuit. In this way, the driving sub-circuits can be detected by detecting the current at the data signal end to judge whether the driving sub-circuits are damaged or not and judge whether all the driving sub-circuits have differences or not, so that the pixel circuits are repaired in time, the influence on the working procedures after the pixel circuits is reduced, and the preparation cost of the display device is reduced.

In some embodiments, the detection subcircuit is coupled with the second node, and the first subcircuit includes a first reset subcircuit and a second light emitting subcircuit. The first reset sub-circuit is coupled with the first initialization signal end, the fourth node and the first reset signal end; the first reset sub-circuit is configured to, in the first phase, transfer a first initialization signal received at the first initialization signal terminal to a fourth node in response to a first reset signal received at the first reset signal terminal; wherein the fourth node is configured to be coupled to an anode of a light emitting device; the second light emitting subcircuit is coupled with the third node, the second light emitting signal terminal and the fourth node; the second light emitting sub-circuit is configured to, in the first phase, transfer the received first initialization signal at the fourth node to the third node in response to the second light emitting signal received at the second light emitting signal terminal; the drive sub-circuit is configured to pass, in the first phase, a received first initialization signal at the third node to the second node in response to a potential of the first node; the detection subcircuit is configured to, in the first phase, pass a first initialization signal received by the third node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

In some embodiments, the detection phase further comprises a second phase, and the pixel circuit further comprises a first light emitting sub-circuit. The first light emitting sub-circuit is coupled with the first voltage signal end, the first light emitting signal end and the second node; the first light emitting sub-circuit is configured to transfer, in the second phase, a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal; the detection subcircuit is further configured to, in the second phase, pass the first voltage signal received at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

In some embodiments, the detection subcircuit is coupled with the third node, the first subcircuit including a first light emitting subcircuit. The first light emitting sub-circuit is coupled with the first voltage signal end, the first light emitting signal end and the second node; the first light emitting sub-circuit is configured to transfer, in the first phase, a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal; the drive sub-circuit is configured to pass, in the first phase, a received first voltage signal at the second node to the third node in response to a potential of the first node; the detection subcircuit is configured to, in the first phase, pass a first voltage signal received at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

In some embodiments, the detection phase further comprises a second phase, the pixel circuit further comprising a first reset sub-circuit and a second light emitting sub-circuit. The first reset sub-circuit is coupled with the first initialization signal end, the fourth node and the first reset signal end; wherein the fourth node is configured to be coupled to an anode of a light emitting device; the first reset sub-circuit is configured to, in the second phase, transfer a first initialization signal received at the first initialization signal terminal to a fourth node in response to a first reset signal received at the first reset signal terminal; the second light emitting subcircuit is coupled with the third node, the second light emitting signal terminal and the fourth node; the second light emitting sub-circuit is configured to transfer, in the second phase, the first initialization signal received at the fourth node to the third node in response to the second light emitting signal received at the second light emitting signal terminal; the detection subcircuit is further configured to, in the second phase, pass the first initialization signal received at the third node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

In some embodiments, the detection subcircuit includes a first transistor. The first electrode of the first transistor is coupled to the data signal terminal, the second electrode is coupled to the other of the second node and the third node, and the control electrode is coupled to the second scan signal terminal.

In some embodiments, the drive subcircuit includes a second transistor. The first pole of the second transistor is coupled to the second node, the second pole is coupled to the third node, the first control pole is coupled to the first node, and the second control pole is coupled to the third node.

In some embodiments, the detection phase further comprises a third phase, and the pixel circuit further comprises a second reset sub-circuit. The second reset sub-circuit is coupled with a second initialization signal terminal, the first node and a second reset signal terminal; the second reset sub-circuit is configured to transmit, in the third stage, a second initialization signal received at the second initialization signal terminal to the first node in response to a second reset signal received at a second reset signal terminal; the data writing sub-circuit is configured to transfer the second initialization signal received at the first node to the data signal terminal in response to the first scan signal received at the first scan signal terminal in the third stage.

In another aspect, a method of detecting a pixel circuit is provided. The detection method is used for detecting the pixel circuit in any embodiment. The detection phase includes a first phase; in the first stage, a first sub-circuit transmits a first signal received at a first signal terminal to a node coupled to the first sub-circuit in response to a scan signal received at the at least one scan signal terminal; under control of a first node, the driving sub-circuit transfers a first signal received at a node coupled to the first sub-circuit to a node coupled to the detection sub-circuit; the detection sub-circuit transfers a first signal received at a node coupled to the detection sub-circuit to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

The detection method of the pixel circuit has the same structure and beneficial technical effects as those of the pixel circuit provided in some embodiments, and is not described herein.

In some embodiments, the detection subcircuit is coupled to the second node; in the first stage, the first reset sub-circuit transmits a first initialization signal received at a first initialization signal terminal to a fourth node in response to a first reset signal received at a first reset signal terminal, the second light emitting sub-circuit transmits the first initialization signal received at the fourth node to a third node in response to a second light emitting signal received at a second light emitting signal terminal, the driving sub-circuit transmits the first initialization signal received at the third node to the second node in response to a potential at the first node, and the detection sub-circuit transmits the first initialization signal at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

In some embodiments, the detection phase further comprises a second phase; in the second stage, the first light emitting sub-circuit transmits a first voltage signal received at a first voltage signal terminal to a second node in response to a first light emitting signal received at a first light emitting signal terminal, and the detection sub-circuit transmits a potential at the second node to a data signal terminal in response to a second scan signal received at a second scan signal terminal.

In some embodiments, the detection subcircuit is coupled to the third node; in the first stage, the first light emitting sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the first light emitting signal received at the first light emitting signal terminal, the driving sub-circuit transmits the first voltage signal received at the second node to the third node in response to the potential at the first node, and the detecting sub-circuit transmits the first voltage signal received at the third node to the data signal terminal in response to the second scanning signal received at the second scanning signal terminal.

In some embodiments, the detection phase further comprises a second phase; in the second stage, the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the fourth node in response to the first reset signal received at the first reset signal terminal, the second light-emitting sub-circuit transmits the potential at the fourth node to the third node in response to the second light-emitting signal received at the second light-emitting signal terminal, and the detection sub-circuit transmits the potential at the third node to the data signal terminal in response to the second scan signal received at the second scan signal terminal.

In some embodiments, the detection phase further comprises a third phase; in the third stage, the second reset sub-circuit transmits a second initialization signal received at a second initialization signal terminal to the first node in response to a second reset signal received at a second reset signal terminal; the data writing sub-circuit transfers the second initialization signal received at the first node to the data signal terminal in response to the first scan signal received at the first scan signal terminal.

In yet another aspect, a display device is provided. The display device includes a pixel circuit as in any one of the embodiments described above.

The display device has the same structure and beneficial technical effects as those of the pixel circuit provided in some embodiments described above, and will not be described in detail herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments;

FIG. 2 is another block diagram of a display device according to some embodiments;

FIG. 3 is a block diagram of a display device including a display panel according to some embodiments;

FIG. 4 is a block diagram of a display panel including a substrate and pixel circuits according to some embodiments;

FIG. 5 is a cross-sectional view taken along section line A-A of FIG. 4;

FIG. 6 is a block diagram of a pixel circuit according to some embodiments;

FIG. 7 is another block diagram of a pixel circuit according to some embodiments;

FIG. 8 is a block diagram of a pixel circuit including a transistor and a capacitor according to some embodiments;

FIG. 9 is another block diagram of a pixel circuit including a transistor and a capacitor according to some embodiments;

FIG. 10 is a timing diagram of a pixel circuit according to some embodiments;

FIG. 11 is another timing diagram of a pixel circuit according to some embodiments;

fig. 12 is a block diagram of a pixel circuit including transistors that are turned on or off according to some embodiments;

fig. 13 is another block diagram of a pixel circuit including transistors that are turned on or off according to some embodiments;

fig. 14 is a further block diagram of a pixel circuit including transistors that are turned on or off according to some embodiments;

fig. 15 is a further block diagram of a pixel circuit including transistors that are turned on or off according to some embodiments;

Fig. 16 is a further block diagram of a pixel circuit including transistors that are turned on or off according to some embodiments;

Fig. 17 is a further block diagram of a pixel circuit including transistors that are turned on or off according to some embodiments;

fig. 18 is yet another block diagram of a pixel circuit according to some embodiments.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments (some embodiments)", "exemplary embodiment (exemplary embodiments)", "example (example)", "specific example (some examples)", etc. are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. The term "coupled" is to be interpreted broadly, as referring to, for example, a fixed connection, a removable connection, or a combination thereof; can be directly connected or indirectly connected through an intermediate medium. The term "coupled" for example, indicates that two or more elements are in direct physical or electrical contact. The term "coupled" or "communicatively coupled (communicatively coupled)" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and includes the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

As used herein, the term "if" is optionally interpreted to mean "when … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if determined … …" or "if a [ stated condition or event ] is detected" is optionally interpreted to mean "upon determination … …" or "in response to determination … …" or "upon detection of a [ stated condition or event ]" or "in response to detection of a [ stated condition or event ], depending on the context.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

As used herein, "parallel", "perpendicular", "equal" includes the stated case as well as the case that approximates the stated case, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel may be, for example, a deviation within 5 °; "vertical" includes absolute vertical and near vertical, where the acceptable deviation range for near vertical may also be deviations within 5 °, for example. "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal, for example, is less than or equal to 5% of either of them within an acceptable deviation of approximately equal.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

In embodiments of the present disclosure, the capacitor may be a capacitive device fabricated separately by a process, such as by fabricating dedicated capacitive electrodes, each of which may be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), or the like. The capacitor may also be a parasitic capacitance between transistors, or may be implemented by the transistors themselves and other devices, lines, or may be implemented by using a parasitic capacitance between lines of the circuit itself.

In the circuit provided by the embodiment of the disclosure, the first node, the second node and the third node do not represent actually existing components, but represent junction points of related electrical connections in the circuit diagram, that is, the nodes are equivalent to the junction points of the related electrical connections in the circuit diagram.

The "low level" of the pixel circuit provided in the embodiments of the present disclosure refers to a level at which the operated transistor included therein can be made to be turned on, and correspondingly, the "high level" refers to a level at which the operated transistor included therein cannot be made to be turned on (i.e., the transistor is turned off).

The control of each transistor provided in embodiments of the present disclosure is the gate of the transistor, the first being one of the source and drain of the transistor and the second being the other of the source and drain of the transistor. Since the source and drain of a transistor may be symmetrical in structure, the source and drain thereof may be indistinguishable in structure, that is, the first and second poles of the transistor in embodiments of the present disclosure may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

As shown in fig. 1 and 2, some embodiments of the present disclosure provide a display device 1000, which display device 1000 may be any device that displays both motion (e.g., video) and stationary (e.g., still image) and text or images.

For example, the display device 1000 may be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a Personal Digital Assistant (PDA), a navigator, a wearable apparatus, an Augmented Reality (AR) apparatus, a Virtual Reality (VR) apparatus, an in-vehicle display, and an in-flight display.

In some examples, as shown in fig. 1, the display device 1000 may be a portable display product. For example, the display device 1000 may be a mobile phone as shown in fig. 1.

In still other examples, as shown in fig. 2, the display apparatus 1000 may be a wearable device. For example, the display device 1000 may be a wristwatch shown in fig. 2.

In some embodiments, as shown in fig. 3, the display device 1000 includes a display panel 100, a driving circuit board 200, a case 300, and a cover plate 400.

The display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B, wherein the light-emitting side 100A is a side of the display panel 100 capable of emitting light (an upper side of the display panel 100 in fig. 3), and the non-light-emitting side 100B is another side opposite to the light-emitting side 100A (a lower side of the display panel 100 in fig. 3).

The driving circuit board 200 is disposed at a non-light emitting side of the display panel 100 and connected to the display panel 100 to provide a light emitting signal to the display panel 100.

The case 300 may have a box-shaped structure with an opening, the display panel 100 and the driving circuit board 200 may be disposed in the case 300, and the cover plate 400 is disposed at the light emitting side of the display panel 100 and at the opening of the case 300.

As shown in fig. 3, the longitudinal section of the housing 300 may be, for example, U-shaped, the display panel 100 and the driving circuit board 200 are disposed in the housing 300, and the cover 400 is disposed at the opening of the housing 300.

The types of the display panel 100 include various types, and can be selected according to actual needs.

Illustratively, the display panel 100 may be: an Organic Light-Emitting Diode (OLED) display panel, a Quantum Dot LIGHT EMITTING Diode (QLED) display panel, an active matrix Organic Light-Emitting Diode (AMOLED) display panel, a Liquid crystal (Liquid CRYSTAL DISPLAY, LCD) display panel, a Micro Light-Emitting (Mini/Micro LIGHT EMITTING DISPLAY, MLED) display panel, or the like, the embodiments of the present disclosure are not particularly limited herein.

Some embodiments of the present disclosure will be schematically described below taking the above-described display panel 100 as an OLED display panel as an example.

In some embodiments, as shown in fig. 4 and 5, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

The material used for the substrate 10 may include a polymer resin or glass. Illustratively, the substrate 10 may be flexible, and the material used for the substrate 10 includes a polymer resin such as one of polyethersulfone (english: polyethersulfone, abbreviated as PES), polyarylate (english: polyaryate, abbreviated as PAR), polyetherimide (english: polyethylenimide, abbreviated as PEI), polyethylene naphthalate (english: polyethylene Naphthalate Two Formic Acid Glycol Ester, abbreviated as PEN), polyethylene terephthalate (english: polyethylene Terephthalate, abbreviated as PET), polyphenylene sulfide (english: polyphenyl Sulfide Granula, abbreviated as PPS), polyimide (english: polyimide, abbreviated as PI), polycarbonate (english: polycarbonate, abbreviated as PC), and cellulose acetate propionate (english: cellulose Acetate Propionate, abbreviated as CAP). Illustratively, the substrate 10 may be rigid, including a glass material containing SiO ₂ as a major component.

As shown in fig. 4, a plurality of sub-pixels 20 are disposed on the substrate 10, and the plurality of sub-pixels 20 may be arranged in a plurality of rows and a plurality of columns, for example, each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along the first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along the second direction Y. Wherein the first direction X intersects the second direction Y, e.g. the first direction X is perpendicular to the second direction Y.

The plurality of sub-pixels 20 may include a first sub-pixel having a first color, a second sub-pixel having a second color, and a third sub-pixel having a third color. Wherein the first color, the second color and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, and embodiments of the present disclosure are not particularly limited herein.

In some embodiments, as shown in fig. 4 and 5, each sub-pixel 20 includes a pixel circuit 21 and a light emitting device 22 disposed on the substrate 10. The pixel circuit 21 includes a plurality of transistors 211 and a storage Capacitor 212 (english: capacitor, abbreviated as C).

The transistors used in the circuit provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are all described by taking the thin film transistors as examples.

Illustratively, the transistor 211 is, for example, an oxide thin film transistor, which has high carrier mobility and can improve the response speed of the transistor 211.

As shown in fig. 5, the transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114, and the source 2112 and the drain 2113 are in contact with the active portion 2111, respectively. The storage capacitor 212 includes two plates disposed opposite each other.

Note that, the source electrode 2112 and the drain electrode 2113 may be interchanged, that is, 2112 represents the drain electrode and 2113 represents the source electrode in fig. 5.

The structure of the pixel circuit 21 described above includes various kinds, and can be selectively set according to actual needs. For example, the structure of the pixel circuit 21 may include a structure of "2T1C", "3T1C", "6T1C", "7T1C", "6T2C", or "7T2C", or the like. Where "T" is denoted as the transistor 211, the number preceding "T" is denoted as the number of transistors 211, "C" is denoted as the storage capacitor 212, and the number preceding "C" is denoted as the number of storage capacitors 212.

As shown in fig. 5, the light emitting device 22 includes a first electrode 221, a light emitting functional layer 222, and a second electrode 223, and the first electrode 221 may be electrically connected to, for example, a source 2112 or a drain 2113 of the plurality of transistors 211 as a driving transistor, and is illustrated in fig. 5 as electrically connecting the first electrode 221 to the drain 2113 of the transistor 211. The material of the first electrode 221 includes Indium Tin Oxide (ITO) or silver (Ag). The material of the second electrode includes aluminum (Al), ag, or magnesium (Mg).

The first electrode 221 is an anode of the light emitting device 22, and the second electrode 223 is a cathode of the light emitting device 22; or the first electrode 221 is a cathode of the light emitting device 22 and the second electrode 223 is an anode of the light emitting device 22. Hereinafter, the embodiment of the present disclosure will be exemplarily described taking the first electrode 221 as an anode of the light emitting device 22 and the second electrode 223 as a cathode of the light emitting device 22.

Illustratively, as shown in fig. 5, the second electrode 223 (cathode) is a monolithic structure.

The light-emitting functional layer 222 may include only a light-emitting layer, or may include at least one of an electron transport layer (english: election Transporting Layer, abbreviated as ETL), an electron injection layer (english: election Injection Layer, abbreviated as EIL), a hole transport layer (english: hole Transporting Layer, abbreviated as HTL), and a hole injection layer (english: hole Injection Layer, abbreviated as HIL) in addition to the light-emitting layer.

In some embodiments, as shown in fig. 5, the display panel 100 further includes an encapsulation layer 30. The encapsulation layer 30 is disposed on a side of the plurality of sub-pixels 20 away from the substrate 10, and the encapsulation layer 30 is used for encapsulating the light emitting device 22, so as to improve the service life of the light emitting device 22. The encapsulation layer 30 may be an encapsulation film or an encapsulation substrate, and the embodiments of the disclosure are not limited herein.

The encapsulation layer 30 may include one layer of encapsulation film, or may include two or more layers of encapsulation film stacked. For example, as shown in fig. 5, the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 that are stacked in a direction perpendicular to the substrate 10 and away from the substrate 10. Wherein the materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.

In some embodiments, the pixel circuit 21 includes a drive sub-circuit 201 and a data write sub-circuit 202.

In some examples, as shown in fig. 6 and 7, the drive sub-circuit 201 is coupled with a first node N1, a second node N2, and a third node N3. The driving sub-circuit 201 is configured to control on and off of the second node N2 and the third node N3 in response to the potential of the first node N1.

Illustratively, as shown in fig. 8 and 9, the driving sub-circuit 201 includes a second transistor (driving transistor) T2, a first pole of the second transistor T2 being connected to a second node N2, and a second pole being connected to a third node N3. The first control electrode is connected with the first node N1, and the second control electrode is connected with the third node N3. In this way, the leakage current of the second transistor T2 is smaller, which is beneficial to improving the performance of the second transistor T2. Wherein the first control is one of a top gate and a bottom gate of the second transistor and the second control is the other of the top gate and the bottom gate.

In some examples, as shown in fig. 8 and 9, the DATA writing sub-circuit 202 is coupled to the first node N1, the first scan signal terminal GATE1, and the DATA signal terminal DATA.

Illustratively, the DATA writing sub-circuit 202 includes a third transistor T3, a first pole of the third transistor T3 is connected to the DATA signal terminal DATA, a second pole is connected to the first node N1, and a control pole is connected to the DATA signal terminal DATA.

In some embodiments, the pixel circuit 21 has a detection stage in which the pixel circuit 21 needs to be detected to determine whether the pixel circuit 21 meets the design requirement. Wherein the detection phase is located after the preparation of the pixel circuit 21 and before the preparation of the light emitting device 22.

In general, the DATA signal terminal DATA is connected to a detecting device (e.g., a current sensor), and whether the pixel circuit 21 meets the requirement is determined by detecting the magnitude of the current at the DATA signal terminal DATA, and if the magnitude of the current at the DATA signal terminal DATA is less than or equal to a preset value, the requirement is satisfied. The preset value can be selected according to actual conditions. For example, the pixel circuit 21 may have a high requirement, the preset value may be smaller, the pixel circuit 21 may have a low requirement, and the preset value may be larger.

In the related art, in the detection stage, the driving sub-circuits cannot be detected, so that whether the driving sub-circuits are damaged or not cannot be judged, whether all the driving sub-circuits have differences or not cannot be judged, and the pixel circuits cannot be repaired in time, so that the subsequent process (for example, the preparation of the light emitting device) of the pixel circuits is affected, and further, the preparation cost of the display panel is high.

To solve the above technical problem, as shown in the figures, some embodiments of the present disclosure provide a pixel circuit 21, where the pixel circuit 21 has a detection stage, and the detection stage includes a first stage P1 as shown in fig. 10 and 11.

Wherein, as shown in fig. 12 and 13, the driving sub-circuit 201 is configured to control the conduction of the second node N2 and the third node N3 in response to the potential of the first node N1 in the first phase P1.

On this basis, as shown in fig. 6 and 7, the pixel circuit 21 further includes a first sub-circuit 203 and a detection sub-circuit 204.

The first sub-circuit 203 is coupled to the first signal terminal V1 and the scan signal terminal, and the first sub-circuit 203 is further coupled to one of the second node N2 and the third node N3. The first sub-circuit 203 is configured to, in the first phase P1, transfer the first signal received at the first signal terminal V1 to the first target node in response to the scan signal received at the at least one scan signal terminal. The first target node is a node coupled to the first sub-circuit 203 in the second node N2 and the third node N3.

The driving sub-circuit 201 is configured to control the conduction of the second node N2 and the third node N3 in response to the potential of the first node N1 in the first phase P1.

The detection sub-circuit 204 is coupled to the second scan signal terminal GATE2 and the DATA signal terminal DATA, and the detection sub-circuit 204 is further coupled to the other of the second node N2 and the third node N3.

Illustratively, as shown in fig. 8 and 9, the detection sub-circuit 204 includes a first transistor T1, a first pole of the first transistor T1 is coupled to the DATA signal terminal DATA, the other one of the second pole and the second node N2 and the third node N3, and a control pole is coupled to the second scan signal terminal GATE 2.

Further, as shown in fig. 12 and 13, the detection sub-circuit 204 is configured to transfer the signal received at the second target node to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE2 in the first phase P1. The second target node is a node coupled to the detection sub-circuit 204 among the second node N2 and the third node N3.

In this way, the first signal may be transferred to the DATA signal terminal DATA through the first sub-circuit 203, the driving sub-circuit 201, and the detecting sub-circuit 204. In this way, by detecting the current at the DATA signal terminal DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged or not, and determine whether all the driving sub-circuits 201 have differences, so as to repair the pixel circuit 21 in time, reduce the influence on the subsequent processes of the pixel circuit 21, and reduce the manufacturing cost of the display device.

It will be appreciated that in some embodiments, the detection subcircuit 204 remains normally closed during one display frame period, such that the risk of the detection subcircuit 204 affecting the display of images by the display panel 100 may be reduced.

In some embodiments, as shown in fig. 6 and 7, the pixel circuit 21 further includes a first light emitting sub-circuit 205, a first reset sub-circuit 206, and a second light emitting sub-circuit 207.

In some examples, as shown in fig. 6 and 7, the first light emitting sub-circuit 205 is coupled with the first voltage signal terminal VDD, the first light emitting signal terminal EM1, and the second node N2.

As shown in fig. 8 and 9, the first light emitting sub-circuit 205 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is coupled to the first voltage signal terminal VDD, a second electrode is coupled to the second node N2, and a control electrode is coupled to the first light emitting signal terminal EM 1.

In some examples, as shown in fig. 8 and 9, the first RESET sub-circuit 206 is coupled with the first initialization signal terminal VINIT1, the fourth node N4, and the first RESET signal terminal RESET 1. Wherein the fourth node N4 is configured to be coupled to an anode of the light emitting device 22.

Illustratively, as shown in fig. 8 and 9, the first RESET sub-circuit 206 includes a fifth transistor T5, a first pole of the fifth transistor T5 is coupled to the first initialization signal terminal VINIT1, a second pole is coupled to the fourth node N4, and a control pole is coupled to the first RESET signal terminal RESET 1.

In this way, under the control of the first RESET signal terminal RESET1, the first initialization signal received by the first initialization signal terminal VINIT1 may be transmitted to the fourth node N4 through the first RESET sub-circuit 206, so that the fourth node N4 may be initialized, and the problem that the electric potential of the previous image frame remaining on the fourth node N4 affects the display image of the next image frame may be improved, thereby improving the brightness uniformity of the display panel 100.

On this basis, as shown in fig. 6 to 9, the cathode of the light emitting device 22 is coupled to the second voltage signal terminal VSS. The level of the output of the second voltage signal terminal VSS is lower than the high level of the output of the first voltage signal terminal VDD.

In some examples, as shown in fig. 8 and 9, the second light emitting sub-circuit 207 is coupled with the third node N3, the second light emitting signal terminal EM2, and the fourth node N4.

As shown in fig. 8 and 9, the second light emitting sub-circuit 207 includes a sixth transistor T6, a first electrode of the sixth transistor T6 is coupled to the third node N3, a second electrode is coupled to the fourth node N4, and a control electrode is coupled to the second light emitting signal terminal EM 2.

In some embodiments, as shown in fig. 6, the detection subcircuit 204 is coupled with the second node N2. The first sub-circuit 203 includes the first reset sub-circuit 206 and the second light emitting sub-circuit 207 described above. At this time, the first signal terminal V1 includes a first initialization signal terminal VINIT1, the first target node is a third node N3, and the second target node is a second node N2.

As shown in fig. 10 and 12, the first RESET sub-circuit 206 is configured to transfer the first initialization signal received at the first initialization signal terminal VINIT1 to the fourth node N4 in response to the first RESET signal received at the first RESET signal terminal RESET1 in the first phase P1.

The second light emitting sub-circuit 207 is configured to transfer the received first initialization signal at the fourth node N4 to the third node N3 in response to the second light emitting signal received at the second light emitting signal terminal in the first phase P1.

The driving sub-circuit 201 is configured to transfer the received first initialization signal at the third node N3 to the second node N2 in response to the potential of the first node N1 in the first phase P1.

The detection sub-circuit 204 is configured to transfer the first initialization signal received with the second node N2 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE2 in the first phase P1.

In this way, the first initialization signal may be transferred to the DATA signal terminal DATA through the first reset sub-circuit 206, the second light emitting sub-circuit 207, the driving sub-circuit 201, and the detecting sub-circuit 204. In this way, by detecting the current at the DATA signal terminal DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged or not, and determine whether all the driving sub-circuits 201 have differences, so as to repair the pixel circuit 21 in time, reduce the influence on the subsequent processes of the pixel circuit 21, and reduce the manufacturing cost of the display device.

On the basis of the above embodiment, as shown in fig. 10 and 14, the detection stage further includes a second stage P2, and the first light emitting sub-circuit 205 is configured to transfer the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the first light emitting signal received at the first light emitting signal terminal EM1 in the second stage P2. At this time, the detection sub-circuit 204 is further configured to transfer the first voltage signal received at the second node N2 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE2 in the second phase P2.

In this manner, the first voltage signal may be transferred to the DATA signal terminal DATA through the first light emitting sub-circuit 205 and the detection sub-circuit 204. In this way, by detecting the current at the DATA signal terminal DATA, the first light emitting sub-circuit 205 can be detected to determine whether the first light emitting sub-circuit 205 is damaged or not, and determine whether all the first light emitting sub-circuits 205 have differences, so as to repair the pixel circuit 21 in time, reduce the influence on the process after the pixel circuit 21, and reduce the manufacturing cost of the display device.

In other implementations, as shown in fig. 7, the detection sub-circuit 204 is coupled to the third node N3, and the first sub-circuit 203 includes a first light-emitting sub-circuit 205. At this time, the first signal terminal V1 includes a first voltage signal terminal VDD, the first target node is a second node N2, and the second target node is a third node N3.

As shown in fig. 11 and 13, the first light emitting sub-circuit 205 is configured to transfer the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the first light emitting signal received at the first light emitting signal terminal EM1 in the first phase P1.

The drive sub-circuit 201 is configured to transfer the received first voltage signal at the second node N2 to the third node N3 in response to the potential of the first node N1 in the first phase P1.

The detection sub-circuit 204 is configured to transfer the first voltage signal received by the third node N3 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE2 in the first phase P1.

In this way, the first voltage signal may be transferred to the DATA signal terminal DATA through the first light emitting sub-circuit 205, the driving sub-circuit 201, and the detecting sub-circuit 204. In this way, by detecting the current at the DATA signal terminal DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged or not, and determine whether all the driving sub-circuits 201 have differences, so as to repair the pixel circuit 21 in time, reduce the influence on the subsequent processes of the pixel circuit 21, and reduce the manufacturing cost of the display device.

On the basis of the above embodiment, as shown in fig. 11 and 15, the detection stage further includes a second stage P2.

At this time, the first RESET sub-circuit 206 is configured to transfer the first initialization signal received at the first initialization signal terminal VINIT1 to the fourth node N4 in response to the first RESET signal received at the first RESET signal terminal RESET1 in the second phase P2.

The second light emitting sub-circuit 207 is configured to transfer the first initialization signal received at the fourth node N4 to the third node N3 in response to the second light emitting signal received at the second light emitting signal terminal EM2 in the second phase P2.

The detection sub-circuit 204 is further configured to transfer the first initialization signal received at the third node N3 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE2 in the second phase P2.

In this way, the first initialization signal may be transferred to the DATA signal terminal DATA through the first reset sub-circuit 206, the second light emitting sub-circuit 207, and the detection sub-circuit 204. In this way, by detecting the current at the DATA signal terminal DATA, the first reset sub-circuit 206 and the second light emitting sub-circuit 207 can be detected to determine whether the first reset sub-circuit 206 and the second light emitting sub-circuit 207 are damaged, and determine whether all the first reset sub-circuit 206 and the second light emitting sub-circuit 207 have differences, so that the pixel circuit 21 is repaired in time, the influence on the process after the pixel circuit 21 is reduced, and the manufacturing cost of the display device is reduced.

In some embodiments, as shown in fig. 6 and 7, the pixel circuit 21 further includes a second reset sub-circuit 208.

In some examples, as shown in fig. 6 and 7, the second RESET subcircuit 208 is coupled with the second initialization signal terminal VINIT2, the first node N1, and the second RESET signal terminal RESET 2.

Illustratively, as shown in fig. 8 and 9, the second RESET sub-circuit 208 includes a seventh transistor T7, a first pole of the seventh transistor T7 is coupled to the second initialization signal terminal VINIT2, a second pole is coupled to the first node N1, and a control pole is coupled to the second RESET signal terminal RESET 2.

In this way, under the control of the second RESET signal terminal RESET2, the second initialization signal received by the second initialization signal terminal VINIT2 may be transmitted to the first node N1 through the second RESET sub-circuit 208, so that the first node N1 may be initialized, and the problem that the potential of the previous image frame remaining in the first node N1 affects the display image of the next image frame may be improved, thereby improving the brightness uniformity of the display panel 100.

As shown in fig. 10, 11, 16 and 17, the detection phase further includes a third phase P3, wherein the second RESET sub-circuit 208 is configured to transmit the second initialization signal received at the second initialization signal terminal VINIT2 to the first node N1 in response to the second RESET signal received at the second RESET signal terminal RESET2 in the third phase P3.

At this time, the DATA writing sub-circuit 202 is configured to transfer the second initialization signal received at the first node N1 to the DATA signal terminal DATA in response to the first scan signal received at the first scan signal terminal GATE1 in the third stage P3.

In this manner, the second initialization signal may be transferred to the DATA signal terminal DATA through the second reset sub-circuit 208 and the DATA write sub-circuit 202. In this way, by detecting the current at the DATA signal terminal DATA, the DATA writing sub-circuit 202 can be detected to determine whether the DATA writing sub-circuit 202 is damaged or not, and determine whether all the DATA writing sub-circuits 202 have differences or not, so that the pixel circuit 21 is repaired in time, the influence on the subsequent process of the pixel circuit 21 is reduced, and the manufacturing cost of the display device is reduced.

In some embodiments, as shown in fig. 6 and 7, the pixel circuit 21 further includes a storage sub-circuit 209, the storage sub-circuit 209 being coupled to the first node N1 and the third node N3. The memory sub-circuit 209 is configured to store the potential of the third node N3.

In some examples, as shown in fig. 8 and 9, the storage subcircuit 209 includes a first storage capacitor 2091, a first plate of the first storage capacitor 2091 coupled to the first node N1, and a second plate coupled to the third node N3.

In other examples, as shown in fig. 18, the storage sub-circuit 209 includes a second storage capacitor 2092 and a third storage capacitor 2093.

Wherein a first plate of the second storage capacitor 2092 is coupled to the first node N1 and a second plate is coupled to the fifth node N5.

The third storage capacitor 2093 has a first plate coupled to the fifth node N5 and a second plate coupled to the third node N3.

In addition, the pixel circuit 21 further includes a third RESET sub-circuit 210, and the third RESET sub-circuit 210 is coupled to the third initialization signal terminal VINIT3, the fifth node N5, and the third RESET signal terminal RESET 3.

Illustratively, as shown in fig. 18, the third RESET sub-circuit 210 includes an eighth transistor T8, a first pole of the eighth transistor T8 is connected to the third initialization signal terminal VINIT3, a second pole is connected to the fifth node N5, and a control pole is connected to the third RESET signal terminal RESET 3.

Next, the operation of the pixel circuit 21 in the detection stage will be described in detail with reference to the timing chart. The following embodiments take the example in which each of the above transistors is N-type. As shown in fig. 10 and 11, the detection phase includes a first phase P1, a second phase P2, and a third phase P3.

Wherein, as shown in fig. 12 and 13, in the first stage P1;

The first sub-circuit 203 transfers the first signal received at the first signal terminal V1 to a node coupled to the first sub-circuit 203 in response to the scan signal received at the at least one scan signal terminal. Under control of the first node N1, the driving sub-circuit 201 passes the first signal received at the node coupled to the first sub-circuit 203 to the node coupled to the detection sub-circuit 204. The detection sub-circuit 204 transfers the first signal received at the node coupled to the detection sub-circuit 204 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE 2.

In some embodiments, as shown in fig. 12, the detection subcircuit 204 is coupled with the second node N2. In the first phase P1;

The first RESET sub-circuit 206 transfers the first initialization signal received at the first initialization signal terminal VINIT1 to the fourth node N4 in response to the first RESET signal received at the first RESET signal terminal RESET1, the second light emitting sub-circuit 207 transfers the first initialization signal received at the fourth node N4 to the third node N3 in response to the second light emitting signal received at the second light emitting signal terminal EM2, the driving sub-circuit 201 transfers the first initialization signal received at the third node N3 to the second node N2 in response to the potential at the first node N1, and the detecting sub-circuit 204 transfers the first initialization signal at the second node N2 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE 2.

In this way, the first signal may be transferred to the DATA signal terminal DATA through the first reset sub-circuit 206, the second light emitting sub-circuit 207, and the driving sub-circuit 201 and the detecting sub-circuit 204. In this way, by detecting the current at the DATA signal terminal DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged or not, and determine whether all the driving sub-circuits 201 have differences, so as to repair the pixel circuit 21 in time, reduce the influence on the subsequent processes of the pixel circuit 21, and reduce the manufacturing cost of the display device.

Illustratively, as shown in fig. 10 and 12, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the first phase P1, the first reset signal, the second light emitting signal and the second scan signal are all 1, and the first light emitting signal, the first scan signal and the second reset signal are all 0. Where "0" indicates a low level and "1" indicates a high level.

In this case, the first RESET signal terminal RESET1, the second light emitting signal terminal EM2, and the second scan signal terminal GATE2 input high level, and the fifth transistor T5, the sixth transistor T6, and the first transistor T1 are all turned on. The first light emitting signal terminal EM1, the first scan signal terminal GATE1, and the second RESET signal terminal RESET2 input low level, and the fourth transistor T4, the third transistor T3, and the seventh transistor T7 are all turned off.

The first initialization signal received at the first initialization signal terminal VINIT1 is transferred to the fourth node N4 through the fifth transistor T5, the first initialization signal received at the fourth node N4 is transferred to the third node N3 through the sixth transistor T6, the first initialization signal received at the third node N3 is transferred to the second node N2 through the second transistor T2, and the first initialization signal at the second node N2 is transferred to the DATA signal terminal DATA through the first transistor T1.

As shown in fig. 10 and 14, in the second phase P2;

the first light emitting sub-circuit 205 transfers the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the first light emitting signal received at the first light emitting signal terminal EM1, and the detection sub-circuit 204 transfers the potential at the second node N2 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE 2.

Illustratively, as shown in fig. 10 and 14, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the second phase P2, the first light emitting signal and the second scan signal are both 1, and the first reset signal, the second light emitting signal, and the first scan signal and the second reset signal are both 0.

In this case, the first light emitting signal terminal EM1 and the second scan signal terminal GATE2 input a high level, and the fourth transistor T4 and the first transistor T1 are both turned on. The first RESET signal terminal RESET1, the second light emitting signal terminal EM2, the first scan signal terminal GATE1, and the second RESET signal terminal RESET2 input a low level, and the fifth transistor T5, the sixth transistor T6, the third transistor T3, and the seventh transistor T7 are all turned off.

The first voltage signal received at the first voltage signal terminal VDD is transferred to the second node N2 through the fourth transistor T4, and the first voltage signal received at the second node N2 is transferred to the DATA signal terminal DATA through the first transistor T1.

In other implementations, as shown in FIG. 13, the detection subcircuit 204 is coupled with the third node N3. In the first phase P1;

The first light emitting sub-circuit 205 transmits the first voltage signal received at the first voltage signal terminal to the second node N2 in response to the first light emitting signal received at the first light emitting signal terminal EM1, the driving sub-circuit 201 transmits the first voltage signal received at the second node N2 to the third node N3 in response to the potential at the first node N1, and the detecting sub-circuit 204 transmits the first voltage signal received at the third node N3 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE 2.

Illustratively, as shown in fig. 11 and 13, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the first phase P1, the first light emitting signal and the second scan signal are both 1, and the first reset signal, the second light emitting signal, the first scan signal and the second reset signal are all 0.

In this case, the first light emitting signal terminal EM1 and the second scan signal terminal GATE2 input a high level, and the fourth transistor T4 and the first transistor T1 are turned on. The first RESET signal terminal RESET1, the second light emitting signal terminal EM2, the first scan signal terminal GATE1, and the second RESET signal terminal RESET2 input a low level, and the fifth transistor T5, the sixth transistor T6, the third transistor T3, and the seventh transistor T7 are all turned off.

The first voltage signal received at the first voltage signal terminal VDD is transferred to the second node N2 through the fourth transistor T4, the first voltage signal received at the second node N2 is transferred to the third node N3 through the second transistor T2, and the first voltage signal received at the third node N3 is transferred to the DATA signal terminal DATA through the first transistor T1.

As shown in fig. 11 and 15, in the second phase P2;

The first RESET sub-circuit 206 transfers the first initialization signal received at the first initialization signal terminal VINIT1 to the fourth node N4 in response to the first RESET signal received at the first RESET signal terminal RESET1, the second light emitting sub-circuit 207 transfers the potential at the fourth node N4 to the third node N3 in response to the second light emitting signal received at the second light emitting signal terminal EM2, and the detection sub-circuit 204 transfers the potential at the third node N3 to the DATA signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE 2.

Illustratively, as shown in fig. 11 and 15, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the second phase P2, the first reset signal, the second light-emitting signal and the second scan signal are all 1, and the first light-emitting signal, the first scan signal and the second reset signal are all 0.

In this case, the first RESET signal terminal RESET1, the second light emitting signal terminal EM2, and the second scan signal terminal GATE2 input high levels, and the fifth transistor T5, the sixth transistor T6, and the first transistor T1 are all turned on. The first light emitting signal terminal EM1, the first scan signal terminal GATE1, and the second RESET signal terminal RESET2 input low level, and the fourth transistor T4, the third transistor T3, and the seventh transistor T7 are all turned off.

The first initialization signal received at the first initialization signal terminal VINIT1 is transferred to the fourth node N4 through the fifth transistor T5, the first initialization signal received at the fourth node N4 is transferred to the third node N3 through the sixth transistor T6, and the first initialization signal received at the third node N3 is transferred to the DATA signal terminal DATA through the first transistor T1.

In some embodiments, as shown in fig. 10, 11, 16 and 17, the detection phase further comprises a third phase P3.

In a third phase P3;

The second RESET sub-circuit 208 transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the first node N1 in response to the second RESET signal received at the second RESET signal terminal RESET 2; the DATA writing sub-circuit 202 transfers the second initialization signal received at the first node N1 to the DATA signal terminal DATA in response to the first scan signal received at the first scan signal terminal GATE 1.

Illustratively, as shown in fig. 10, 11, 16, and 17, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the third phase P3, the second reset signal and the first scan signal are all 1, and the first reset signal, the second light-emitting signal, the second scan signal and the first light-emitting signal are all 0.

In this case, the second RESET signal terminal RESET2 and the first scan signal terminal GATE1 input a high level, and the third transistor T3 and the seventh transistor T7 are both turned on. The first RESET signal terminal RESET1, the second light emitting signal terminal EM2, the second scan signal terminal GATE2, and the first light emitting signal terminal EM1 input a low level, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the first transistor T1 are all turned off.

The second initialization signal received at the second initialization signal terminal VINIT2 is transferred to the first node N1 through the seventh transistor T7, and the second initialization signal received by the first node N1 is transferred to the DATA signal terminal DATA through the third transistor T3.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pixel circuit, characterized by a detection phase, the detection phase comprising a first phase; the pixel circuit includes:

A driving sub-circuit coupled to the first node, the second node, and the third node; the drive sub-circuit is configured to control conduction of the second node and the third node in response to a potential of a first node in the first phase;

The data writing sub-circuit is coupled with the first node, the first scanning signal end and the data signal end;

The first sub-circuit is coupled with the first signal end and the scanning signal end; the first sub-circuit is also coupled with one of the second node and the third node; the first sub-circuit is configured to, in the first stage, transfer a first signal received at the first signal terminal to a first target node in response to a scan signal received at the scan signal terminal; wherein the first target node is a node coupled to the first sub-circuit of the second node and the third node;

The detection sub-circuit is coupled with the second scanning signal end and the data signal end; the detection subcircuit is also coupled with the other of the second node and the third node; the detection subcircuit is configured to, in the first phase, pass signals received at a second target node to the data signal terminal in response to second scan signals received at a second scan signal terminal; wherein the second target node is a node of the second node and the third node coupled to the detection subcircuit.

2. The pixel circuit of claim 1, wherein the detection subcircuit is coupled with the second node, the first subcircuit comprising:

The first reset sub-circuit is coupled with the first initialization signal end, the fourth node and the first reset signal end; the first reset sub-circuit is configured to, in the first phase, transfer a first initialization signal received at the first initialization signal terminal to a fourth node in response to a first reset signal received at the first reset signal terminal; wherein the fourth node is configured to be coupled to an anode of a light emitting device;

A second light emitting sub-circuit coupled to the third node, the second light emitting signal terminal, and the fourth node; the second light emitting sub-circuit is configured to, in the first phase, transfer the received first initialization signal at the fourth node to the third node in response to the second light emitting signal received at the second light emitting signal terminal;

The drive sub-circuit is configured to pass, in the first phase, a received first initialization signal at the third node to the second node in response to a potential of the first node;

The detection subcircuit is configured to, in the first phase, pass a first initialization signal received by the third node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

3. The pixel circuit of claim 2, wherein the detection phase further comprises a second phase, the pixel circuit further comprising:

The first light-emitting sub-circuit is coupled with the first voltage signal end, the first light-emitting signal end and the second node; the first light emitting sub-circuit is configured to transfer, in the second phase, a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal;

The detection subcircuit is further configured to, in the second phase, pass the first voltage signal received at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

4. The pixel circuit of claim 1, wherein the detection subcircuit is coupled with the third node, the first subcircuit comprising:

The first light-emitting sub-circuit is coupled with the first voltage signal end, the first light-emitting signal end and the second node; the first light emitting sub-circuit is configured to transfer, in the first phase, a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal;

the drive sub-circuit is configured to pass, in the first phase, a received first voltage signal at the second node to the third node in response to a potential of the first node;

The detection subcircuit is configured to, in the first phase, pass a first voltage signal received at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

5. The pixel circuit of claim 4, wherein the detection phase further comprises a second phase, the pixel circuit further comprising:

The first reset sub-circuit is coupled with the first initialization signal end, the fourth node and the first reset signal end; wherein the fourth node is configured to be coupled to an anode of a light emitting device; the first reset sub-circuit is configured to, in the second phase, transfer a first initialization signal received at the first initialization signal terminal to a fourth node in response to a first reset signal received at the first reset signal terminal;

a second light emitting sub-circuit coupled to the third node, the second light emitting signal terminal, and the fourth node; the second light emitting sub-circuit is configured to transfer, in the second phase, the first initialization signal received at the fourth node to the third node in response to the second light emitting signal received at the second light emitting signal terminal;

The detection subcircuit is further configured to, in the second phase, pass the first initialization signal received at the third node to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

6. The pixel circuit according to any one of claims 1 to 5, wherein the detection sub-circuit includes:

a first transistor; the first electrode of the first transistor is coupled to the data signal terminal, the second electrode is coupled to the other of the second node and the third node, and the control electrode is coupled to the second scan signal terminal.

7. A pixel circuit according to any one of claims 1 to 5, wherein the drive sub-circuit comprises:

A second transistor; the first pole of the second transistor is coupled to the second node, the second pole is coupled to the third node, the first control pole is coupled to the first node, and the second control pole is coupled to the third node.

8. The pixel circuit according to any one of claims 1 to 5, wherein the detection stage further comprises a third stage,

The pixel circuit further includes:

The second reset sub-circuit is coupled with the second initialization signal end, the first node and the second reset signal end; the second reset sub-circuit is configured to transmit, in the third stage, a second initialization signal received at the second initialization signal terminal to the first node in response to a second reset signal received at a second reset signal terminal;

The data writing sub-circuit is configured to transfer the second initialization signal received at the first node to the data signal terminal in response to the first scan signal received at the first scan signal terminal in the third stage.

9. A method of detecting a pixel circuit, characterized by detecting the pixel circuit according to any one of claims 1 to 8; the detection phase includes a first phase;

In the first stage, a first sub-circuit transmits a first signal received at a first signal terminal to a node coupled to the first sub-circuit in response to a scan signal received at the at least one scan signal terminal; under control of a first node, the driving sub-circuit transfers a first signal received at a node coupled to the first sub-circuit to a node coupled to the detection sub-circuit; the detection sub-circuit transfers a first signal received at a node coupled to the detection sub-circuit to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

10. The method of detecting according to claim 9, wherein the detection subcircuit is coupled to the second node;

In the first stage, the first reset sub-circuit transmits a first initialization signal received at a first initialization signal terminal to a fourth node in response to a first reset signal received at a first reset signal terminal, the second light emitting sub-circuit transmits the first initialization signal received at the fourth node to a third node in response to a second light emitting signal received at a second light emitting signal terminal, the driving sub-circuit transmits the first initialization signal received at the third node to the second node in response to a potential at the first node, and the detection sub-circuit transmits the first initialization signal at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

11. The method of claim 10, wherein the detection phase further comprises a second phase;

In the second stage, the first light emitting sub-circuit transmits a first voltage signal received at a first voltage signal terminal to a second node in response to a first light emitting signal received at a first light emitting signal terminal, and the detection sub-circuit transmits a potential at the second node to a data signal terminal in response to a second scan signal received at a second scan signal terminal.

12. The method of detecting according to claim 9, wherein the detection subcircuit is coupled to a third node;

In the first stage, the first light emitting sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the first light emitting signal received at the first light emitting signal terminal, the driving sub-circuit transmits the first voltage signal received at the second node to the third node in response to the potential at the first node, and the detecting sub-circuit transmits the first voltage signal received at the third node to the data signal terminal in response to the second scanning signal received at the second scanning signal terminal.

13. The method of claim 12, wherein the detection phase further comprises a second phase;

In the second stage, the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the fourth node in response to the first reset signal received at the first reset signal terminal, the second light-emitting sub-circuit transmits the potential at the fourth node to the third node in response to the second light-emitting signal received at the second light-emitting signal terminal, and the detection sub-circuit transmits the potential at the third node to the data signal terminal in response to the second scan signal received at the second scan signal terminal.

14. The method according to any one of claims 9 to 13, wherein the detection phase further comprises a third phase;

In the third stage, the second reset sub-circuit transmits a second initialization signal received at a second initialization signal terminal to the first node in response to a second reset signal received at a second reset signal terminal; the data writing sub-circuit transfers the second initialization signal received at the first node to the data signal terminal in response to the first scan signal received at the first scan signal terminal.

15. A display device comprising the pixel circuit according to any one of claims 1 to 8.