CN118295482A - Integrated circuit and low dropout linear voltage regulator circuit - Google Patents

Abstract

The application provides an integrated circuit, which comprises a first conductive segment, a second conductive segment, a third conductive segment, a fourth conductive segment, a first conductive wire and a second conductive wire. The first to fourth conductive segments are separated from each other along the first direction. The first conductive segment and the third conductive segment are arranged between the first grid electrodes, and the second conductive segment and the fourth conductive segment are arranged between the second grid electrodes. The first conductive line transmits a drain/source signal and is coupled to the first conductive segment and the second conductive segment. The second conductive line transmits source/drain signals and is coupled with the third conductive segment and the fourth conductive segment. The third conductive segment and the fourth conductive segment are mirror symmetrical with respect to the second conductive line in a planar view.

Description

Integrated circuit and low dropout linear voltage regulator circuit

Technical Field

The present application relates to an integrated circuit and a low dropout linear voltage regulator circuit, and more particularly, to an integrated circuit and a low dropout linear voltage regulator circuit with symmetrical structures.

Background

In some output stage circuits, a plurality of transistors connected in parallel are generally applied in a limited area, thus compressing the distance between conductive lines, resulting in an increase in parasitic capacitance. The parasitic capacitance causes the output terminal to generate high-frequency voltage noise when transmitting high-frequency signals. In addition, in order to maintain high reliability of the circuit, a semiconductor layout (layout) of a conductive line and a metal wiring, which occupy a large area, is often used, thereby increasing manufacturing cost.

Disclosure of Invention

According to an embodiment of the present application, an integrated circuit is provided that includes first to fourth conductive segments and first to second conductive lines. The first to fourth conductive segments are separated from each other along the first direction. The first conductive segment and the third conductive segment are arranged between the first grid electrodes, and the second conductive segment and the fourth conductive segment are arranged between the second grid electrodes. The first conductive line transmits source/drain signals and is coupled with the first conductive segment and the second conductive segment. The second conductive line transmits a drain/source signal and is coupled to the third conductive segment and the fourth conductive segment. The third conductive segment and the fourth conductive segment are mirror symmetrical with respect to the second conductive line in a planar view.

According to another embodiment of the present application, an integrated circuit is provided that includes active regions separated from each other along a first direction, and first and second conductive lines having a comb-like structure. The first conductive line includes a plurality of first branch portions. The first branch of the first branch portion is coupled to two of the active regions adjacent to each other through a plurality of first conductive segments and a plurality of second conductive segments. The first conductive segment and the second conductive segment are disposed between the two of the active regions. The second conductive line comprises a plurality of second branch parts, wherein the second branch parts are staggered with the active region.

According to another embodiment of the present application, a low dropout linear regulator circuit is provided, which includes a first conductive line, a second conductive line, and an output stage circuit. The output stage circuit comprises a first conductive segment, a second conductive segment, a plurality of first active regions arranged in the first active region and a plurality of second active regions arranged in the second active region. The first conductive segment and the second conductive segment are in mirror image configuration relative to the first direction and correspond to the source/drain of the output stage circuit. The first active region and the second active region are disposed between the first conductive line and the second conductive line. The first active region and the second active region are coupled to the second conductive line through the first conductive segment and the second conductive segment, respectively.

Drawings

The manner in which an embodiment of the application is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale in accordance with standard practices in the art. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 shows a schematic diagram of a low dropout linear regulator circuit according to an embodiment.

Fig. 2 shows a schematic diagram of a low dropout linear regulator circuit according to another embodiment.

Fig. 3 is a schematic diagram illustrating the integrated circuit of fig. 1 or fig. 2 in a planar view according to an embodiment.

Fig. 4 is a schematic diagram illustrating an integrated circuit corresponding to fig. 1 or fig. 2 in a planar view according to another embodiment.

Detailed Description

Many different embodiments or examples are provided below for implementing different features of the provided subject matter. In order to simplify one embodiment of the present application, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, an embodiment of the present application may repeat reference numerals and/or letters in the various examples. For brevity and clarity, the repetition itself does not dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "below," "lower," "above," "upper," "top," "bottom," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated. The spatially relative terms are intended to encompass different orientations of the device in use or operation and the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected," may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.

See fig. 1. Fig. 1 shows a schematic diagram of a low dropout linear regulator circuit 10 according to an embodiment. As shown in fig. 1, the low dropout linear regulator circuit 10 includes an operational amplifier 12, an output stage circuit 14, and resistor units R1 to R2. The output stage 14 and the resistor units R1-R2 are coupled between the supply voltage terminal 16 and the ground. The supply voltage terminal 16 is used for providing the supply voltage VDD. The output terminal 18 is coupled between the output stage 14 and the resistor unit R1.

The operational amplifier 12 receives the input signal Vin at its positive input terminal and the voltage division voltage of the output signal Vout through the resistor units R1 to R2 at its negative input terminal. In some embodiments, the operational amplifier 12 outputs the signal Vc to the output stage 14 according to the divided voltage of the input signal Vin and the output signal Vout to adjust the output signal Vout.

As shown in fig. 1, the output stage circuit 14 includes an N-type transistor TN. In some embodiments, the N-type transistor TN is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with an N-type doping. Thus, the operational amplifier 12 outputs a signal Vc to the control terminal (gate) of the N-type transistor TN.

See fig. 2. Fig. 2 shows a schematic diagram of a low dropout linear regulator circuit 20 according to an embodiment. With respect to the embodiment of fig. 2, for ease of understanding, the same elements as in fig. 1 are denoted by the same reference numerals. For the sake of brevity, specific operations of similar elements that have been discussed in detail in the preceding paragraphs are omitted herein unless a cooperative relationship with the elements shown in fig. 2 needs to be introduced.

In contrast to the low dropout linear regulator circuit 10 of fig. 1, the output stage circuit 14 in the low dropout linear regulator circuit 20 includes a P-type transistor TP. In some embodiments, the P-type transistor TP is a metal oxide semiconductor field effect transistor with P-type doping. In addition, the negative input terminal of the operational amplifier 12 in fig. 2 is used for receiving the input signal Vin, and the positive input terminal receives the divided voltage corresponding to the output signal Vout. Thus, the operational amplifier 12 outputs a signal Vc to the control terminal (gate) of the P-type transistor TP.

The configurations of fig. 1-2 are presented for illustrative purposes. The various implementations of fig. 1-2 are within the intended scope of an embodiment of the invention. For example, in some embodiments, output stage 14 may include a plurality of transistors connected in parallel with one another between supply voltage terminal 16 and output 18.

See fig. 3. Fig. 3 is a schematic diagram illustrating an integrated circuit 30 corresponding to fig. 1 or fig. 2 in a planar view according to an embodiment.

As shown in fig. 3, the integrated circuit 30 includes active regions 110-120, a plurality of conductive segments 210, a plurality of conductive segments 220, a plurality of conductive segments 230, a plurality of conductive segments 240, a plurality of gates 310, a plurality of gates 320, a conductive line 410, a conductive line 420, and a plurality of vias 510.

In some embodiments, conductive segments 210, 220 correspond to the drain/source of N-type transistor TN in FIG. 1 or the drain/source of P-type transistor TP in FIG. 2, while conductive segments 230, 240 correspond to the source/drain of N-type transistor TN in FIG. 1 or the source/drain of P-type transistor TP in FIG. 2. The gates 310 and 320 correspond to the gates of the N-type transistor TN in fig. 1 or the gates of the P-type transistor TP in fig. 2. For brevity, embodiments of the present application will be described below with respect to integrated circuit 30 corresponding to N-type transistor TN of fig. 1.

In the embodiment shown in fig. 3, the structures in the integrated circuit 30 correspond to mirror symmetry of the line segments 101 extending in the x-direction. In some embodiments, conductive line 420 extends in the x-direction and is disposed intermediate active regions 110-120; in other words, the structures in integrated circuit 30 are mirror symmetric with respect to conductive line 420 in a planar view.

Specifically, the active regions 110 to 120 extend in the x-direction and are separated from each other in the y-direction in the first semiconductor layer. Active regions 110-120 are disposed between conductive line 410 and conductive line 420. As shown in the embodiment of fig. 3, active regions 110-120 are each on opposite sides of conductive line 420 and are surrounded by conductive line 410.

The conductive segments 210 to 240 are arranged apart in the x-direction in the second semiconductor layer disposed above the first semiconductor layer. Conductive segments 210 and 230 are disposed between gates 310 extending along y, and conductive segments 220 and 240 are disposed between gates 320 extending along y. In some embodiments, the gate 310 and the gate 320 are disposed in the second semiconductor layer.

Conductive segments 210 and 220 are separated from each other along the y-direction and are mirror image configured with respect to the x-direction or conductive line 420. Conductive segment 210 extends in the y-direction from branch 411 in conductive line 410 toward active region 120 and serves to couple a plurality of active regions 122 in active region 120 between gates 310 with conductive line 410. On the other hand, the conductive segment 220 extends from the branch portion 412 in the conductive line 410 toward the active region 110 in the y-direction and serves to couple the plurality of active regions 112 in the active region 110 between the gates 320 with the conductive line 410. In some embodiments, branch portion 413 in conductive line 410 extends in the y-direction and is coupled between branch portion 411 and branch portion 412.

Similarly, conductive segments 230 and 240 are separated from each other along the y-direction and are mirror-image configured with respect to the x-direction or conductive line 420. Conductive segment 230 extends in the y-direction from conductive line 420 toward active region 120 and serves to couple a plurality of active regions 121 in active region 120 between gates 310 with conductive line 420. On the other hand, the conductive segment 240 extends from the conductive line 420 toward the active region 110 in the y-direction and serves to couple the plurality of active regions 111 in the active region 110 between the gates 320 with the conductive line 420.

As shown in fig. 3, in the y-direction, the active regions 110 to 120 have a width W1, the branch portions 411 and 412 of the conductive lines 410 have a width W2, the conductive lines 420 have a width W3, and the via 510 has a width W4. In some embodiments, since design rule checking (Design rule checking, DRC) during integrated circuit fabrication indicates that the spacing (spacing) between gates 310 and 320 needs to be at least greater than a particular threshold, the width W3 of conductive line 420 is greater than the widths W2 of branch portions 411 and 412 on both sides of conductive line 420 (which may be considered outside of integrated circuit 30). The width W1 of the active regions 110-120 is between the width W2 and the width W3. In some embodiments, width W3 may be about 1.4 times width W2, and width W3 may be about 1.1 times width W1. Further, the gates 310 and 320 have a length L1 in the x-direction. In some embodiments, length L1 is between width W1 and width W2.

In some embodiments, conductive line 410 is used to pass drain/source signals and conductive line 420 is used to pass source/drain signals. For example, referring to fig. 1 and 3, the conductive line 410 transmits the drain/source signal between the drain/source of the N-type transistor TN and the supply voltage terminal 16, i.e., the conductive line 410 is used as the input terminal of the output stage circuit 14 to receive the supply voltage VDD. The conductive line 420 transmits source/drain signals between the source/drain of the N-type transistor TN and the output terminal 18, i.e., the conductive line 420 is used as the output terminal 18 of the output stage circuit 14.

In some embodiments, conductive lines 410 and 420 are disposed in a third semiconductor layer over a second semiconductor layer and will receive or transmit signals through vias 510 to other conductive connection lines in a fourth semiconductor layer over the third semiconductor layer. For example, the conductive lines 410 and 420 may be Metal-zero (M0) and the other conductive lines may be Metal-one (M1) or higher. In some embodiments, the thickness of the conductive lines 410 and 420 along the z-direction is thinner than other conductive connection lines, so the conductive lines 410 and 420 can be considered as thin metal layers, and other conductive connection lines can be considered as thick metal layers. In some embodiments, in order to make the conductive lines 410 and 420 safely connected to the thick metal layer through the via 510, the widths W2 of the branch portions 411 and 412 of the conductive lines 410 and the width W3 of the conductive lines 420 are larger than the width W4 of the via 510.

The configurations of fig. 1-3 are presented for illustrative purposes. The various implementations of fig. 1-3 are within the intended scope of an embodiment of the invention. For example, in some embodiments, conductive line 410 is used to pass source/drain signals and conductive line 420 is used to pass drain/source signals.

In a general low dropout linear regulator circuit, a plurality of transistors connected in parallel are generally applied as an output stage circuit in a limited area, so that a distance between conductive lines connecting drain and source of the transistors is compressed, resulting in an increase in parasitic capacitance. The parasitic capacitance forms a feed-forward path connected to the output terminal so that the output terminal generates high-frequency voltage noise when transmitting high-frequency signals. In addition, in order to maintain high reliability of the circuit against high voltage and high current, a semiconductor layout (layout) using a large-area conductive wire and a metal wire is required, and thus manufacturing cost is increased.

By the integrated circuit layout provided by the application, only a single conductive line is contained in the adjacent active region. In other words, the distance between the two conductive wires is increased, thereby reducing the parasitic capacitance between the conductive wires and reducing the output quantity of high-frequency voltage noise output through the parasitic capacitance, and improving the product performance. Meanwhile, compared with some methods, the symmetrical design provided by the application can lead the conducting segments of the same pole of the corresponding transistor to be directly coupled with the same conducting wire, thereby greatly reducing the area required by the circuit. For example, in some embodiments, the integrated circuit area of the present application saves about 20% of the area over some approaches, further saving manufacturing costs.

Refer to fig. 4. Fig. 4 is a schematic diagram illustrating an integrated circuit 40 corresponding to fig. 1 or fig. 2 in a planar view according to another embodiment. With respect to the embodiment of fig. 4, the same elements as in fig. 1 to 3 are denoted by the same reference numerals for easy understanding.

As shown in fig. 4, integrated circuit 40 further includes active regions 130-140 and conductive segments 250-280. In some embodiments, active regions 130-140 are configured in connection with, for example, active regions 110-120. Conductive segments 250-280 are configured in connection with, for example, conductive segments 210-240. In some embodiments, conductive segments 250 and 280 correspond to the drain/source of the N-type transistor TN of FIG. 1, and conductive segments 260 and 270 correspond to the source/drain of the N-type transistor TN of FIG. 1.

In addition, compared to the integrated circuit 30 in fig. 3, the conductive lines 410 and 420 in the integrated circuit 40 have a comb-like structure including a plurality of branch portions. Specifically, the conductive line 410 further includes a branch portion 414 parallel to the branch portions 411 and 412 and separated from each other in the y-direction, and the branch portion 413 is coupled between the branch portions 411 to 412 and the branch portion 414. The conductive line 420 includes a branch portion 421 extending in the x-direction, a branch portion 422, and a branch portion 423 extending in the y-direction and coupled between the branch portions 421 and 422. The branch portions 421 and 422 are staggered with the active regions 110 to 140; further, the branching portion 421 is disposed between the branching portion 411 and the branching portion 414, and the branching portion 422 is disposed between the branching portion 411 and the branching portion 412.

In some embodiments, the number of branch portions of conductive line 410 (e.g., 3 in fig. 4) is different from the number of branch portions of conductive line 420 (e.g., 2 in fig. 4) along the x-direction.

In the embodiment shown in FIG. 4, the region 40A defined by the branch portions 411-414 is mirror symmetric along the x-direction. Specifically, region 40A is mirror symmetric along line segment 102. In some embodiments, the region 40B defined by the branch portion 411 and the branch portion 414 is mirror symmetric along the x-direction and the line segment 103.

For example, conductive segment 250 is mirror symmetric with conductive segment 210 with respect to line segment 102 (and branch portion 411) and is used to couple active region 130 to branch portion 411. In other words, the branch portion 411 is coupled with the active regions 120 to 130 adjacent to each other through the conductive segments 210 and 250 configured in mirror symmetry. In some embodiments, conductive segment 250 is also mirror symmetric with conductive segment 210 with respect to branch 411.

The conductive segments 260-270 are disposed between adjacent active regions 130-140 and mirror-symmetrical with respect to line segment 103 (and branch 421). Conductive segments 260-270 also serve to couple adjacent active regions 130-140 to branch 421. In some embodiments, conductive segment 260 is also mirror symmetric with respect to branch portion 411 and conductive segment 230 coupled to branch portion 422.

In summary, the integrated circuit and the low dropout linear regulator circuit of the present application provide a symmetrically configured integrated circuit layout design. By reducing the number of conductive wires and increasing the distance between two conductive wires, the parasitic capacitance between the conductive wires and the output quantity of high-frequency voltage noise output through the parasitic capacitance are reduced, the product efficiency is improved, and the manufacturing cost is saved.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various ways in which an embodiment of the application may be implemented. Those skilled in the art should appreciate that they may readily use an embodiment of the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of an embodiment of the application, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of an embodiment of the application.

Description of the reference numerals

10. 20 Low dropout linear voltage regulator circuit

30. 40 Integrated circuit

12: Operational amplifier

14: Output stage circuit

16: Supply voltage terminal

18: An output terminal

101-103: Line segment

110. 120, 130, 140: Active region

111. 112: Active area

121. 122: Active area

210. 220, 230, 240, 250, 260, 270, 280: Conductive segment

310. 320: Grid electrode

40A: region(s)

40B: region(s)

410. 420: Conductive wire

411 To 414: branching portion

421 To 423: branching portion

510: Through hole

TN, TP: transistor with a high-voltage power supply

Vc: signal signal

Vin: input signal

Vout: output signal

VDD: supply voltage

R1 and R2: resistor unit

W1 to W4: width of (L)

L1: length of

H: height of (1)

X, y: direction of

Claims (10)

1. An integrated circuit, comprising:

The plurality of first conductive segments and the plurality of second conductive segments are separated from each other along a first direction;

a plurality of third conductive segments and a plurality of fourth conductive segments separated from each other along the first direction, wherein the plurality of first conductive segments and the plurality of third conductive segments are disposed between a plurality of first gates, and the plurality of second conductive segments and the plurality of fourth conductive segments are disposed between a plurality of second gates;

The first conductive wire is used for transmitting a drain/source signal and is coupled with the first conductive segments and the second conductive segments; and

The second conductive line is used for transmitting source/drain signals and is coupled with the third conductive segments and the fourth conductive segments, wherein the third conductive segments and the fourth conductive segments are mirror symmetrical relative to the second conductive line in a plane view.

2. The integrated circuit of claim 1, wherein the plurality of first conductive segments and the plurality of second conductive segments are mirror symmetric with respect to the second conductive line.

3. The integrated circuit of claim 1, further comprising:

a first active region coupled with the plurality of first conductive segments and the plurality of third conductive segments and having a first width along the first direction;

Wherein the plurality of first conductive segments to the plurality of fourth conductive segments extend in the first direction and the second conductive line extends in a second direction different from the first direction and has a second width in the first direction that is greater than the first width,

Wherein the first conductive line has a third width in the first direction that is different from the second width.

4. The integrated circuit of claim 1, further comprising:

a plurality of fifth conductive segments coupled to a first portion of the first conductive line and mirror-symmetrical to the plurality of first conductive segments with respect to the first portion,

Wherein a second portion of the first conductive line is coupled with the plurality of second conductive segments and the first portion and the second portion extend in a second direction different from the first direction; and

A plurality of sixth conductive segments are coupled to the second conductive line and mirror-symmetrical to the plurality of third conductive segments with respect to the first portion of the first conductive segments.

5. The integrated circuit of claim 1, further comprising:

a plurality of fifth conductive segments are coupled with a first portion of the second conductive line and the plurality of third conductive segments are coupled with a second portion of the second conductive line,

Wherein the first portion and the second portion extend in a second direction different from the first direction, and a third portion of the second conductive line is coupled between the first portion and the second portion.

6. An integrated circuit, comprising:

A plurality of active regions separated from each other along a first direction;

A first conductive line having a comb-like structure and including a plurality of first branch portions, wherein first branches of the plurality of first branch portions are coupled to two of the plurality of active regions adjacent to each other through a plurality of first conductive segments and a plurality of second conductive segments, wherein the plurality of first conductive segments and the plurality of second conductive segments are disposed between the two of the plurality of active regions; and

The second conductive wire is provided with a comb-shaped structure and comprises a plurality of second branch parts, wherein the second branch parts and the active areas are staggered.

7. The integrated circuit of claim 6, wherein a first branch of the second branch portion is disposed between the first branch of the plurality of first branch portions and a second branch of the plurality of first branch portions,

Wherein the first branch of the second branch portion is coupled to another two of the plurality of active regions adjacent to each other through a plurality of third conductive segments and a plurality of fourth conductive segments, wherein the plurality of third conductive segments and the plurality of fourth conductive segments are disposed between the another two of the plurality of active regions,

Wherein the regions defined by the first branches of the plurality of first branch portions and the second branches of the plurality of first branch portions are mirror symmetric along a second direction different from the first direction.

8. The integrated circuit of claim 6, wherein a number of the plurality of first branch portions is different than a number of the plurality of second branch portions.

9. A low dropout linear regulator circuit, comprising:

a first conductive line and a second conductive line; and

An output stage circuit comprising:

A plurality of first conductive segments and a plurality of second conductive segments, wherein the plurality of first conductive segments and the plurality of second conductive segments are mirror-configured with respect to a first direction and correspond to source/drain electrodes of the output stage circuit; and

A plurality of first active regions disposed in a first active region and a plurality of second active regions disposed in a second active region, wherein the first active region and the second active region are disposed between the first conductive line and the second conductive line, and

The plurality of first active regions and the plurality of second active regions are coupled to the second conductive lines through the plurality of first conductive segments and the plurality of second conductive segments, respectively.

10. The low dropout linear regulator circuit according to claim 9, wherein said first conductive line further comprises a first portion and a second portion extending along said first direction,

Wherein the output stage circuit further comprises a plurality of third conductive segments and a plurality of fourth conductive segments corresponding to the drain/source of the output stage circuit,

The plurality of third conductive segments extend from the first portion to the second active region in a second direction different from the first direction, and

The plurality of fourth conductive segments extend from the second portion to the first active region in the second direction.