CN1182762C

CN1182762C - High-speed circuit board with high-dielectric coefficient insulating material to lower wire impedance

Info

Publication number: CN1182762C
Application number: CNB011324074A
Authority: CN
Inventors: 郑裕强
Original assignee: Mitac International Corp
Current assignee: Mitac International Corp; Mitac Inc
Priority date: 2001-08-30
Filing date: 2001-08-30
Publication date: 2004-12-29
Anticipated expiration: 2021-08-30
Also published as: CN1404351A

Abstract

The present invention relates to a high speed circuit board which reduces routing resistance by using an insulation material with high dielectric coefficient and comprises at least two metal layers and at least two signal routing layers, wherein the at least one of the at least two metal layers is used as a ground plane, and at least one metal layer is used as a power plane; two outer layers of the circuit board are respectively the signal running cable layers, and insulation layers are clamped among the layers of the circuit board for insulation. The present invention is characterized in that the dielectric constant of an insulation layer on one side of at least one metal layer in the metal layers is a first dielectric constant, a material of the insulation layer on the other side is a low consumption factor, and the dielectric constant of the material is a second dielectric constant which is higher than the first dielectric constant; the other side which is positioned on the insulating layer with the second dielectric coefficient and is not connected with at least one metal layer is one of the signal routing layers, and the wire width and the wire distance of the routing are not reduced.

Description

Utilize the insulating material of high-dielectric coefficient to reduce the high speed circuit board of walking line impedence

Technical field

The present invention relates to a kind of high-dielectric coefficient insulating material that utilizes and reduce the high speed circuit board of walking line impedence, particularly a kind of circuit board that is laid in the anti-cabling of High speed and low resistance for the high speed signal use.

Background technology

With reference to Fig. 1, it is the four-layer circuit board of a kind of public thickness of slab 1.6mm, first and four layer of this circuit board is signal lead layer S1, S2, the second layer is that bus plane Power and the 3rd layer are ground plane GND, and this circuit board has one and lays respectively at the second insulating barrier I2 between first and two layer and the 3rd and four layer of this circuit board at the first insulating barrier I1 and two between second and three layer of this circuit board, the first insulating barrier I1 is a base material (thin core) and the second insulating barrier I2 is film (prepreg), the thickness H1 of the first insulating barrier I1 is that the thickness H2 of the 47mil and the second insulating barrier I2 is 5mil, general manufacturer adopts glass reinforced epoxy to make first, two insulating barrier I1, so I2 is first, two insulating barrier I1, the dielectric coefficient of I2 is 4.5.

Signal lead layer S1 on the general circuit plate, S2 is last except laying electronic component, also have many cablings in order to aforesaid electronic component and the electrical path that provides circuit board and other devices to electrically connect to be provided, and for the characteristic that signal transmits on these cablings deny well one of main decision important document be its relative impedance, and because first and second signal lead layer among Fig. 1 is symmetric structure, so the first signal lead layer S1 equals the impedance with respect to metal level (being ground plane GND) of secondary signal routing layer S2 with respect to metal level (promptly referring to bus plane POWER) impedance meeting, thereby only represent with the relative impedance of calculating the first signal lead S1 following, refer again to Fig. 2, calculate the relative impedance Z of the first signal lead layer S1 with the habitual condition of present industry according to following formula 1 ₀:

Z_{0} = (\frac{87}{\sqrt{E + 1.414}}) \ln (\frac{5.98 H}{0.8 W + T})

Formula 1

Wherein: E=dielectric coefficient=4.5

The thickness 5mil of the H=second insulating barrier I2

W=live width=5mil

Thickness=the 0.7mil of T=signal lead layer

Then, behind above-listed formula 1 and experimental check, the relative resistance value Z that signal lead layer S1 is right ₀The relative impedance of=60 ohm=secondary signal routing layer S2.

Yet, to require to be 28 ± 10% ohm according to the impedance of internet at present for the anti-cabling of High speed and low resistance on the circuit board, and the anti-cabling of this High speed and low resistance can be used the layout or the like of the static RAM (DRAM) of RAMBUS, with aforementioned public four-layer circuit board, desire to be low to moderate 28 ohm by 60 ohmmic drops, then add result of experiment with above-listed formula, then the width W of cabling must increase to 21mil, and general phase mutual interference for fear of signal, factors such as cross-talk, so line-spacing S (distance that promptly refers to space in the cabling in twos) is 1: 1 than the ratio of live width W, thereby line-spacing S also is required to be 21mil.But today, circuit board was obviously towards short and small frivolous development trend, and it is rare precious to make that the area that can supply layout (layout) more comes, and layout difficulty in the anti-cabling of the High speed and low resistance in the so big space of this kind needs (each bar cabling need the 42mil) formation.

Summary of the invention

Therefore, a purpose of the present invention is promptly providing a kind of high-dielectric coefficient insulating material that can utilize to reduce the high speed circuit board of walking line impedence, to reach the live width of dwindling the anti-cabling of High speed and low resistance.

A further object of the present invention is promptly providing a kind of high-dielectric coefficient insulating material that can utilize to reduce the high speed circuit board of walking line impedence, reaches to improve cabling layout closeness to meet economic benefits.

Another purpose of the present invention promptly providing a kind of high-dielectric coefficient insulating material that can utilize to reduce the high speed circuit board of walking line impedence, reaches the effect that thickness of slab meets industrial standard.

So, the invention provides a kind of insulating material of high-dielectric coefficient that utilizes and reduce the high speed circuit board of walking line impedence, this circuit board comprises at least two metal levels and at least two signal lead layers, metal level in this at least two metal level is used separately as ground plane and bus plane, and the layer in two outsides of this circuit board is respectively this signal lead layer, and insert and put an insulating barrier respectively to isolate in each interlayer of aforementioned circuit plate, it is characterized in that:

The dielectric coefficient of the insulating barrier of one side of at least one metal level in this metal level in this circuit board is one first dielectric coefficient, and the dielectric coefficient of the insulating barrier of opposite side is one to be higher than second dielectric coefficient of this first dielectric coefficient, and be arranged in for the non-opposite side that joins with this at least one metal level of the insulating barrier of this second dielectric coefficient is of aforementioned signal lead layer, to reduce the cabling live width and the line-spacing of this signal lead layer.

Description of drawings

Other features and advantages of the present invention in the detailed description below in conjunction with the preferred embodiment of accompanying drawing, can clearly be understood, in the accompanying drawings:

Fig. 1 is the schematic section of a public four-layer circuit board.

Fig. 2 is the local schematic section of public four-layer circuit board.

Fig. 3 is a schematic section of one first preferred embodiment of the present invention, and this embodiment is a four-layer circuit board.

Fig. 4 is a schematic section of one second preferred embodiment of the present invention, and this embodiment is a 6-layer circuit board.

Fig. 5 is the partial sectional view of second preferred embodiment among Fig. 4.

Fig. 6 is a schematic section of one the 3rd preferred embodiment of the present invention, and this embodiment is a 8-layer printed circuit board.

Fig. 7 is the partial sectional view of the 3rd preferred embodiment of Fig. 6.

Fig. 8 is the schematic section of one the 4th preferred embodiment of the present invention, and this embodiment is 10 layer circuit boards.

Fig. 9 is the schematic section of one the 5th preferred embodiment of the present invention, and this embodiment is a Floor 12 circuit board.

Figure 10 is the schematic section of one the 6th preferred embodiment of the present invention, and this embodiment is 10 6-layer circuit boards.

Embodiment

It should be noted that each diagram in this specification is only for illustrating that the relation between each layer illustrates, the standard specification when its dimensions is not practical application.

With reference to Fig. 3, it is first preferred embodiment of the present invention, in the present embodiment, this circuit board 1 is a four-layer circuit board, first of this circuit board 1, four layers is signal lead layer S1, S2, and these signal lead layers S1, also power sub-part of S2 is laid and the layout cabling, and the second layer of this circuit board 1 and the 3rd layer are all a metal level and be used as bus plane POWER or ground plane GND according to institute's role in its circuit design, at this second layer as bus plane POWER, reach the 3rd layer as ground plane GND, in addition, this circuit board from top to bottom has one first insulating barrier 11 of aforementioned each layer of the electrical isolation of being used in regular turn, one second insulating barrier 12 and one the 3rd insulating barrier 13, for manufacturer, second insulating barrier 12 is base material (thin core) and the first and the 3rd insulating barrier 11, the 13rd, film (prepreg).

As previously mentioned, desire is for each signal lead layer-S1 of the anti-cabling of layout High speed and low resistance in the circuit board 1, the relative resistance value of S2 preferably is in 25.2～30.8 ohm of scopes of the theoretical resistance value of the anti-circuit of High speed and low resistance of internet regulation, and as with aforementioned formula 1 if relative impedance is reduced, can utilize the thickness H that reduces insulating barrier or increase mode such as dielectric coefficient E, yet the gross thickness of various different layers circuit boards and the thickness of insulating barrier in fact early have industry specification numerical value, so if excessively reduce thickness of insulating layer, then the characteristic of circuit board changes thereupon, make integral layout also will significantly change thereupon, moreover the gross thickness of circuit board also can no longer meet industrial standard thickness, causes the difficulty in the use.

Thereby the present invention excessively do not change circuit board originally thickness etc. impose a condition down, utilize the dielectric coefficient of the partial insulative layer 11,13 of the signal line layer that improves the anti-cabling of adjacent desire laying High speed and low resistance to reduce relative impedance, and for fear of signal in cabling the transmission in the excessive loss, and cause too high signal transmission loss, so seek the insulating material that replaces also need meet the low consumption factor (Dissipation Factor) except high-dielectric coefficient requirement.Moreover, circuit board symmetry pressing for convenience, manufacturers design mostly make symmetric position insulating barrier (as first with the 3rd insulating barrier 11,13) thickness identical, comparatively convenient on not only making, also meet manufacture now, so, in the present embodiment, set first and second signal lead layer S1, S2 and all can be used to the anti-cabling of layout High speed and low resistance, so according to earlier figures 2 and formula 1, the material of first and second insulating barrier 11,13 of contiguous two signal lead layer S1, S2 is improved.The material of insulating barrier that manufacturer is applied in 11,12,13 all was that dielectric coefficient is 4.5 glass reinforced epoxy in the past, thus the present invention seek dielectric coefficient be higher than 4.5 and the material of the low consumption factor make the first and the 3rd insulating barrier 11,13.

It should be noted that the following explanation of present embodiment is that the thickness of slab at the industrial standard of four-layer circuit board is that 1.6mm illustrates, but enforcement of the present invention should be not limited to the four-layer circuit board 1 of thickness of slab 1.6mm:

Simultaneously with reference to Fig. 3, set the glass reinforced epoxy that second insulating barrier 12 still uses dielectric coefficient 4.5, do not change, and the first and the 3rd insulating barrier 11,13 change over and utilize dielectric coefficient to be higher than 4.5 high-dielectric coefficient and make for the insulating material of the low consumption factor, in the present embodiment, select for use polytetrafluoroethylene (the Ceramic filled Teflon) dielectric coefficient of ceramic filling to be used as the first and the 3rd insulating barrier 11,13 insulating material, and its dielectric coefficient be 10.2 with consume the factor and equal 0.002, resistance value Z with following formula 2 (in fact formula 2 is identical with aforesaid formula 1, rearranges once at this for the ease of understanding again) the supposition relative metal level of the first signal lead layer S1 (being bus plane POWER) ₁Be 28 ohm (because circuit board is the symmetry structure, so Z ₁Equal the resistance value Z of the relative metal level of secondary signal routing layer S2 (ground plane GND) ₂) the anti-numerical value that pushes away live width W:

Z_{0} = \frac{87}{\sqrt{E + 1.41}} \ln {\frac{5.98 H 2}{0.8 W + T 1}}

Formula 2

Wherein: E=dielectric coefficient=10.2

The thickness of H2=first and the 3rd insulating barrier 11,13

Thickness=0.7mil of the T1=first signal lead layer S1

So according to aforesaid notion and data, the present invention utilizes above-listed mode after repeatedly testing, obtain in this embodiment, the live width W of first and second signal lead layer S1, S2 is reduced to 12mil, and be that 1 public affairs are decided ratio (for fear of factors such as mutual interference of signal phase and cross-talks) according to the public fixed live width of industry than line-spacing, line-spacing also is reduced to 12mil, thereby only needs 24mil (12mil+12mil=24mil) in first and second signal lead layer S1, the anti-cabling of each bar High speed and low resistance of the last layout of S2.

According to aforementioned, so the present invention has following advantage:

1. significantly dwindle the required live width of the anti-cabling of High speed and low resistance:

The minor insulation layer 11,13 of contiguous first and second signal lead layer S1 of change, S2 is by the insulating material (as the polytetrafluoroethylene of pottery filling) of the higher dielectric coefficient and the low consumption factor, so that the relative impedance Z of signal lead layer S1, S2 in this enforcement ₁, Z ₂Fall within 28 ± 10% ohm to the anti-cabling of High speed and low resistance that meets Ying Daier regulation, thereby obviously different public circuit board utilization increase live width W to 21mil reduces impedance, so the live width of the anti-cabling of High speed and low resistance in the present embodiment can significantly be reduced to 12mil, so the present invention can reach the goal of the invention of the width that reduces the anti-cabling of High speed and low resistance really.

2. the thickness of circuit board meets industrial standard:

Because in the present embodiment, need not adjust each

insulating barrier

11,12,13 thickness of circuit board, the thickness that makes its integrated circuit plate is still for being thickness (as 1.6mm) originally, meet industrial standard, so do not need excessively to change circuit board design originally in the present invention, can make the gross thickness of circuit board can meet industrial standard.

3. be applicable to high speed signal:

Because of resistance value Z ₁, Z ₂In 25.2～30.8 ohm of scopes of the theoretical resistance value of the anti-cabling of High speed and low resistance of internet regulation, so be applicable to the High speed and low resistance antinoise signal, the required cabling of the RAMBUS memory layout promoted mainly of internet for example, meeting now, manufacturing industry can improve the value of product and competitiveness toward the trend of high speed signal development.

4. meet economic benefits:

Owing to only need change the material of part pressing condition such as insulating barrier, can reach the desired resistance value of High speed and low resistance antinoise signal, and need not spend a large amount of manpowers, material resources, revise layout on the circuit board, the manpower and the material resources that can significantly reduce modification and spent, meet economic benefits to reach, and because live width is compared also can decline to a great extent (being reduced to 24mil by 42mil) with line-spacing with public circuit, thereby more can effectively utilize on the circuit board rare precious area, to improve positioning efficiency, more can meet today circuit board towards short and small frivolous trend development, make product more competitive.

It should be noted, the notion that the present invention makes the minor insulation layer of adjacent signal routing layer use higher dielectric coefficient and low consumption factor material and residue insulating barrier still to continue to use public glass reinforced epoxy also can be applicable in the circuit board of other kinds, to utilize the disclosed mode of aforementioned first embodiment, meet under the industrial standard in the circuit board gross thickness, reach anti-circuit theoretical value of High speed and low resistance and the advantage that does not excessively change circuit board script design condition that resistance value meets the internet regulation, should not be subject to four-layer circuit board, enumerate the circuit board explanation of several different numbers of plies now.

At first explanation is, circuit board is to carry out pressing with symmetrical structure, so for the convenience that designs, increasing progressively of the number of plies of circuit board is to increase so that even number is tired, as four-layer circuit board, 6-layer circuit board, 8-layer printed circuit board .. or the like, yet, increase along with the circuit board number of plies, the number of plies of signal lead layer also increases thereupon, for instance, when 6-layer circuit board, the signal lead layer that then has three layers or four layers, and may not need all signal lead layers all to be used for the anti-circuit of layout High speed and low resistance in the practical application, so can only to select one deck or the two-layer material of making that changes the insulating barrier that is right after it in these signal lead layers in the design of circuit board be that the high-dielectric coefficient and the low consumption factor get final product.Moreover, if signal lead layer adjacent metal layers (being finger stratum or bus plane), then be suitable for the high speed signal of walking because of metal capture-effect or the like factor, so the present invention selects wherein one deck or even level to change its circuit characteristic from the signal lead layer of adjacent metal layers, so that it is more suitable for the anti-circuit of layout High speed and low resistance.Yet, select even number signal lead layer when laying the layer of High speed and low resistance antinoise signal at these signal lead layers that are arranged in a side of metal level, general to select center with respect to circuit board be that the signal lead layer of symmetrical layers is that good (first signal lead layer S1 of four-layer circuit board 1 and secondary signal routing layer S2 as described above) is to make things convenient for the circuit board pressing.

With reference to Fig. 4, be second preferred embodiment of the present invention.The circuit board 2 of this embodiment is a 6-layer circuit board, and wherein ground floor, the 3rd layer, the 4th layer are all signal lead layer S1, S2, S3, S4 with layer 6, and the second layer is that ground plane GND and layer 5 are bus plane POWER.This circuit board 2 also has in order to support first insulating barrier 21, second insulating barrier 22, the 3rd insulating barrier 23, the 4th insulating barrier 24 and the 5th insulating barrier 25 of aforementioned each layer at interval.

In this embodiment, by aforementioned formula 2 as can be known, also as the aforementioned as first embodiment, the material that changes the first and the 5th insulating barrier 21,25 of contiguous outer signal lead layer S1, S4 (first and second signal lead layer S1, the S2 that refer to the circuit board 1 of first embodiment) is a high-dielectric coefficient and low consumption factor material (polytetrafluoroethylene of filling as pottery), the first and the 4th signal lead layer S1, S4 are changed over be suitable for cabling that the layout High speed and low resistance resists layer and have the advantage of previous embodiment concurrently.

Simultaneously with reference to Fig. 5, about the two adjacent signal lead layer S2 that are folded in two metal levels (being ground plane GND and bus plane POWER), the relative impedance of S3, because condition is identical, the relative impedance Z of stratum GND and bus plane POWER so secondary signal routing layer S2 connects ₃Equal the connect relative impedance Z of stratum GND and bus plane POWER of the 3rd signal lead layer S3 ₄Both relative impedances can following formula 3 expressions, the thickness that skin (as first and second routing layer S1, S2) according to industry allocated circuit plate 2 at first is described is 0.7mil, and the thickness of internal layer (as first to the 3rd ground plane GND1-GND2, the second and the 3rd signal lead layer S2, S3 and bus plane POWER) is 1.4mil:

Z_{3} = \frac{80 [\frac{A}{4 (A + D + T_{2})}]}{\sqrt{E}} \ln {\frac{1.9 (2 A + T_{2})}{0.8 W + T_{2}}}

Formula 3

Wherein: E=dielectric coefficient=at this is 10.2

The thickness of the thickness of A=second insulating barrier=the 4th insulating barrier

T ₂=be positioned at the thickness of the secondary signal routing layer of internal layer

Thickness=the 1.4mil of=the three signal lead layer

The thickness of D=the 3rd insulating barrier

The W=live width

By in the above-mentioned formula as can be known along with the increase of dielectric coefficient E, then secondary signal routing layer S2 descends with the relative impedance of the 3rd signal lead layer S3 thereupon, thereby can utilize the material of the high-dielectric coefficient and the low consumption factor to make second, the the 3rd and the 4th insulating barrier 22,23,24, can make the second and the 3rd signal lead layer S2, the relative impedance of S3 descends, also need not increase live width and line-spacing thereupon, thereby in a second embodiment, also variable second, the the 3rd and the 4th insulating barrier 22,23,24 material is the material of the high-dielectric coefficient and the low consumption factor, make the second and the 3rd signal lead layer S2 of internal layer, S3 becomes can hang down live width, the anti-cabling of line-spacing layout High speed and low resistance, thereby also can reach the advantage of aforementioned first embodiment.

Moreover, as Fig. 6, be the third embodiment of the present invention.The circuit board 3 of this embodiment is 8-layer printed circuit boards, its ground floor, the 3rd layer, layer 6 and the 8th layer are the first, second, third and the 4th signal lead S1, S2, S3, S4 in regular turn, the second layer, the 4th layer and layer 7 are first, second and the 3rd ground plane GND1, GND2, GND3 in regular turn, and layer 5 is bus plane POWER.And insert and put respectively and support first to the 7th insulating barrier 31-37 of each layer in regular turn at each interlayer of circuit board 3.In this embodiment, according to the formula 2 of aforementioned first embodiment as can be known, the variable first and the 7th insulating

barrier

31,37 utilizes the insulating material (is the polytetrafluoroethylene that 10.2 pottery is filled as dielectric coefficient) of the high and low consumption factor of dielectric coefficient compared to other insulating barriers 32-36 (be as public dielectric coefficient 4.5 glass reinforced epoxy), make the first and the 4th signal lead layer S1, S4 for be fit to the anti-cabling of layout High speed and low resistance layer and reach the advantage of aforementioned first embodiment.

Perhaps, in conjunction with Fig. 7, illustrating that the second or the 3rd signal lead layer S2, S3 also can change in abutting connection with its insulating

barrier

32,33 or 35,35 makes it be fit to come the anti-cabling of layout High speed and low resistance with low live width and line-spacing, because circuit board 3 is the symmetry pressing, so the relative impedance Z of the relative first ground plane GND1 of secondary signal routing layer S2 and the second ground plane GND2 ₅The relative impedance Z of the relative bus plane POWER of=the three signal lead layer S3 and the 3rd ground plane GND3 ₆, the relative impedance Z of secondary signal routing layer S2 ₅Can following formula 4 expressions:

Z_{5} = \frac{60}{\sqrt{E}} \ln {\frac{4 B}{0.67 πW (0.8 + \frac{T}{W})}}

Formula 4

Wherein: E=dielectric coefficient=at this is 10.2

The W=live width

Thickness=1.4mil of T=secondary signal routing layer S2

Thickness between B=two metal levels

Thickness between=first and second ground plane GND1 and the GND2

By in the formula 4 as can be known along with the increase of dielectric coefficient E, the relative impedance Z of secondary signal routing layer S2 then ₅Descend thereupon, then need not increase live width W and reach Low ESR, thereby in this 3rd embodiment, except aforementioned the variable first and the 7th insulating barrier 31 of mentioning, 37 material is high-dielectric coefficient and low loss factors, select the first and the 4th signal lead layer S1, S4 comes outside the anti-cabling of layout High speed and low resistance, the also variable second and the 3rd insulating barrier 32, the 33 or the 5th and the 6th insulating barrier 35,36 material is the material (as the polytetrafluoroethylene of pottery filling) of the high-dielectric coefficient and the low consumption factor, so that the second or the 3rd signal lead layer S2, S3 can hang down live width and line-spacing comes the anti-cabling of layout High speed and low resistance, perhaps can change second simultaneously, three, five, six insulating barriers 32,33,35,36 is the material of the high-dielectric coefficient and the low consumption factor, make the second and the 3rd signal lead layer S2, but S3 is the anti-cabling of layout High speed and low resistance, thereby can select contiguous arbitrary or appoint the insulating layer material of binary signal routing layer make it be suitable for laying the anti-cabling of High speed and low resistance and can reach the advantage that aforementioned first embodiment is reached according to user's demand in the present embodiment.

In addition, as Fig. 8, be the fourth embodiment of the present invention.The circuit board 4 of this embodiment is ten layer circuit boards, its ground floor, the 3rd layer, the 4th layer, layer 7, the 8th layer are the first, second, third, fourth, the 5th and the 6th signal lead layer S1, S2, S3, S4, S5, S6 with the tenth layer in regular turn, the second layer, layer 5 and the 9th layer are first, second and the 3rd ground plane GND1, GND2, GND3 in regular turn, and layer 6 is the first bus plane POWER.And each interlayer of this circuit board 4 comes electrically interval and support with first to the 9th insulating barrier 41-49 in regular turn.In the present embodiment, because six layer signal routing layer S1-S6 are arranged, and each signal lead layer S1-S6 has at least one side to be right after metal level (bus plane or ground plane), in this embodiment, can make the dielectric coefficient of first insulating barrier 41 and the 9th insulating barrier 49 be higher than other insulating barriers 42-48 (polytetrafluoroethylene of filling as pottery), allow the first and the 6th signal lead layer S1, the anti-cabling of S6 layout High speed and low resistance; Perhaps, make the dielectric coefficient of second, third and the 4th insulating barrier 42,43,44 be higher than the dielectric coefficient of other insulating barriers 41,45-49, allow secondary signal routing layer S2 and the 3rd signal lead layer S3 be suitable for the anti-circuit of layout High speed and low resistance; Perhaps, make the 6th, the 7th and the 8th insulating barrier 46,47,48 use dielectric coefficients to be higher than the material (polytetrafluoroethylene of filling as pottery) of other insulating barriers 41-45,49 dielectric coefficient, allow the 4th and the 5th signal lead layer S4, S5 be suitable for the anti-circuit of layout High speed and low resistance, and explanation and the formula 2,3 of aforementioned first embodiment of foundation, the various changes of provable aforementioned present embodiment can both have the advantage of first embodiment.

Moreover, as Fig. 9, be the fifth embodiment of the present invention.This embodiment is a Floor 12 circuit board 5, its ground floor, the 3rd layer, layer 6, layer 7, the tenth layer are the first, second, third, fourth, the 5th and the 6th signal lead layer S1, S2, S3, S4, S5, S6 with Floor 12 in regular turn, the second layer, layer 5, the 9th layer are the first, second, third and the 4th ground plane GND1, GND2, GND3, GND4 with eleventh floor in regular turn, and the 4th layer and the 8th layer is first and second bus plane POWER1, POWER2 in regular turn.Each interlayer of this circuit board 5 supports at interval with the first to the 11 insulating barrier 51-61 in regular turn.According to aforesaid explanation as can be known, in the present embodiment, be to allow the dielectric coefficient of the first and the 11 insulating barrier 51,61 be higher than the dielectric coefficient of other insulating barriers 52-60, so that the first and the 6th signal lead layer S1, S6 are suitable for low live width and the anti-cabling of line-spacing layout High speed and low resistance; Perhaps in order to allow the second or the 5th signal lead layer S2, S5 be suitable for the anti-cabling of layout High speed and low resistance, the material that then makes the second and the 3rd insulating barrier 52,53 or the 9th and the tenth insulating barrier 59,60 is the dielectric coefficient material that is higher than other insulating barriers 51,54-58,61 dielectric coefficient (polytetrafluoroethylene of filling as pottery), or makes the second and the 5th signal lead layer S2, S5 be suitable for the anti-cabling of layout High speed and low resistance simultaneously also can; Also or, can make the dielectric coefficient of the 5th, the 6th and the 7th insulating barrier 55,56,57 be higher than the dielectric coefficient of other insulating barriers 54-54,58-61, so that the anti-cabling of the 3rd and the 4th signal lead layer 53,54 energy layout High speed and low resistance, and various enforcement aspects in this embodiment all can reach the effect of aforementioned first embodiment.

At last, as Figure 10, be the sixth embodiment of the present invention.This embodiment is ten 6-layer circuit boards 7, its ground floor, the 3rd layer, layer 6, layer 7, the tenth layer, eleventh floor, the 14 layer are the first, second, third, fourth, the 5th, the 6th, the 7th and the 8th signal lead layer S1-S8 with the 16 layer in regular turn, the second layer, layer 5, the 9th layer, the 13 layer are the first, second, third, fourth and the 5th ground plane GND1-GND5 with the 15 layer in regular turn, and the 4th layer, the 8th layer and Floor 12 are first, second and the 3rd bus plane POWER1, POWER2, POWER3 in regular turn.Each interlayer of this circuit board 7 also comes at interval each other with the first to the 15 insulating barrier 71-85 in regular turn.In the present embodiment, can make the dielectric coefficient of first insulating barrier 71 and the 15 insulating barrier 85 be higher than other insulating barriers 72-84, so that the first signal lead layer S1 and the 8th signal lead layer S8 are suitable for low live width, the anti-cabling of line-spacing layout High speed and low resistance; Perhaps, the second and the 3rd insulating barrier 72,73 or the 13 and the 14 insulating barrier 83,84 are used compared to other insulating barriers 71,74-82,85 materials as higher dielectric coefficient (polytetrafluoroethylene that pottery is filled), so that the second or the 7th signal lead layer S2, S7 are suitable for also or simultaneously making the second and the 7th signal lead layer S2, S7 can hang down live width, the anti-cabling of line-spacing layout High speed and low resistance with low live width, the anti-cabling of line-spacing layout High speed and low resistance; Perhaps, make the dielectric coefficient of the 5th, the 6th and the 7th insulating barrier 75,76,77 or the 9th, the tenth and the 11 insulating barrier 79,80,81 be higher than the dielectric coefficient of other insulating barriers 71-74,78,82-85, so that the 3rd and the 4th signal lead layer S3, S4 or the 5th and the 6th signal lead layer S5, S6 can hang down live width, the anti-cabling of line-spacing layout High speed and low resistance, also can make the 3rd, the 4th, the 5th and the 6th signal lead layer S3, S4, S5, S6 all can hang down live width, the anti-cabling of line-spacing layout High speed and low resistance.The various forms of implementation of this embodiment also should have the advantage of first embodiment simultaneously.

It should be noted, because aforementioned second to the 6th embodiment insulating barrier that all can use the higher dielectric coefficient and the low consumption factor changes the circuit characteristic of signal lead layer, meet industrial standard, be suitable for high speed signal, meet advantage such as economic benefits so all can reach the thickness that significantly dwindles the required live width of the anti-cabling of High speed and low resistance and line-spacing, circuit board.

The above, it only is preferred embodiment of the present invention, when not limiting scope of the invention process with this, promptly the simple equivalent of doing according to claim scope of the present invention and description generally changes and modifies, and all should still belong in the scope that claim of the present invention contains.

Claims

1. one kind is utilized the insulating material of high-dielectric coefficient to reduce the high speed circuit board of walking line impedence, this circuit board comprises at least two metal levels and at least two signal lead layers, metal level in this at least two metal level is used separately as ground plane and bus plane, and the layer in two outsides of this circuit board is respectively this signal lead layer, and insert and put an insulating barrier respectively to isolate in each interlayer of aforementioned circuit plate, it is characterized in that:

The dielectric coefficient of the insulating barrier of one side of at least one metal level in this metal level in this circuit board is one first dielectric coefficient, and the insulating layer material of opposite side to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, and be that the non-opposite side that joins with this at least one metal level is in the described signal lead layer one in the insulating barrier of this second dielectric coefficient, to reduce the cabling live width and the line-spacing of this signal lead layer.

2. a kind of insulating material of high-dielectric coefficient that utilizes as claimed in claim 1 reduces the high speed circuit board of walking line impedence, this circuit board is a four-layer circuit board, first and four layer of this circuit board is that ground plane and the 3rd layer are bus plane for first and second signal lead layer, the second layer in regular turn, and this circuit board has the 3rd insulating barrier between the 3rd and four layer at this circuit board of second insulating barrier and between first insulating barrier between first and two layer of this circuit board, second and three layer at this circuit board, wherein:

The dielectric coefficient of this second insulating barrier is one first dielectric coefficient, and this first with the 3rd insulating layer material be that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this first and second signal lead layer.

3. a kind of insulating material of high-dielectric coefficient that utilizes as claimed in claim 1 reduces the high speed circuit board of walking line impedence, this circuit board is a 6-layer circuit board, the ground floor of this circuit board, the 3rd layer, the 4th layer is first with layer 6 in regular turn, second, the the 3rd and the 4th signal lead layer, layer 5 is that the bus plane and the second layer are ground plane, this bus plane and this ground plane are metal level, and this circuit board has one at the ground floor of this circuit board and first insulating barrier between the second layer, one second insulating barrier between the second layer of this circuit board and the 3rd layer, one the three-layer insulated layer between the 3rd layer and the 4th layer of this circuit board, one the 4th insulating barrier and between the 4th layer of this circuit board and layer 5 is at the layer 5 of this circuit board and the 5th insulating barrier between the layer 6, wherein:

4. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 3 reduces the high speed circuit board of walking line impedence, wherein, this second, third and the dielectric coefficient of the 4th insulating barrier be one first dielectric coefficient, this first and pentasyllabic quatrain edge layer material be that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this first and the 4th signal lead layer.

5. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 3 reduces the high speed circuit board of walking line impedence, wherein, the dielectric coefficient of this first and the 5th insulating barrier is one first dielectric coefficient, and this second, third and the 4th insulating layer material be that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this second and the 3rd signal lead layer.

6. a kind of insulating material of high-dielectric coefficient that utilizes as claimed in claim 1 reduces the high speed circuit board of walking line impedence, this circuit board is a 8-layer printed circuit board, the ground floor of this circuit board, the 3rd layer, layer 6 and the 8th layer are first in regular turn, second, the the 3rd and the 4th signal lead layer, the second layer, the 4th layer is first with layer 7 in regular turn, the second and the 3rd ground plane and layer 5 are bus plane, these ground planes and bus plane are metal level, and this circuit board has one at the ground floor of this circuit board and first insulating barrier between the second layer, one second insulating barrier between the second layer of this circuit board and the 3rd layer, one the three-layer insulated layer between the 3rd layer and the 4th layer of this circuit board, one the 4th insulating barrier between the 4th layer of this circuit board and layer 5, one at the layer 5 of this circuit board and the 5th insulating barrier between the layer 6, one at the layer 6 of this circuit board and the 6th insulating barrier between the layer 7 and one at the 7th insulating barrier between the layer 7 of this circuit board and the 8th layer, wherein:

7. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 6 reduces the high speed circuit board of walking line impedence, wherein, this second, third, the dielectric coefficient of the 4th, the 5th and the 6th insulating barrier is one first dielectric coefficient, and this first and four-line poem with seven characters to a line edge layer material be that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this first and the 4th signal lead layer.

8. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 6 reduces the high speed circuit board of walking line impedence, wherein, the dielectric coefficient of this first, the 4th, the 5th, the 6th and the 7th insulating barrier is one first dielectric coefficient, and this second and the 3rd insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this secondary signal routing layer.

9. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 6 reduces the high speed circuit board of walking line impedence, wherein, the dielectric coefficient of this first, second, third, fourth and the 7th insulating barrier is one first dielectric coefficient, and the 5th and the 6th insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 3rd signal lead layer.

10. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 6 reduces the high speed circuit board of walking line impedence, wherein, the dielectric coefficient of this first, the 4th and the 7th insulating barrier is one first dielectric coefficient, and this second, third, the 5th and the 6th insulating layer material is that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this second and the 3rd signal lead layer.

11. a kind of insulating material of high-dielectric coefficient that utilizes as claimed in claim 1 reduces the high speed circuit board of walking line impedence, this circuit board is ten layer circuit boards, the ground floor of this circuit board, the 3rd layer, the 4th layer, layer 7, the 8th layer is first with the tenth layer in regular turn, second, the 3rd, the 4th, the the 5th and the 6th signal lead layer, layer 6 is a bus plane, and the second layer, layer 5 and the 9th layer are first in regular turn, the second and the 3rd ground plane, aforementioned ground plane and bus plane are metal level, and this circuit board has one at the ground floor of this circuit board and first insulating barrier between the second layer, one second insulating barrier between the second layer of this circuit board and the 3rd layer, one the 3rd insulating barrier between the 3rd layer and the 4th layer of this circuit board, one the 4th insulating barrier between the 4th layer of this circuit board and layer 5, one at the layer 5 of this circuit board and the 5th insulating barrier between the layer 6, one at the layer 6 of this circuit board and the 6th insulating barrier between the layer 7, one the 7th insulating barrier between the layer 7 of this circuit board and the 8th layer, one the 9th insulating barrier between the 8th insulating barrier between the 8th layer and the 9th layer of this circuit board and the 9th layer and the tenth layer at this circuit board, wherein:

12. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 11 reduces the high speed circuit board of walking line impedence, wherein, this second, third, the dielectric coefficient of the 4th, the 5th, the 6th, the 7th and the 8th insulating barrier is one first dielectric coefficient, and this first and the 9th insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this first and the 6th signal lead layer.

13. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 11 reduces the high speed circuit board of walking line impedence, wherein, the dielectric coefficient of this first, the 5th, the 6th, the 7th, the 8th and the 9th insulating barrier is one first dielectric coefficient, and this second, third and the 4th insulating layer material be that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this second and the 3rd signal lead layer.

14. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 11 reduces the high speed circuit board of walking line impedence, wherein, the dielectric coefficient of this first, second, third, fourth, the 5th and the 9th insulating barrier is one first dielectric coefficient, and the 6th, the 7th and the 8th insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 4th and the 5th signal lead layer.

15. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 11 reduces the high speed circuit board of walking line impedence, wherein, the dielectric coefficient of this first, the 5th and the 9th insulating barrier is one first dielectric coefficient, and this second, third, the 4th, the 6th, the 7th and the 8th insulating layer material is that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, with reduce this second, third, the cabling live width and the line-spacing of the 4th and the 5th signal lead layer.

16. a kind of insulating material of high-dielectric coefficient that utilizes as claimed in claim 1 reduces the high speed circuit board of walking line impedence, this circuit board is the Floor 12 circuit board, the ground floor of this circuit board, the 3rd layer, layer 6, layer 7, the tenth layer is first with Floor 12 in regular turn, second, the 3rd, the 4th, the the 5th and the 6th signal lead layer, the 4th layer is first and second bus plane with the 8th layer in regular turn, and the second layer, layer 5, the 9th layer is first with eleventh floor in regular turn, second, the the 3rd and the 4th ground plane, this bus plane and ground plane are metal level, and this circuit board has one at the ground floor of this circuit board and first insulating barrier between the second layer, one second insulating barrier between the second layer of this circuit board and the 3rd layer, one the 3rd insulating barrier between the 3rd layer and the 4th layer of this circuit board, one the 4th insulating barrier between the 4th layer of this circuit board and layer 5, one at the layer 5 of this circuit board and the 5th insulating barrier between the layer 6, one at the layer 6 of this circuit board and the 6th insulating barrier between the layer 7, one the 7th insulating barrier between the layer 7 of this circuit board and the 8th layer, one the 8th insulating barrier between the 8th layer and the 9th layer of this circuit board, one the 9th insulating barrier between the 9th layer and the tenth layer of this circuit board, one the tenth insulating barrier and between the tenth layer of this circuit board and eleventh floor is at the eleventh floor of this circuit board and the 11 insulating barrier between the Floor 12, wherein:

17. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 16 reduces the high speed circuit board of walking line impedence, wherein, this second, third, the dielectric coefficient of the 4th, the 5th, the 6th, the 7th, the 8th, the 9th and the tenth insulating barrier is one first dielectric coefficient, this the first and the 11 insulating layer material is that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this first and the 6th signal lead layer.

18. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 16 reduces the high speed circuit board of walking line impedence, wherein, this first, the 4th, the 5th, the 6th, the 7th, the 8th, the 9th, the tenth and the dielectric coefficient of the 11 insulating barrier be one first dielectric coefficient, this the second and the 3rd insulating layer material is that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this secondary signal routing layer.

19. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 16 reduces the high speed circuit board of walking line impedence, wherein, this first, second, third, fourth, the 5th, the 6th, the 7th, the 8th and the dielectric coefficient of the 11 insulating barrier be one first dielectric coefficient, the the 9th and the tenth insulating layer material is that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 5th signal lead layer.

20. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 16 reduces the high speed circuit board of walking line impedence, wherein, this first, the 4th, the 5th, the 6th, the 7th, the 8th and the dielectric coefficient of the 11 insulating barrier be one first dielectric coefficient, and this second, third, the 9th and the tenth insulating layer material is that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this second and the 5th signal lead layer.

21. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 16 reduces the high speed circuit board of walking line impedence, wherein, this first, second, third, fourth, the 8th, the 9th, the tenth and the dielectric coefficient of the 11 insulating barrier be one first dielectric coefficient, five, the 6th and four-line poem with seven characters to a line edge layer material be that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 3rd and the 4th signal lead layer.

22. a kind of insulating material of high-dielectric coefficient that utilizes as claimed in claim 1 reduces the high speed circuit board of walking line impedence, this circuit board is ten 6-layer circuit boards, the ground floor of this circuit board, the second layer, the 3rd layer, layer 6, layer 7, the tenth layer, eleventh floor, the 14 layer is first with the 16 layer in regular turn, second, the 3rd, the 4th, the 5th, the 6th, the the 7th and the 8th signal lead layer, the 4th layer, the 8th layer is first with Floor 12 in regular turn, the second and the 3rd bus plane, and the second layer, layer 5, the 9th layer, the 13 and the 15 layer be first in regular turn, second, the 3rd, the the 4th and the 5th ground plane, this bus plane and ground plane are metal level, and this circuit board has one at the ground floor of this circuit board and first insulating barrier between the second layer, one second insulating barrier between the second layer of this circuit board and the 3rd layer, one the 3rd insulating barrier between the 3rd layer and the 4th layer of this circuit board, one the 4th insulating barrier between the 4th layer of this circuit board and layer 5, one at the layer 5 of this circuit board and the 5th edge layer between the layer 6, one at the layer 6 of this circuit board and the 6th insulating barrier between the layer 7, one the 7th insulating barrier between the layer 7 of this circuit board and the 8th layer, one the 8th insulating barrier between the 8th layer and the 9th layer of this circuit board, one the 9th insulating barrier between the 9th layer and the tenth layer of this circuit board, one the tenth insulating barrier between the tenth layer of this circuit board and eleventh floor, one at the eleventh floor of this circuit board and the 11 insulating barrier between the Floor 12, one the 12 insulating barrier between the Floor 12 of this circuit board and the 13 layer, one the 13 insulating barrier between the 13 layer and the 14 layer of this circuit board, one the 15 insulating barrier between the 15 layer and the 16 layer of the 14 insulating barrier and between the 14 layer and the 15 layer of this circuit board at this circuit board, wherein:

23. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 22 reduces the high speed circuit board of walking line impedence, wherein, this second, third, the the the the the 4th, the 5th, the 6th, the 7th, the 8th, the 9th, the tenth, the 11, the 12, the 13 and the dielectric coefficient of the 14 insulating barrier be one first dielectric coefficient, and this first and the tenth pentasyllabic quatrain edge layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this first and the 8th signal lead layer.

24. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 22 reduces the high speed circuit board of walking line impedence, wherein, this first, the 4th, the 5th, the 6th, the 7th, the 8th, the 9th, the tenth, the 11, the 12, the 13, the 14 and the dielectric coefficient of the 15 insulating barrier be one first dielectric coefficient, and this second and the 3rd insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this secondary signal routing layer.

25. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 22 reduces the high speed circuit board of walking line impedence, wherein, this first, second, third, fourth, the 5th, the 6th, the 7th, the 8th, the 9th, the tenth, the 11, the 12 and the dielectric coefficient of the 15 insulating barrier be one first dielectric coefficient, and the 13 and the 14 insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 7th signal lead layer.

26. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 22 reduces the high speed circuit board of walking line impedence, wherein, this first, the 4th, the 5th, the 6th, the 7th, the 8th, the 9th, the tenth, the 11, the 12 and the dielectric coefficient of the 15 insulating barrier be one first dielectric coefficient, and this second, third, the 13 and the 14 insulating layer material is that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of this second and the 7th signal lead layer.

27. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 22 reduces the high speed circuit board of walking line impedence, wherein, this first, second, third, fourth, the 8th, the 9th, the tenth, the 11, the 12, the 13, the 14 and the dielectric coefficient of the 15 insulating barrier be one first dielectric coefficient, and the 5th, the 6th and four-line poem with seven characters to a line edge layer material be that the low consumption factor and its dielectric coefficient are one to be higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 3rd and the 4th signal lead layer.

28. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 22 reduces the high speed circuit board of walking line impedence, wherein, this first, second, third, fourth, the 5th, the 6th, the 7th, the 8th, the 12, the 13, the 14 and the dielectric coefficient of the 15 insulating barrier be one first dielectric coefficient, and the 9th, the tenth and the 11 insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 5th and the 6th signal lead layer.

29. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 22 reduces the high speed circuit board of walking line impedence, wherein, this first, second, third, fourth, the 8th, the 12, the 13, the 14 and the dielectric coefficient of the 15 insulating barrier be one first dielectric coefficient, and the 5th, the 6th, the 7th, the 9th, the tenth and the 11 insulating layer material to be the low consumption factor and its dielectric coefficient be one is higher than second dielectric coefficient of this first dielectric coefficient, to reduce the cabling live width and the line-spacing of the 3rd, the 4th, the 5th and the 6th signal lead layer.

30. reduce the high speed circuit board of walking line impedence as each the described insulating material of high-dielectric coefficient that utilizes in the claim 1 to 29, wherein, this first dielectric coefficient is 4.5.

31. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 30 reduces the high speed circuit board of walking line impedence, wherein, this second dielectric coefficient is greater than 4.5.

32. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 30 reduces the high speed circuit board of walking line impedence, wherein, and for the material of the insulating barrier of this first dielectric coefficient is a glass reinforced epoxy.

33. the insulating material of high-dielectric coefficient that utilizes as claimed in claim 31 reduces the high speed circuit board of walking line impedence, wherein, and for the material of the insulating barrier of this second dielectric coefficient is the polytetrafluoroethylene that pottery is filled.