CN118264101A - Charge pump and control circuit thereof - Google Patents
Charge pump and control circuit thereof Download PDFInfo
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- CN118264101A CN118264101A CN202211680355.0A CN202211680355A CN118264101A CN 118264101 A CN118264101 A CN 118264101A CN 202211680355 A CN202211680355 A CN 202211680355A CN 118264101 A CN118264101 A CN 118264101A
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Abstract
The invention discloses a charge pump and a control circuit thereof, wherein the control circuit comprises: the system comprises an LDO module, a charge pump module, a clock driving module, an error amplifying module, a voltage dividing module and a switch module, wherein the LDO module is used for carrying out step-down processing on input power supply voltage and inputting stable voltage to the charge pump module and the clock driving module. The invention makes up that the output of the charge pump in the clock switching mode in the prior art can generate great noise when the charge pump is applied to a wide-voltage power supply, optimizes the input voltage of the charge pump module by using the LDO module, can effectively reduce the noise output by the charge pump module, and maintains the characteristics of quick response and low power consumption of the charge pump in the clock switching mode.
Description
Technical Field
The present invention relates to electronic circuits, and more particularly to a charge pump and a control circuit therefor.
Background
The charge pump can be connected to various dc power supply devices to supply a boosted voltage, and low power consumption is a target pursued in increasingly slim and high-performance electronic devices. In order to reduce the power consumption of charge pumps, clock-switching mode charge pumps are becoming a preference in the industry.
The charge pump of the clock switch mode has fast response and low power consumption, but when the charge pump is applied to a wide voltage domain, when the input voltage fluctuates and is close to the set output voltage of the charge pump, the output voltage of the charge pump can generate great noise, and the service performance of the charge pump of the clock switch mode is greatly reduced.
Disclosure of Invention
The invention aims to solve the technical problem that the output of a clock switch mode charge pump in the prior art generates great noise when the clock switch mode charge pump is applied to a wide voltage domain, so that the stability of a circuit is reduced, and provides the clock switch mode charge pump with the wide voltage domain output and low noise and a control circuit thereof.
The invention solves the technical problems by the following technical scheme:
the first aspect of the present invention provides a control circuit of a charge pump, the control circuit including an LDO (low dropout regulator) module, a charge pump module, a clock driving module, an error amplifying module, a voltage dividing module, and a switching module;
The input end of the LDO module is connected with the power supply voltage, and the output end of the LDO module is respectively connected with the input end of the charge pump module and the input end of the clock driving module; the output end of the charge pump module is connected with the input end of the error amplifying module through the voltage dividing module; the output end of the error amplification module is connected with the input end of the switch module; the output end of the switch module is connected with the charge pump module through the clock driving module;
The LDO module is used for carrying out step-down processing on the input power supply voltage and outputting stable voltage to the charge pump module and the clock driving module, wherein the stable voltage is smaller than the set output voltage of the charge pump module, and the difference value between the stable voltage and the set output voltage is larger than a set value;
when the clock driving module outputs a clock control signal to the charge pump module, the charge pump module is used for carrying out boosting treatment on the voltage output by the LDO module until the output voltage of the charge pump module reaches the set output voltage;
the voltage dividing module is used for dividing the output voltage of the charge pump module and outputting the divided voltage to the error amplifying module;
the error amplification module is used for comparing the divided voltage with a reference voltage and outputting a level signal according to a comparison result to control the working state of the switch module;
The switch module is used for outputting an external clock signal to the clock driving module according to the level signal output by the error amplifying module;
The clock driving module is used for outputting the clock control signal to the charge pump module according to the stable voltage output by the LDO module and the external clock signal.
Preferably, when the output voltage of the charge pump module does not reach the set output voltage, the divided voltage is smaller than the reference voltage, and the error amplifying module outputs a high-level signal to the enabling end of the switch module; when the output voltage of the charge pump module reaches or exceeds the set output voltage, the divided voltage is equal to or greater than the reference voltage, and the error amplification module outputs a low-level signal to the enabling end of the switch module.
Preferably, the switch module comprises a logic AND gate; the enabling end of the logic AND gate is used for receiving the level signal output by the error amplifying module, and the input end of the logic AND gate is used for receiving the external clock signal.
Preferably, the clock control signal output by the clock driving module to the charge pump module includes a first clock signal and a second clock signal; the frequencies of the first clock signal and the second clock signal are the same as the external clock signal, and the phases of the first clock signal and the second clock signal are different.
Preferably, the voltage dividing module comprises a first resistor and a second resistor; one end of the first resistor is connected with the output end of the charge pump, and the other end of the first resistor is connected with the second resistor and the input end of the error amplifying module; the other end of the second resistor is grounded.
Preferably, the output end of the charge pump module is connected with a load capacitor and the load capacitor is grounded.
A second aspect of the invention provides a charge pump comprising the control circuit described above.
On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the invention.
The invention has the positive progress effects that: in the wide voltage domain, after the LDO module is used for carrying out step-down processing on the power supply voltage, a stable voltage is output, the stable voltage is smaller than the set output voltage of the charge pump module, and the difference value between the stable voltage and the set output voltage is larger than a set threshold value.
Drawings
Fig. 1 is a block diagram of a charge pump control circuit according to embodiment 1 of the present invention.
Fig. 2 is a circuit diagram of a charge pump control circuit according to embodiment 1 of the present invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
The embodiment provides a control circuit of a charge pump, as shown in fig. 1, which comprises an LDO module 1, a charge pump module 2, a clock driving module 3, an error amplifying module 4, a switch module 5 and a voltage dividing module 6.
As shown in fig. 1, the input end of the LDO module 1 is connected with a power supply voltage VCC, and the output end of the LDO module 1 is respectively connected with the input end of the charge pump module 2 and the input end of the clock driving module 3; the output end of the charge pump module 2 is connected with the input end of the error amplifying module 4 through the voltage dividing module 6; the output end of the error amplification module 4 is connected with the input end of the switch module 5; the output end of the switch module 5 is connected with the charge pump module 2 through the clock driving module 3;
Specifically, as shown in fig. 2, the error amplifying module 4 includes an error amplifier 7 (i.e., EA in fig. 2), the voltage dividing module 6 includes a first resistor R1 and a second resistor R2, and the switching module 5 includes a logic and gate 8.
Specifically, as shown in fig. 2, the output terminal of the CHARGE PUMP module 2 (i.e., CHARGE PUMP in fig. 2) is electrically connected to the negative input terminal of the error amplifier 7 through the first resistor R1; the output end of the error amplifier 7 is electrically connected with the enabling end of the logic AND gate 8; the output end of the logic AND gate 8 is electrically connected with the charge pump module 2 through the CLOCK driving module 3 (i.e. CLOCK DRIVER in fig. 2); the other end of the first resistor R1 is electrically connected with the second resistor R2 and the negative input end of the error amplifier 7 respectively; the other end of the second resistor R2 is grounded to the ground terminal VSS.
In this embodiment, when the power supply voltage VCC is 1.5V to 3.9V, the set output voltage of the charge pump module 2 is 2.5V, and if the power supply voltage VCC is directly input to the charge pump module 2, the output voltage of the charge pump module 2 is very noisy when VCC reaches a range of 2 to 3V; if the power supply voltage VCC is input to the charge pump module 2 and is processed by the LDO module 1, the VIN can be stabilized at 1V, so that the charge pump module 2 can output a low-noise voltage of 2.5V, thereby maintaining the low-noise output of the charge pump.
Specifically, the LDO module 1 steps down an input power supply voltage VCC to obtain a stable voltage VIN, and then outputs the VIN to the charge pump module 2 and the clock driving module 3, wherein VIN is smaller than a set output voltage of the charge pump module 2 and a difference between VIN and the set output voltage is larger than a set value; when the clock driving module 3 outputs the clock control signals CLK1 and CLK2 to the charge pump module 2, the charge pump module 2 is configured to boost the voltage VIN output by the LDO module 1 until the output voltage of the charge pump module 2 reaches the set output voltage.
Specifically, as shown in fig. 2, the first resistor R1 and the second resistor R2 are used for dividing the output voltage of the charge pump module 2, and outputting the obtained divided voltage Vfb to the negative input terminal of the error amplifier 7.
Specifically, as shown in fig. 2, a set reference voltage Vref is input to the positive input terminal of the error amplifier 7, the error amplifier 7 compares the divided voltage Vfb with the reference voltage Vref, and outputs a level signal clk_en according to the comparison result to control the operation state of the logic and gate 8.
Specifically, the error amplifier 7 operates on the principle that:
(1) When the output voltage of the charge pump module 2 does not reach the set output voltage, the divided voltage Vfb is smaller than the reference voltage Vref, and the error amplifier 7 outputs a high level signal, that is, clk_en=1, to the enable terminal of the logic and gate 8.
(2) When the output voltage of the charge pump module 2 reaches or exceeds the set output voltage, the divided voltage Vfb is equal to or greater than the reference voltage Vref, and the error amplifier 7 outputs a low level signal, that is, clk_en=0, to the enable terminal of the logic and gate 8.
Specifically, as shown in fig. 2, the input terminal of the logic and gate 8 is configured to receive the external clock signal CLK, and the logic and gate 8 outputs the external clock signal CLK to the clock driving module 3 according to the level signal clk_en output by the error amplifier 7 received by the enable terminal.
Specifically, the logical and gate 8 operates on the principle that:
(1) When the input of the enable terminal of the logic and gate 8 is a high level signal, i.e., clk_en=1, the logic and gate 8 can transmit the external clock signal CLK to the clock driving module 3, so that the clock driving module 3 operates normally.
(2) When the input of the enable terminal of the logic and gate 8 is a low level signal, that is, clk_en=0, the logic and gate 8 cannot transmit the external clock signal CLK to the clock driving module 3, and the clock driving module 3 stops operating.
It should be noted that in the switching module 5, the logic and gate 8 may be replaced by an external clock signal CLK and a switch controlled by the error amplifier 7.
Specifically, as shown in fig. 2, the clock driving module 3 is configured to output a clock control signal to the charge pump module 2 according to the regulated voltage VIN output by the LDO module 1 and the external clock signal CLK.
Specifically, as shown in fig. 2, the clock control signal output from the clock driving module 3 to the charge pump module 2 includes a first clock signal CLK1 and a second clock signal CLK2; the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are the same as the external clock signal CLK, and the phases of the first clock signal CLK1 and the second clock signal CLK2 are different.
Specifically, as shown in fig. 2, the output end of the charge pump module 2 is connected to a load capacitor C, and the other end of the load capacitor C is grounded.
In the wide voltage domain, after the step-down processing is performed on the power supply voltage VCC through the LDO module 1, a stable voltage VIN is output, the VIN is smaller than the set output voltage of the charge pump module 2, and the difference value between the VIN and the set output voltage is larger than a set threshold value.
Example 2
The present invention provides a charge pump including the charge pump control circuit as described in embodiment 1.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (7)
1.A control circuit for a charge pump, the control circuit comprising:
The device comprises an LDO module, a charge pump module, a clock driving module, an error amplifying module, a voltage dividing module and a switch module;
The input end of the LDO module is connected with the power supply voltage, and the output end of the LDO module is respectively connected with the input end of the charge pump module and the input end of the clock driving module; the output end of the charge pump module is connected with the input end of the error amplifying module through the voltage dividing module; the output end of the error amplification module is connected with the input end of the switch module; the output end of the switch module is connected with the charge pump module through the clock driving module;
The LDO module is used for carrying out step-down processing on the input power supply voltage and outputting stable voltage to the charge pump module and the clock driving module, wherein the stable voltage is smaller than the set output voltage of the charge pump module, and the difference value between the stable voltage and the set output voltage is larger than a set value;
when the clock driving module outputs a clock control signal to the charge pump module, the charge pump module is used for carrying out boosting treatment on the voltage output by the LDO module until the output voltage of the charge pump module reaches the set output voltage;
the voltage dividing module is used for dividing the output voltage of the charge pump module and outputting the divided voltage to the error amplifying module;
the error amplification module is used for comparing the divided voltage with a reference voltage and outputting a level signal according to a comparison result to control the working state of the switch module;
The switch module is used for outputting an external clock signal to the clock driving module according to the level signal output by the error amplifying module;
The clock driving module is used for outputting the clock control signal to the charge pump module according to the stable voltage output by the LDO module and the external clock signal.
2. The control circuit of a charge pump of claim 1, wherein the error amplification module comprises an error amplifier;
When the output voltage of the charge pump module does not reach the set output voltage, the divided voltage is smaller than the reference voltage, and the error amplification module outputs a high-level signal to the enabling end of the switch module;
When the output voltage of the charge pump module reaches or exceeds the set output voltage, the divided voltage is equal to or greater than the reference voltage, and the error amplification module outputs a low-level signal to the enabling end of the switch module.
3. The control circuit of a charge pump of claim 1, wherein the switch module comprises a logic and gate;
The enabling end of the logic AND gate is used for receiving the level signal output by the error amplifying module, and the input end of the logic AND gate is used for receiving the external clock signal.
4. The control circuit of claim 1, wherein the clock control signal output by the clock drive module to the charge pump module comprises a first clock signal and a second clock signal;
the frequencies of the first clock signal and the second clock signal are the same as the external clock signal, and the phases of the first clock signal and the second clock signal are different.
5. The control circuit of a charge pump of claim 1, wherein the voltage divider module comprises a first resistor and a second resistor;
one end of the first resistor is connected with the output end of the charge pump, and the other end of the first resistor is connected with the second resistor and the input end of the error amplifying module; the other end of the second resistor is grounded.
6. The control circuit of claim 1, wherein an output of the charge pump module is connected to a load capacitor and the load capacitor is grounded.
7. A charge pump comprising a control circuit as claimed in any one of claims 1 to 6.
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118264101A true CN118264101A (en) | 2024-06-28 |
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