CN118262755A

CN118262755A - Control circuit, peripheral circuit and operation method of control circuit

Info

Publication number: CN118262755A
Application number: CN202211686898.3A
Authority: CN
Inventors: 宋璧若; 王瑜
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Filing date: 2022-12-26
Publication date: 2024-06-28

Abstract

The embodiment of the application discloses a control circuit, a peripheral circuit and an operation method of the control circuit, and belongs to the technical field of storage. In an embodiment of the application, the control circuit is configured to: acquiring the current ambient temperature; determining a target supply voltage based on the current ambient temperature; determining a target regulation signal based on the target supply voltage; the target regulation signal is sent to the voltage regulation circuit to instruct the voltage regulation circuit to output a target supply voltage to the delay chain circuit. Based on the above, the control circuit can regulate the voltage VDD_dly output by the voltage regulating circuit to the delay chain circuit based on the current ambient temperature in the normal working process of the memory, thereby realizing the purpose of precisely controlling the transmission delay of the delay chain circuit.

Description

Control circuit, peripheral circuit and operation method of control circuit

Technical Field

The embodiment of the application relates to the technical field of storage, in particular to a control circuit, a peripheral circuit and an operation method of the control circuit.

Background

During operation of a memory such as a DRAM (dynamic random access memory ), control signals such as a row activate Command (Row Active Command) and a Read Command (Read Command) need to be executed in strict timing.

In the related art, a delay chain circuit is disposed in a peripheral circuit of a memory. The delay chain circuit comprises a plurality of delay units and a bypass gate circuit. In general, fine tuning control can be performed through a fine tuning control end in the bypass gate circuit to control the number of delay units of any control signal passing through the delay chain circuit, so as to realize delay transmission of the control signal.

The number of delay units in the delay chain circuit, through which any control signal passes, in the related art is obtained by testing when the memory leaves the factory, and the testing time is longer for the production process of the memory such as DRAM. Moreover, the bypass gate circuit requires a larger number of registers at the trim control end, which occupies a larger area of the DRAM chip.

Disclosure of Invention

The embodiment of the application provides a control circuit, a peripheral circuit and an operation method of the control circuit, which can control the delay of a delay chain circuit without adjusting a fine adjustment control end, thereby avoiding the problems of long test time and large occupied chip area of a register, and further ensuring the stability of the transmission delay of the delay chain circuit in the working process of a memory. The technical scheme is as follows:

In one aspect, a control circuit is provided, the control circuit is coupled to a control terminal of a voltage regulation circuit in a memory, and a voltage output terminal of the voltage regulation circuit is also coupled to a power supply input terminal of a delay chain circuit in the memory; wherein the control circuit is configured to:

Acquiring the current ambient temperature;

Determining a target power supply voltage based on the current ambient temperature;

Determining a target regulation signal based on the target supply voltage;

The target regulation signal is sent to the voltage regulation circuit to instruct the voltage regulation circuit to output the target power supply voltage to the delay chain circuit.

Optionally, the target power supply voltage has a positive correlation with the current ambient temperature.

Optionally, the control circuit stores a target mapping relationship, where the target mapping relationship indicates a relationship between a power supply voltage and a temperature loaded at a power supply input end of the delay chain circuit when a transmission delay of the delay chain circuit is stable;

The control circuit is configured to:

and determining the target power supply voltage based on the current environment temperature and the target mapping relation.

Optionally, the voltage output terminal of the voltage regulating circuit is further coupled with a power supply input terminal of an oscillating circuit in the memory;

the control circuit is further configured to:

Acquiring a first power supply voltage, wherein the first power supply voltage is a power supply voltage loaded at a power supply input end of the oscillating circuit under the condition that the temperature of the environment where the memory is located is a first temperature and the frequency of a clock signal generated by the oscillating circuit is a target clock frequency;

Acquiring a second power supply voltage, wherein the second power supply voltage is a power supply voltage loaded at a power supply input end of the oscillating circuit under the condition that the temperature of the environment where the memory is located is a second temperature and the frequency of a clock signal generated by the oscillating circuit is the target clock frequency;

the target map is determined based on the first power supply voltage, the second power supply voltage, the first temperature, and the second temperature.

Optionally, the first temperature is a lower boundary of a safe operating temperature range of the memory, and the second temperature is an upper boundary of the safe operating temperature range of the memory.

Optionally, the control circuit is configured to:

and if the current ambient temperature is within the safe working temperature range of the memory, determining the target power supply voltage based on the current ambient temperature and the target mapping relation.

Optionally, the control circuit is configured to:

And if the current environment temperature is not in the safe working temperature range of the memory and the current environment temperature is lower than the lower boundary of the safe working temperature range, determining the target power supply voltage based on the lower boundary of the safe working temperature range and the target mapping relation.

Optionally, the control circuit is configured to:

And if the current ambient temperature is not located in the safe working temperature range of the memory and the current ambient temperature exceeds the upper boundary of the safe working temperature range, determining the target power supply voltage based on the upper boundary of the safe working temperature range and the target mapping relation.

Optionally, the control circuit is further coupled with a temperature acquisition circuit within the memory;

The control circuit is configured to:

And receiving the current ambient temperature acquired by the temperature acquisition circuit.

In another aspect, a peripheral circuit is provided, the peripheral circuit including any of the control circuits provided above, the peripheral circuit further including a power supply circuit and the delay chain circuit, the power supply circuit including the voltage regulation circuit;

The control circuit is configured to acquire a current ambient temperature, determine a target power supply voltage based on the current ambient temperature, determine a target regulation signal based on the target power supply voltage, and send the target regulation signal to the voltage regulation circuit;

The voltage regulating circuit is configured to receive the target regulating signal and output the target power supply voltage to the delay chain circuit through the voltage output terminal;

the delay chain circuit is configured to delay transmission of a control signal in response to the target power supply voltage.

The control circuit is configured to determine the target power supply voltage based on the current ambient temperature and the target map.

Optionally, the power supply circuit further includes an oscillating circuit:

the voltage regulating circuit is further configured to output a first power supply voltage to the delay chain circuit and the oscillating circuit through the voltage output terminal when the temperature of the environment where the memory is located is a first temperature, the oscillating circuit is configured to generate a clock signal corresponding to the first power supply voltage, and the voltage regulating circuit is further configured to receive a first regulating signal, and the first regulating signal is used for regulating the first power supply voltage so that the frequency of the clock signal reaches a target clock frequency;

The voltage regulating circuit is further configured to output a second power supply voltage to the delay chain circuit and the oscillating circuit through the voltage output terminal when the temperature of the environment where the memory is located is a second temperature, the oscillating circuit is configured to generate a clock signal corresponding to the second power supply voltage, and the voltage regulating circuit is further configured to receive a second regulating signal, and the second regulating signal is used for regulating the second power supply voltage so that the frequency of the clock signal reaches the target clock frequency;

The control circuit is configured to determine the target mapping relationship based on the adjusted first supply voltage, the adjusted second supply voltage, the first temperature, and the second temperature.

Optionally, the peripheral circuit further comprises a temperature acquisition circuit;

the temperature acquisition circuit is configured to acquire the current environment temperature and send the current environment temperature to the control circuit;

The control circuit is configured to receive the current ambient temperature.

In another aspect, a method of operating a control circuit is provided, the control circuit being any of the control circuits described above; the method comprises the following steps:

Acquiring the current ambient temperature;

Determining a target regulation signal based on the target supply voltage;

The determining a target supply voltage based on the current ambient temperature includes:

Optionally, a voltage output of the voltage regulating circuit is coupled to a power supply input of an oscillating circuit within the memory; the method further comprises the steps of:

Optionally, the control circuit determines the target power supply voltage based on the current ambient temperature and the target mapping relation, including:

The control circuit obtains the current ambient temperature, including:

In another aspect, there is provided a memory comprising:

A peripheral circuit as described in any one of the above aspects;

and a memory array coupled to the peripheral circuitry.

In another aspect, a storage system is provided, the storage system comprising:

a memory as in any one of the above aspects;

And a controller coupled to the memory and configured to control the memory.

In another aspect, an electronic product is provided, the electronic product comprising the storage system of any one of the preceding aspects.

In the embodiment of the application, the transmission delay of the delay chain circuit is considered to be easily influenced by the environmental temperature, and the difference between the testing environment of the off-chip testing device to the memory and the actual working environment of the memory can be larger. For example, an off-chip test device tests the voltage required at the supply input of the delay chain circuit in an environment at room temperature of 23 ℃, but the memory is actually operating in an environment at-10 ℃. Thus if the supply voltage tested by the photo-out test device directly supplies power to the delay chain circuit, it may result in a delay chain circuit whose transmission delay is not the expected transmission delay. Therefore, in the embodiment of the application, the control circuit adjusts the voltage VDD_dly output by the voltage adjusting circuit to the delay chain circuit based on the current ambient temperature in the normal working process of the memory, thereby realizing the purpose of precisely controlling the transmission delay of the delay chain circuit.

For any fixed delay chain circuit, the transmission delay of the delay chain circuit also becomes larger along with the rise of temperature, and when the voltage loaded at the power supply input end of the delay chain circuit is increased, the transmission delay of the delay chain circuit can be reduced, so that the voltage vdd_dly output by the voltage regulating circuit to the delay chain circuit can be regulated in real time based on the current environment temperature in order to keep the stability of the transmission delay of the delay chain circuit.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a memory 10 according to an embodiment of the present application;

fig. 2 is a schematic diagram of a peripheral circuit 102 according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a delay chain circuit 203 coupled by 2 delay cells 301 in series according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another delay chain circuit 203 according to an embodiment of the present application;

FIG. 5 is a timing diagram of implementing different delays through a delay chain circuit according to an embodiment of the present application;

Fig. 6 is a schematic circuit diagram of a power supply circuit 201 according to an embodiment of the present application;

Fig. 7 is a schematic diagram of a voltage adjusting circuit 601 according to an embodiment of the present application;

Fig. 8 is a schematic diagram of an oscillating circuit 602 according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a test device 90 coupled to circuitry in a memory 10 according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a simulation result provided by an embodiment of the present application;

FIG. 11 is a schematic flow chart of determining a target mapping relationship according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a control circuit for adjusting a voltage applied to a power supply input of a delay chain circuit according to an embodiment of the present application;

Fig. 13 is a schematic flow chart of adjusting the voltage vdd_dly applied to the power supply input terminal of the delay chain circuit 203 according to an embodiment of the present application;

FIG. 14 is a flowchart of a method of operation of a control circuit provided by an embodiment of the present application;

FIG. 15 is a schematic diagram of another peripheral circuit 102 according to an embodiment of the present application;

FIG. 16 is a block diagram of a storage system 160 provided by an embodiment of the present application;

FIG. 17 is a block diagram of another storage system 170 provided in an embodiment of the present application;

fig. 18 is a schematic structural diagram of an electronic device 180 according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings.

In embodiments of the present application, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms "first," "second," and the like, may be interchanged with one another in the specific order or sequence in which the embodiments of the application are described herein to be implemented in other than the order illustrated or described herein.

It should be appreciated that reference throughout this specification to "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in some embodiments" or "in other embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The memory and related circuits according to the embodiments of the present application are explained below.

Fig. 1 is a schematic diagram of a memory 10 according to an embodiment of the present application.

The Memory 10 in the embodiment of the present application may be a volatile Memory, such as a DRAM (dynamic Random Access Memory) or SRAM (Static Random-Access Memory) device. Alternatively, the Memory 10 may also be a nonvolatile Memory such as a ReRAM (Re-random access Memory, resistive random access Memory), EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE READ-Only Memory), flash Memory (which may also be considered as a subset of EEPROM), FRAM (ferromagnetic random access Memory, ferroelectric random access Memory), MRAM (Magnetic Random Access Memory, magnetoresistive random access Memory), or the like. Alternatively, the memory 10 may be other semiconductor elements capable of storing information. Wherein each type of memory may have a different configuration and will not be described in detail herein.

As shown in fig. 1, the memory 10 illustratively includes a memory array 101 and peripheral circuitry 102. Peripheral circuitry 102 is coupled to memory array 101.

In response to control signals received from the peripheral circuit 102, the memory array 101 may perform operations such as writing and reading data. In some embodiments, memory array 101 may comprise a plurality of memory cells. The embodiment of the present application does not limit the specific arrangement manner of the storage array 101.

In the process of the memory array 101 performing operations such as writing and reading data, the respective control signals transmitted from the peripheral circuit 102 to the memory array 101 need to be performed strictly at a certain timing to ensure smooth execution of the operations such as writing and reading data.

Taking a memory as an example of a DRAM, the DRAM is addressed in rows and columns according to a latency parameter (or timing parameter) for data access. In some embodiments, the delay parameters may include tRP (Row PRECHARGE TIMING, row precharge time) and tRCD (RAS to CAS DELAY TIMING, row column transition delay time). Where tRP can be understood as the time the row address controller is precharged. tRCD can be understood as the delay time of row addressing to column addressing.

When the address request triggers, the control circuit 102 in the DRAM is first precharged according to tRP, after which the DRAM initializes RAS (Row Address Strobe ) for data addressing. Where in data addressing, the DRAM addresses the row address first and then passes through the tRCD before accessing the exact address of the data via the CAS (Column Address Strobe ).

In some embodiments, the delay of the delay parameter of the DRAM may be implemented by a delay chain circuit in the peripheral circuit 102, i.e., the delay parameter of the DRAM may be determined by the delay chain circuit. Therefore, in the DRAM chip production process, it is important to control the delay of the delay chain circuit. Wherein, different delay parameters of the DRAM can be realized by different delay chain circuits.

The peripheral circuit will be described first. Fig. 2 is a schematic diagram of a peripheral circuit 102 according to an embodiment of the application. As shown in fig. 2, the peripheral circuit 102 includes a power supply circuit 201, a control circuit 202, and a delay chain circuit 203. The control circuit 202 is coupled to the power supply circuit 201 and the delay chain circuit 203, respectively, and the power supply circuit 201 is also coupled to the delay chain circuit 203.

Wherein the power supply circuit 201 is configured to supply power to the delay chain circuit 203. The control circuit 202 is used for controlling the voltage supplied from the power supply circuit 201 to the delay chain circuit 203, and for controlling the input of a control signal to the delay chain circuit 203 so that the control signal is transmitted to the memory array 101 through the delay chain circuit at a timing.

For the delay chain circuit 203, connection can be made by a delay cell and a bypass circuit of smaller size. Each delay unit may be used to generate a delay control signal having a phase difference from the initial control signal. Fig. 3 is a schematic diagram of a delay chain circuit 203 coupled by 2 delay cells 301 connected in series according to an embodiment of the present application. As shown in fig. 3, a single delay cell 301 may include two transistors 3011 coupled. Where Vcc represents a power supply voltage for supplying power to the delay element 301, and Vss represents ground. Vin represents the output voltage of the bypass circuit or the previous delay cell, and Vout represents the output voltage of the next delay cell.

Based on the description of the delay unit 301 shown in fig. 3, fig. 4 is a schematic circuit diagram of another delay chain circuit 203 according to an embodiment of the present application. The delay chain circuit 203 includes 4 delay cells 301 and a bypass circuit 302 (as illustrated within the dashed box) outside the 4 delay cells 301. The bypass circuit 302 may control the number of delay cells 301 through which the control signal received by the delay chain circuit 203 passes. The en_in shown in fig. 4 may be understood as an input signal of a control signal corresponding to a delay parameter to the delay chain circuit 203, and the en_dly_out may be understood as an output signal when the control signal is output from the delay chain circuit 203.

This control signal for en_in and en_dly_out can be further understood with reference to fig. 5. Fig. 5 is a timing diagram illustrating different delays implemented by a delay chain circuit according to an embodiment of the present application. It is understood that each memory cell in the memory array 101 is addressable by the intersection of a BL (bit line) and a WL (word line). WL is used to address row addresses and BL is used to address column addresses. Taking tRP as an example, the time between the rising edge of the control signal WL_precharge.en < m > and the rising edge of BL_sensing_en < m > in FIG. 5 can be understood as the timing tRP between the start time of the WL precharge control signal for the mth row and the start time of the BL sense control signal for the mth row.

Continuing with FIG. 4 as an example, in some scenarios, the number of delay units 301 through which any control signal passes is controlled by the bypass circuit 302, which can be adjusted by the fine control terminal Ctl < > shown in FIG. 4. For example, assume that 2 fine control terminals are taken as an example, and 2bits are used to indicate the level of the fine control terminals. When the bits of the trim control terminal Ctl <0> and the trim control terminal Ctl <1> are both 0, i.e., ctl <1:0> =00, the bypass circuit 302 can make the control signal en_dly_out not pass through the 4 delay units 301, and the delay time of the control signal output from the delay chain circuit 302 is the shortest. When the bits of the trim control terminal Ctl <0> and the trim control terminal Ctl <1> are both 1, i.e., ctl <1:0> =11, the bypass circuit 302 can make the control signal en_dly_out pass through the 4 delay units 301, and the delay time of the control signal output from the delay chain circuit 203 is the longest.

That is, the number of delay cells in a delay chain circuit 203 through which any control signal passes can control the delay of the delay chain circuit 203, and the smaller the number of delay cells 201 through which the control signal passes, the shorter the delay of the delay chain circuit 203.

However, the performance of the delay cells 301 in the delay chain circuit 203 is easily affected by the process corner variation of the process corner, so in order to accurately determine the number of delay cells 301 through which the control signal passes, when the memory is shipped, for any control signal, the number of delay cells 301 through which the control signal passes may be tested based on the delay parameter corresponding to the control signal, and the tested number may be written into a register at the trimming control end in the bypass gate circuit 302. After the memory leaves the factory, the number of delay units through which the control signal passes is controlled according to the number stored in the register.

The above-described method requires the number of delay units 301 through which the test control signal passes when the memory leaves the factory, and thus affects chip test and production efficiency due to the long test time. When the bit of the fine adjustment control terminal of any one of the delay chain circuits 203 is determined, the bit corresponding to the fine adjustment control terminal needs to be stored in a register of the memory. In the case where the number of delay cells 301 in the delay chain circuit 203 is large, the number of registers required for the memory is large, and the area occupied by the registers is large.

Based on this, in the embodiment of the application, considering that the power supply voltage of the delay chain circuit affects the transmission delay of the delay chain circuit, a power supply circuit can be designed for the delay chain circuit in a chip such as a memory, and the power supply voltage of the delay chain circuit is adjusted after the chip leaves the factory, so as to realize the delay of the delay chain circuit corresponding to different delay parameters. Compared with the mode of realizing delay chain delay through the fine adjustment control end, the embodiment of the application adopts the mode of adjusting the power supply voltage, and can provide different power supply voltages for delay chain circuits in different process angle ranges so as to realize delay parameters corresponding to different process angle ranges, the chip test process is simpler, the test efficiency of the chip is improved, and more registers are not needed to occupy the area of the chip.

Fig. 6 is a schematic circuit diagram of a power supply circuit 201 according to an embodiment of the present application.

The power supply circuit 201 includes a voltage adjusting circuit 601 and an oscillating circuit 602.

The voltage output terminal a of the voltage adjusting circuit 601 is coupled to the power supply input terminal B of the delay chain circuit 203, and the voltage output terminal a of the voltage adjusting circuit 601 is also coupled to the power supply input terminal E of the oscillating circuit 602.

Wherein the voltage regulating circuit 601 is configured to output the voltage vdd_dly to the delay chain circuit 203 and the oscillating circuit 602 through the voltage output terminal a.

The oscillation circuit 602 is configured to generate a clock signal Tclk corresponding to the voltage vdd_dly. Alternatively, the oscillating circuit 602 may generate a clock signal Tclk for indicating the voltage vdd_dly.

The voltage regulation circuit 601 is further configured to receive a regulation signal for regulating the voltage vdd_dly.

VDD is understood to be a power supply voltage for supplying power to the chip by an off-chip power supply device to which the power supply circuit 201 belongs. The supply voltage VDD provided by the off-chip supply device to the on-chip supply circuit 201 is fixed over the same process corner. Therefore, conversion of the fixed supply voltage VDD provided by the off-chip supply device into a supply voltage vdd_dly that can be adjusted can be achieved by the voltage adjusting circuit 601.

In some embodiments, in performing the chip test, the off-chip test apparatus may determine the adjustment signal output to the voltage adjustment circuit 601 according to whether the frequency of the clock signal Tclk for indicating the voltage vdd_dly reaches the target clock frequency, so that the voltage adjustment circuit 601 adjusts the voltage vdd_dly according to the received adjustment signal.

The use of the frequency of the clock signal Tclk to adjust the voltage vdd_dly is considered here if the frequency of the clock signal Tclk reaches the target clock frequency, in which case the corresponding delay parameters of the delay chain circuit 203 are different in different process corner ranges, and the delay of the delay chain circuit 203 may be achieved by the voltage vdd_dly supplying the delay chain circuit 203, for example, the higher the value of the voltage vdd_dly, the shorter the delay. Also, in the case where the voltage vdd_dly is simultaneously used to supply power to the oscillation circuit 602, the frequency of the clock signal Tclk output by the oscillation circuit 602 may reflect the voltage vdd_dly. Therefore, the application can realize the adjustment of the voltage VDD_dly supplied to the delay chain circuit 203 according to the frequency of the clock signal Tclk output by the oscillating circuit 602 by the testing device so as to meet the delay of the delay chain circuit 203 in different process angle ranges.

In addition, the specific structure of the voltage adjusting circuit 601 is not limited in the embodiment of the present application, and any circuit capable of implementing a voltage adjusting function may be used as the voltage adjusting circuit 601 provided in the embodiment of the present application. Fig. 7 is a schematic diagram illustrating a voltage adjusting circuit 601 according to an embodiment of the present application.

As shown in fig. 7, the voltage adjustment voltage 601 includes a first adjustable circuit 701 and a second adjustable circuit 702.

The first adjustable circuit 701 includes a first comparator 7011, a first switching device M1, a first resistor R1, and a first adjustable resistor R2; the first terminal a of the first switching device M1 is configured to input the power supply voltage signal VDD of the memory, the second terminal b of the first switching device is coupled to the output terminal c of the first comparator 7011, the third terminal d of the first switching device M1 is coupled to the first terminal e of the first resistor R1, the second terminal f of the first resistor R1 is coupled to the first terminal g of the first adjustable resistor R2, the second terminal h of the first adjustable resistor R2 is grounded, the non-inverting input terminal i of the first comparator 7011 is coupled between the second terminal f of the first resistor R1 and the first terminal g of the first adjustable resistor R2, and the inverting input terminal k of the first comparator 7011 is configured to input the reference voltage VBG.

In some embodiments, the reference voltage VBG may be provided by an on-chip reference voltage source.

The second adjustable circuit 702 includes a second comparator 7021, a second switching device M2, and a second adjustable resistor R3; the inverting input terminal l of the second comparator 7021 is coupled between the third terminal d of the first switching device M1 and the first terminal e of the first resistor R1, the non-inverting input terminal M of the second comparator 7021 is coupled between the first terminal n of the second switching device M2 and the first terminal o of the second adjustable resistor R3, the output terminal p of the second comparator 7021 is coupled with the second terminal q of the second switching device M2, the third terminal R of the second switching device M2 is configured to input the supply voltage signal VDD of the memory, the second terminal s of the second adjustable resistor R3 is grounded, and the first voltage output terminal a is coupled between the first terminal n of the second switching device M2 and the first terminal o of the second adjustable resistor R3.

In some embodiments, the first adjustable circuit 701 may be configured to receive an adjustment signal to adjust the size of the first adjustable resistor R2, thereby adjusting the voltage value of the reference voltage signal vdd_dly_ref output by the first adjustable circuit 701. The second adjustable circuit 702 may be configured to receive an adjustment signal to adjust the size of the second adjustable resistor R3, thereby adjusting the voltage vdd_dly output by the second adjustable circuit 702.

The adjustment of the magnitude of the voltage vdd_dly provided to the supply input of the delay chain circuit 203 is achieved by the first and second adjustable circuits 701, 702.

In addition, the specific structure of the oscillating circuit 602 is not limited in the embodiment of the present application, and any circuit capable of generating a clock signal may be used as the oscillating circuit 602 provided in the embodiment of the present application. Fig. 8 is a schematic diagram illustrating an oscillating circuit 602 according to an embodiment of the present application.

The oscillating circuit 602 may include at least one nand gate 801 and an even number of inverters 802 in series as shown in fig. 8. The signal osc_en input to the input terminal of the nand gate 801 can be understood as a driving signal input to the oscillation circuit 502. For example, when the level of osc_en is high, the oscillating circuit 502 may be driven to oscillate under the supply of the voltage vdd_dly, and output the clock signal Tclk to the off-chip testing device.

When the test device detects that the frequency of the clock signal Tclk reaches the target clock frequency, the delay chain circuit 203 may be powered with a voltage vdd_dly corresponding to the target clock frequency.

It will be appreciated that chips at different process corner ranges on the wafer may correspond to different target clock frequencies for reflecting the voltage vdd_dly required by the delay chain circuit 203 in the chips at different process corner ranges.

Once the voltage vdd_dly corresponding to the target clock frequency is determined, the voltage vdd_dly may be used to power the delay chain circuit 203 corresponding to the various delay parameters of the chip, respectively. The delay chain delay corresponding to the various delay parameters may be implemented by different delay chain circuits 203, for example, the number of delay cells 201 in the delay chain circuits 203 is different.

In this way, compared with the mode of realizing different delay parameters corresponding to delay chain delay through the fine tuning control ends in different delay chain circuits 203, the embodiment of the application does not need to control the delay of the delay chain circuits 203 through adjusting the fine tuning control ends, the delay of the delay chain circuits can be realized through adjusting the power supply voltage of the delay chain circuits 203, the chip test is realized more conveniently, and the test time of the chip can be reduced. Furthermore, the area of the chip occupied by the voltage adjusting circuit 601 and the oscillating circuit 602 is much smaller than that occupied by the register.

Fig. 9 is a schematic diagram of a circuit coupling between a testing device 90 and a memory 10 according to an embodiment of the present application. As shown in fig. 9, the test device 90 includes an interface circuit 901 and a processor 902, the interface circuit 901 and the processor 902 are coupled, a first terminal K of the interface circuit 901 is coupled to a clock output terminal L of the oscillating circuit 602 in the memory 10, a second terminal M of the interface circuit 901 is coupled to an input terminal N of the voltage regulating circuit 601 in the memory 10, and a third terminal O of the interface circuit 901 is coupled to a voltage output terminal a of the voltage regulating circuit 601 in the memory 10.

According to the description of the power supply circuit hereinabove, in some embodiments, the test device 90 may adjust the voltage vdd_dly output by the voltage output terminal a of the voltage adjustment circuit 601 through the second terminal M of the interface circuit 901, and scan the clock signal of the oscillating circuit 602 through the first terminal K in the interface circuit 901 to obtain the target clock frequency, i.e. the interface circuit 901 may be configured to receive the clock signal output by the clock output terminal L of the oscillating circuit 602 through the first terminal K of the interface circuit 901 and output the clock signal to the processor 902. The processor 902 may determine the adjustment signal according to the frequency of the clock signal, and output the adjustment signal to the voltage adjustment circuit 601 through the second terminal M of the interface circuit 901, so that the voltage adjustment circuit 601 adjusts the voltage vdd_dly output by the voltage output terminal a.

In addition, the test device 90 may also determine whether the voltage vdd_dly_is within the safe voltage threshold range by using the voltage vdd_dly_ outputted from the voltage output terminal a obtained from the third terminal O of the interface circuit 901.

Based on fig. 6-9, the supply voltage of the delay chain circuit 203 in the memory can be tested at the factory of the memory 10 to achieve the required transmission delay of the delay chain circuit 203. The voltage output by the voltage regulator circuit 601 to the delay chain circuit 203 may be controlled based on the pre-tested supply voltage during subsequent operation of the memory 10.

Further, in the embodiment of the present application, it is considered that the propagation delay of the delay chain circuit 203 is easily affected by the environmental temperature, and the difference between the testing environment of the off-chip testing device for the memory 10 and the actual operating environment of the memory 10 may be relatively large. For example, the off-chip test device tests the voltage required at the power supply input of delay chain circuit 203 in the above-described manner in an environment at room temperature of 23 ℃, but the memory is actually operating in an environment at-10 ℃. Thus if the supply voltage tested by the photo out test device directly supplies power to the delay chain circuit 203, it may result in a transmission delay of the delay chain circuit 203 that is not the expected transmission delay.

Based on this, in some embodiments, during operation of memory 10, control circuitry 202 is configured to: acquiring the current ambient temperature; determining a target supply voltage based on the current ambient temperature; determining a target regulation signal based on the target supply voltage; a target adjustment signal is sent to the voltage adjustment circuit 601 to instruct the voltage adjustment circuit 601 to output a target power supply voltage to the delay chain circuit 203.

Further, in the embodiment of the present application, in order to enable the control circuit 202 to control the voltage vdd_dly supplied by the voltage regulator circuit 601 to the delay chain circuit 203 based on the current ambient temperature during normal operation of the memory, when the memory leaves the factory for chip testing, the off-chip testing device may test vdd_dl at different ambient temperatures, so that the control circuit 202 determines the mapping relationship between vdd_dly and temperature based on vdd_dly at different ambient temperatures. Subsequently, during normal operation of memory 10, control circuitry 202 may determine vdd_dly that matches the current ambient temperature based on the mapping relationship.

For any fixed delay chain circuit 203, when the transmission delay of the delay chain circuit 203 is stable, the power supply voltage required to be loaded at the power supply input end of the delay chain circuit 203 and the temperature of the environment where the memory is located show a positive correlation. This is because the transmission delay of the delay chain circuit 203 increases with an increase in temperature, and when the voltage applied to the power supply input terminal of the delay chain circuit 203 is increased, the transmission delay of the delay chain circuit 203 can be reduced, so that the voltage applied to the power supply input terminal of the delay chain circuit 203 can be increased when the temperature increases in order to keep the transmission delay of the delay chain circuit 203 stable.

In order to illustrate the relationship between the propagation delay and the temperature of the delay chain circuit 203 and the voltage applied to the power supply input terminal, a simulation experiment was performed on the delay chain circuit 203. The simulation experiment includes the delay chain circuit 203 prepared under three processes including a fast (fast) process, a slow (slow) process, and a typical (typical) process.

And for the delay chain circuit under each process, testing the transmission delay of the delay chain circuit when the power supply input end of the delay chain circuit is loaded with different voltages under each of a plurality of environment temperatures. For example, 6 temperatures are selected as the ambient temperature between-25 ℃ and 100 ℃, and at each of the 6 ambient temperatures, 11 different voltages distributed at 0.7V to 1.2V are respectively loaded to the power supply input end of the delay chain circuit, and the transmission delay of the delay chain circuit at each voltage is tested. Thus, 11×6=66 simulation results can be obtained.

The simulation result analysis of the delay chain circuit under each process can find that the voltage loaded at the power supply input end of the delay chain circuit also presents an ascending trend along with the ascending of the temperature under the condition that the transmission delay of the delay chain circuit is stabilized at about 1.5E-08.

Further, another simulation experiment is performed on the delay chain circuit 203, and a test process of the simulation experiment includes: the propagation delay of the delay chain circuit 203 is fixed and then the supply voltage to be applied to the supply input of the delay chain circuit 203 is simulated at different ambient temperatures. Fig. 10 is a schematic diagram of a simulation result provided by an embodiment of the present application. As shown in fig. 10, in the case where the transmission delay of the delay chain circuit 203 is stable, the voltage vdd_dly required to be applied to the power supply input terminal of the delay chain circuit 203 has a linear positive correlation with the ambient temperature T.

Therefore, when the memory leaves the factory, the off-chip testing device can test vdd_dly at two different ambient temperatures, so that the mapping relationship between the power supply voltage required to be loaded at the power supply input end of the delay chain circuit 203 and the ambient temperature can be obtained.

Based on this, in some embodiments, the voltage adjustment circuit 601 is configured to output a first power supply voltage to the delay chain circuit 203 and the oscillating circuit 602 through the voltage output terminal a when the temperature of the environment in which the memory is located is a first temperature, the oscillating circuit 602 is configured to generate a clock signal corresponding to the first power supply voltage, and the voltage adjustment circuit 601 is further configured to receive a first adjustment signal for adjusting the first power supply voltage so that the frequency of the clock signal reaches the target clock frequency.

The voltage adjusting circuit 601 is further configured to output a second power supply voltage to the delay chain circuit 203 and the oscillating circuit 602 through the voltage output terminal a when the temperature of the environment in which the memory is located is a second temperature, the oscillating circuit 602 is configured to generate a clock signal corresponding to the second power supply voltage, and the voltage adjusting circuit 601 is further configured to receive a second adjusting signal for adjusting the second power supply voltage so that the frequency of the clock signal reaches the target clock frequency.

For the above-mentioned process of adjusting the first power supply voltage and the second power supply voltage, reference may be made to the above-mentioned related description about the voltage adjusting circuit 601, which is not repeated here.

Accordingly, the control circuit 202 is configured to determine the target mapping relationship based on the adjusted first supply voltage, the adjusted second supply voltage, the first temperature, and the second temperature. The target map may indicate a relationship between the power supply voltage applied to the power supply input B of the delay chain circuit 203 and the temperature in the case where the transmission delay of the delay chain circuit 203 is stable.

For example, based on the adjusted first supply voltage, the adjusted second supply voltage, the first temperature, and the second temperature, the determined target mapping may be expressed by the following formula:

wherein V1 represents a first power supply voltage, T1 represents a first temperature, V2 represents a second power supply voltage, and T2 represents a second temperature.

In addition, the off-chip testing device can select the first temperature and the second temperature for testing according to the safe working temperature range of the memory. The first temperature is illustratively the lower boundary of the safe operating temperature range of the memory and the second temperature is the upper boundary of the safe operating temperature range of the memory. In this scenario, the target mapping relationship may be expressed by the following formula:

Where Vmin represents a first power supply voltage, tmin represents a first temperature, and the first temperature is a lower boundary of a safe operating temperature range of the memory, vmax represents a second power supply voltage, tmax represents a second temperature, and the second temperature is an upper boundary of the safe operating temperature range of the memory.

Fig. 11 is a schematic flow chart of determining a target mapping relationship according to an embodiment of the present application. As shown in fig. 11, an adjustment signal (vdd_dly trim) is sent to the voltage adjustment circuit 601 in the power supply circuit by the off-chip test device to adjust the voltages output from the voltage adjustment circuit 601 to the delay chain circuit 203 and the oscillation circuit 602, respectively. Then, the temperature of the environment in which the memory is currently located is set, for example, the environment temperature t=tmin, and when the frequency of the clock signal of the oscillating circuit 602 reaches the target clock frequency, the off-chip testing device tests the voltage vdd_dly applied to the power supply input terminal of the delay chain circuit 203, so as to obtain vdd_dly corresponding to Tmin, and sends vdd_dly corresponding to Tmin to the control circuit.

Then, the temperature of the environment in which the memory is currently located is set, for example, the environment temperature t=tmax, and when the frequency of the clock signal of the oscillating circuit 602 reaches the target clock frequency, the off-chip testing device tests the voltage vdd_dly applied to the power supply input terminal of the delay chain circuit 203, so as to obtain vdd_dly corresponding to Tmax, and sends vdd_dly corresponding to Tmax to the control circuit.

The control circuit may calculate a target map based on vdd_dly corresponding to Tmin and vdd_dly corresponding to Tmax.

Alternatively, the off-chip testing device may also select two other temperatures to test vdd_dly corresponding to different temperatures, which are not illustrated here.

After the control circuit 202 obtains the target mapping relationship, the control circuit 202 may adjust the voltage output by the voltage adjusting circuit 601 in the power supply circuit 201 to the delay chain circuit 203 based on the current ambient temperature and the target mapping relationship in a subsequent process of the memory operation, so as to accurately control the transmission delay of the delay chain circuit 203.

Based on this, in some embodiments, the control circuitry 202 is configured to: and determining a target power supply voltage based on the current ambient temperature and the target mapping relation.

For example, when the target mapping relation is thatWhen the control circuit 202 obtains the current ambient temperature T, T may be substituted into the formula, and the output Vout is the target power supply voltage.

In addition, since the temperature used for calibrating the target mapping relationship is usually within the safe operating temperature range of the memory, when the control circuit determines the target power supply voltage based on the target mapping relationship, it can also be determined whether the current ambient temperature exceeds the safe operating temperature range of the memory.

Based on this, in some embodiments, the control circuitry 202 is configured to: and if the current ambient temperature is within the safe operating temperature range of the memory, determining a target power supply voltage based on the current ambient temperature and the target mapping relationship.

Accordingly, if the current ambient temperature is not within the safe operating temperature range of the memory and the current ambient temperature is below the lower boundary of the safe operating temperature range, a target supply voltage is determined based on the lower boundary of the safe operating temperature range and the target mapping relationship.

Accordingly, if the current ambient temperature is not within the safe operating temperature range of the memory and the current ambient temperature exceeds the upper boundary of the safe operating temperature range, a target supply voltage is determined based on the upper boundary of the safe operating temperature range and the target mapping relationship.

Fig. 12 is a schematic flow chart of a control circuit for adjusting a voltage applied to a power supply input terminal of a delay chain circuit according to an embodiment of the present application. As shown in fig. 12, during operation of the memory, the temperature acquisition circuit monitors the current ambient temperature T and sends the current ambient temperature T to the control circuit. Control circuit 202 determines whether current ambient temperature T is greater than Tmin and less than Tmax, and if this condition is satisfied, determines vdd_dly corresponding to current ambient temperature T from the target map, and takes this vdd_dly as the target power supply voltage.

Accordingly, if the current ambient temperature T does not satisfy the condition that is greater than Tmin and less than Tmax, the control circuit 202 continues to determine whether the current ambient temperature T is greater than Tmax, and if the current ambient temperature T is greater than Tmax, the maximum vdd_dly corresponding to Tmax in the target map is taken as the target power supply voltage. And if the current environment temperature T does not meet the condition of being greater than Tmax, taking the minimum VDD_dly corresponding to the Tmin in the target mapping relation as the target power supply voltage.

After determining the target power supply voltage, the control circuit 202 may send a target adjustment signal (vdd_dly trim) to the voltage adjustment circuit 601 based on the target power supply voltage to control the voltage output by the voltage adjustment circuit 601 to the power supply input terminal of the delay chain circuit 203 to be the target power supply voltage.

Alternatively, in other embodiments, the control circuit 202 may determine the target supply voltage directly based on the target map and the current ambient temperature without determining whether the current ambient temperature is outside the safe operating temperature range of the memory.

Alternatively, in other embodiments, the target mapping relationship may not be calibrated by the testing device in advance, in which case the target mapping relationship may be configured in the control circuit 202 by the relevant expert based on experience, which will not be described in detail herein.

Alternatively, in other embodiments, if the control circuit 202 does not have a target mapping relationship configured thereon, the control circuit 202 may further determine the target power supply voltage by means of a remote end, such as a cloud platform, when acquiring the current ambient temperature, which is not described in detail herein.

In addition, the control circuit 202 may acquire the current ambient temperature through a temperature acquisition circuit built in the chip, so as to reduce the cost of the embodiment of the present application. Based on this, in some embodiments, the control circuit is further coupled with an in-memory temperature acquisition circuit, at which time the temperature acquisition circuit is configured to: collecting the current environmental temperature and sending the current environmental temperature to a control circuit; a control circuit configured to receive a current ambient temperature.

Alternatively, the control circuit 202 may also obtain the current ambient temperature through an off-chip temperature sensing device, which is not limited in the embodiment of the present application.

Fig. 13 is a schematic flow chart of adjusting the voltage vdd_dly applied to the power supply input terminal of the delay chain circuit 203 according to an embodiment of the present application. As shown in fig. 13, when the temperature acquisition circuit acquires the current ambient temperature, the current ambient temperature is sent to the control circuit 202, and the control circuit 202 sends a target adjustment signal (vdd_dly trim) to the voltage adjustment circuit 601 in the power supply circuit 201 based on the current ambient temperature, so that the voltage adjustment circuit 601 adjusts the voltage vdd_dly applied to the power supply input terminal of the delay chain circuit 203, and the delay of the transmission of the control signal by the delay chain circuit 203 can be adjusted by vdd_dly.

In summary, in the embodiment of the present application, the control circuit 202 in the peripheral circuit 102 may adjust the voltage vdd_dly output by the voltage adjusting circuit 601 in the power supply circuit 201 to the delay chain circuit 203 based on the current ambient temperature during the normal operation of the memory 10, so as to achieve the purpose of precisely controlling the delay chain circuit 203.

Based on the foregoing, the embodiment of the present application further provides an operation method of the control circuit 202. Fig. 14 is a flowchart of an operation method of a control circuit according to an embodiment of the present application. As shown in fig. 14, the method includes the following steps.

Step 1401: the current ambient temperature is obtained.

Step 1402: a target supply voltage is determined based on the current ambient temperature.

Step 1403: the target regulation signal is determined based on the target supply voltage.

Step 1404: the target regulation signal is sent to the voltage regulation circuit to instruct the voltage regulation circuit to output a target supply voltage to the delay chain circuit.

Optionally, in some embodiments, the control circuit stores a target map indicating a relationship between a supply voltage applied to a supply input of the delay chain circuit and a temperature in a case where a transmission delay of the delay chain circuit is stable. In this scenario, the implementation of determining the target supply voltage based on the current ambient temperature may be: and determining a target power supply voltage based on the current ambient temperature and the target mapping relation.

Optionally, in some embodiments, a voltage output of the voltage regulating circuit is coupled to a power supply input of an oscillating circuit within the memory. In this scenario, the control circuit may further obtain a first power supply voltage, where the first power supply voltage is a power supply voltage loaded at a power supply input end of the oscillating circuit when the temperature of the environment where the memory is located is the first temperature and the frequency of the clock signal generated by the oscillating circuit is the target clock frequency; acquiring a second power supply voltage, wherein the second power supply voltage is a power supply voltage loaded at a power supply input end of the oscillating circuit under the condition that the temperature of the environment where the memory is located is a second temperature and the frequency of a clock signal generated by the oscillating circuit is a target clock frequency; the target map is determined based on the first supply voltage, the second supply voltage, the first temperature, and the second temperature.

Optionally, in some embodiments, the first temperature is a lower boundary of a safe operating temperature range of the memory and the second temperature is an upper boundary of the safe operating temperature range of the memory.

Optionally, in some embodiments, based on the current ambient temperature and the target mapping, the implementation of determining the target supply voltage may be: and if the current ambient temperature is within the safe operating temperature range of the memory, determining a target power supply voltage based on the current ambient temperature and the target mapping relationship.

Optionally, in some embodiments, based on the current ambient temperature and the target mapping, the implementation of determining the target supply voltage may be: if the current ambient temperature is not within the safe operating temperature range of the memory and the current ambient temperature is below the lower boundary of the safe operating temperature range, determining a target power supply voltage based on the lower boundary of the safe operating temperature range and the target mapping relationship.

Optionally, in some embodiments, based on the current ambient temperature and the target mapping, the implementation of determining the target supply voltage may be: if the current ambient temperature is not within the safe operating temperature range of the memory and the current ambient temperature exceeds the upper boundary of the safe operating temperature range, determining a target power supply voltage based on the upper boundary of the safe operating temperature range and the target mapping relationship.

Optionally, in some embodiments, the control circuit is further coupled with a temperature acquisition circuit within the memory. In this scenario, the implementation manner of the control circuit to obtain the current ambient temperature may be: and receiving the current ambient temperature acquired by the temperature acquisition circuit.

Detailed implementation of the foregoing embodiments may refer to the relevant content of fig. 1-13, and will not be described herein.

Fig. 15 is a schematic diagram of another peripheral circuit 102 according to an embodiment of the present application. As shown in fig. 15, the peripheral circuit 102 includes a sense amplifier and IO (input/output) circuit 121, a column decoder 122, a row decoder 123, a control logic unit 124, a refresh counter 125, a MUX (multiplexer) 126, a row address latch 127, a column address latch 128, a data input buffer (data input buffer) 129, and a data output buffer 130.

In addition, as shown in fig. 15, the peripheral circuit 102 further includes a power supply circuit 201 and a temperature acquisition circuit 131. It should be appreciated that in some examples, additional peripheral circuitry not shown in fig. 15 may also be included.

The control logic unit 124 is configured to parse a control signal sent by the external controller to trigger a read/write operation on the storage array 101. As shown in fig. 15, the control logic unit 124 includes a timing control unit for controlling the timing of the respective control signals, and a voltage control unit in which one or more delay chain circuits are arranged as shown in fig. 15. The voltage control unit is used to control the supply voltage of the power supply circuit 201 for supplying power to the delay chain circuit. The control circuit 202 in the foregoing embodiment may be implemented by a voltage control unit in fig. 15. That is, the embodiment of the present application can be implemented by the control logic unit 124, the temperature acquisition circuit, and the power supply circuit 201 in the peripheral circuit 102 shown in fig. 15.

In addition, the sense amplifier and IO circuit 121 may be configured to read data from the memory array 101 and program (write) data to the memory array 101 according to control signals from the control logic unit 124, and store the relevant data to the data output buffer 130. The sense amplifier and IO circuits 121 may also receive data to be written from the data input buffer 129 and store a page of programming data (i.e., write data) to be programmed into a page of the memory array 101.

The refresh counter 125 may be configured to record the row for which a refresh operation is next required, and the refresh counter 125 may be updated after completion of a refresh operation. The row address latch 127 may be configured to receive a row address to be operated on. MUX126 is used to select a row address from refresh counter 125 and row address latch 127 as the row address currently to be operated on.

The Row decoder 123 may be configured to map a Row Address (Row Address) to a specific word line (word line), ultimately opening a designated Row. The Column decoder 122 may be configured to map a Column Address (Column Address) to a specific CSL (Column select line), ultimately selecting a particular Column.

In addition, the power supply circuit 201 may also be configured to be controlled by the control logic unit 124 and generate a word line voltage (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 101.

The control logic unit 124 may be coupled to and configured to control the operation of various ones of the peripheral circuits described above.

It should be noted that the peripheral circuit shown in fig. 15 is an example peripheral circuit, and does not limit the peripheral circuit provided in the embodiment of the present application.

In addition, the embodiment of the application also provides a storage system based on the memory 10 in the previous embodiment. Fig. 16 is a block diagram of a storage system 160 provided by an embodiment of the present application. Fig. 17 is a block diagram of another storage system 170 provided in an embodiment of the present application.

As shown in fig. 16 and 17, the memory system may include a controller and the memory 10 of the foregoing embodiments, the controller being coupled to the memory 10 to control the memory 10 to store data.

Wherein the storage system may be integrated into various types of storage devices. For example, in the same package (e.g., UFS (Universal Flash Storage, universal flash storage) package or eMMC (Embedded Multi MEDIA CARD) package). That is, the storage system 160 may be applied to and packaged into different types of electronic products. For example, a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power source, a VR (Virtual Reality) device, an AR (Augmented Reality) device, or any other suitable electronic device having a memory therein.

In some embodiments, as shown in FIG. 16, the memory system 160 may include a controller 1601 and one memory 10, and the memory system 160 may be integrated into a memory card.

The memory Card includes any one of PC Card (PCMCIA, personal computer memory Card international association), CF (Compact Flash) Card, SM (SMART MEDIA ) Card, memory stick, MMC (Multimedia Card), SD (Secure Digital Memory, secure digital) Card, UFS.

In other embodiments, as shown in fig. 17, the storage system 170 includes a controller 1701 and a plurality of memories 10, and the storage system 170 is integrated into an SSD (Solid STATE DRIVES, solid state disk).

In the storage system 170, the controller 1701 is illustratively configured for operation in a low duty cycle environment, such as an SD card, CF card, USB (Universal Serial Bus ) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

Also for example, the controller 1701 is configured to operate in a high duty cycle environment SSD or eMMC, such as a data storage for mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

Additionally, in some embodiments, the controller 1701 may be configured to manage data stored in the memory 10 and communicate with an external device (e.g., host). In other embodiments, the controller 1701 may also be configured to control operations of the memory 10, such as read, erase, and program operations. In other embodiments, the controller 1701 may be further configured to manage various functions with respect to data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In other embodiments, the controller 1701 is further configured to process error correction codes with respect to data read from the memory 10 or written to the memory 10.

Optionally, the controller 1701 may also perform any other suitable function, such as formatting the memory 10; for example, the controller 1701 may communicate with an external device (e.g., host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of USB protocol, MMC protocol, PCI (PERIPHERAL COMPONENT INTERCONNECT ) protocol, PCI express (PCI-E) protocol, ATA (Advanced Technology Attachment ) protocol, serial ATA protocol, parallel ATA protocol, SCSI (Small Computer SYSTEM INTERFACE, small Computer interface) protocol, ESDI (ENHANCED SMALL DRIVE INTERFACE, enhanced Small disk interface) protocol, IDE (INTEGRATED DEVELOPMENT ENVIRONMENT ) protocol, firewall (Firewire) protocol.

In addition, the embodiment of the application also provides electronic equipment. The electronic device may be any of a cell phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

Fig. 18 is a schematic structural diagram of an electronic device 180 according to an embodiment of the present application. The electronic device 180 may include the above storage system 160 or 170, and may further include at least one of a central processing unit CPU (Central Processing Unit ) and a cache (cache), etc.

The foregoing is merely illustrative embodiments of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A control circuit, characterized in that the control circuit is coupled to a control terminal of a voltage regulating circuit in a memory, and a voltage output terminal of the voltage regulating circuit is also coupled to a power supply input terminal of a delay chain circuit in the memory; wherein the control circuit is configured to:

Acquiring the current ambient temperature;

Determining a target regulation signal based on the target supply voltage;

2. The control circuit of claim 1, wherein the target supply voltage is in positive correlation with the current ambient temperature.

3. The control circuit of claim 1, wherein the control circuit stores a target map indicating a relationship between a supply voltage applied to a supply input of the delay chain circuit and a temperature in a case where a transmission delay of the delay chain circuit is stable;

The control circuit is configured to:

4. The control circuit of claim 3, wherein the voltage output of the voltage regulation circuit is further coupled to a supply input of an oscillating circuit within the memory;

the control circuit is further configured to:

5. The control circuit of claim 4 wherein the first temperature is a lower boundary of a safe operating temperature range of the memory and the second temperature is an upper boundary of the safe operating temperature range of the memory.

6. The control circuit of claim 3, wherein the control circuit is configured to:

7. The control circuit of claim 3, wherein the control circuit is configured to:

8. The control circuit of claim 3, wherein the control circuit is configured to:

9. The control circuit of any of claims 1-8, wherein the control circuit is further coupled to a temperature acquisition circuit within the memory;

The control circuit is configured to:

10. A peripheral circuit comprising the control circuit of any one of claims 1-9, further comprising a power supply circuit and the delay chain circuit, the power supply circuit comprising the voltage regulation circuit;

11. The peripheral circuit of claim 10, wherein the control circuit stores a target map indicating a relationship between a power supply voltage applied to a power supply input of the delay chain circuit and a temperature in a case where a transmission delay of the delay chain circuit is stable;

12. The peripheral circuit of claim 11, wherein the power supply circuit further comprises an oscillating circuit:

13. The peripheral circuit of claim 10, wherein the peripheral circuit further comprises a temperature acquisition circuit;

The control circuit is configured to receive the current ambient temperature.

14. A method of operating a control circuit, characterized in that the control circuit is a control circuit as claimed in any one of claims 1-9; the method comprises the following steps:

Acquiring the current ambient temperature;

Determining a target regulation signal based on the target supply voltage;

15. The method of claim 14, wherein the control circuit stores a target map indicating a relationship between a supply voltage applied to a supply input of the delay chain circuit and a temperature in a case where a transmission delay of the delay chain circuit is stable;

16. The method of claim 15, wherein a voltage output of the voltage regulation circuit is coupled to a power supply input of an oscillating circuit within the memory; the method further comprises the steps of:

17. A memory, the memory comprising:

The peripheral circuit of any of claims 10-13;

and a memory array coupled to the peripheral circuitry.

18. A storage system, the storage system comprising:

The memory of claim 17;

And a controller coupled to the memory and configured to control the memory.

19. An electronic product comprising the storage system of claim 18.