CN118260228A - Bus address setting method - Google Patents

Abstract

The invention relates to the technical field of bus address conflict avoidance, and provides a bus address setting method, which mainly comprises the following steps that a UBM controller scans a management bus to generate scan address information, the UBM controller is switched into a monitoring mode to monitor the management bus to generate monitoring address information, the definition of the monitoring address information is an unexpected bus address of an unexpected device connected to the management bus in the monitoring mode time, the UBM controller judges whether a target address is identical to one of the scan address information and the monitoring address information according to the scan address information and the monitoring address information, and if the judgment result is yes, the UBM controller changes the target address by one of the rest addresses which are different from the scan address information and the monitoring address information and is used as a verified target address.

Description

Bus address setting method

Technical Field

The invention relates to the technical field of bus address conflict avoidance, in particular to a bus address setting method.

Background

The conventional hard disk management for external connection standard (PERIPHERAL COMPONENT INTERCONNECT, hereinafter referred to as PCIe) is to perform the related signal control of the hard disk back plane by performing the handshake communication between the hard disk management component and the master control component on the serial bus through Virtual Pin Port (hereinafter referred to as VPP) and universal back plane management (Universal Backplane Management, hereinafter referred to as UBM). Both VPP and UBM carry out communication protocol through integrated bus circuit (I2C) interface, and more than two devices with same address can not exist on the same bus of I2C, otherwise, the master control component can not communicate with the devices. Therefore, when the VPP address sent by the master control component collides with the UBM address or other special device positions collide, the hard disk management interface is crashed, so that the system hard disk cannot be used normally.

Disclosure of Invention

It is therefore an object of the present invention to provide a bus address setting method that overcomes the drawbacks of the prior art.

In order to solve the technical problems, the invention provides the following technical scheme:

A bus address setting method executed by a servo device, the servo device including a back-plane controller, a management bus, a back-plane memory and a front-end module, the bus address setting method comprising:

(A) The back panel controller scans the management bus to generate scanning address information, wherein the definition of the scanning address information is the peripheral device address of at least one additional device connected to the management bus; (D) The back panel controller is switched into a monitoring mode to monitor the management bus and generate monitoring address information, wherein the definition of the monitoring address information is an unexpected bus address of an unexpected device connected to the management bus in the monitoring mode time; (G) The backboard controller judges whether a target address is identical to one of the scanning address information and the monitoring address information according to the scanning address information and the monitoring address information, and if so, the backboard controller changes the target address by one of the rest addresses different from the scanning address information and the monitoring address information to serve as the verified target address; (H) The backplane controller writes the verified target address to the primary block of the backplane storage, the target address written to the primary block for reading by the front-end module.

Preferably, the step (a) and the step D further comprise: (B) The back panel controller sets a parameter of the back panel storage to a locking parameter corresponding to an invalid state, wherein the definition of the locking parameter is that the target address of the back panel controller recorded by the back panel storage is not verified yet; (C) The back panel controller generates a notification signal to the front end module, so that the front end module starts to execute an initialization mode according to the notification signal.

Preferably, the step D further comprises: (E) The front-end module generates an access signal to trigger reading the locking parameter of the back-plate storage, and reads a time parameter according to the locking parameter, wherein the definition of the time parameter is to re-read the interval time value of the back-plate storage again; (F) The back panel controller stops the monitoring mode according to the access signal.

Preferably, the method further comprises: (I) The backplane controller alters the parameter of the backplane storage to an unlock parameter defined as the primary block of the backplane storage recording that the target address is verified.

Preferably, the method further comprises: (J) The front-end module reads the unlocking parameter from the back-plate storage according to the time parameter, and obtains and adopts the target address stored in the back-plate storage according to the unlocking parameter.

Preferably, the method further comprises: (K) The front-end module communicates with the back panel controller via the management bus according to the target address.

Preferably, the step (G) further includes if the determination result is no, the backplane controller maintaining the target address as the verified target address.

Preferably, the step (a) is preceded by: (S) the servo device performing a power-up mode.

Preferably, the management bus comprises a two-wire protocol interface.

The invention has the following effects: address collision of the bus is avoided, so that compatibility of the system to the serial bus device is improved.

[ Description of the drawings ]

Other features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the drawings, in which:

FIG. 1 is a system diagram of one embodiment of a servo apparatus of the present invention; and

FIG. 2 is a flowchart of an embodiment of a method for setting a bus address.

The reference numerals in the figures illustrate: 1. a back panel controller; 11. a UBM controller; 2. a bus device; 3. a back plate reservoir; 31. a non-volatile memory; 4. a front end module; 41. a disk array device; 6. a back plate; 7. a storage module; 71. a hard disk; s, powering up the step of the mode; A-K, setting addresses.

[ Detailed description ] of the invention

Before the present invention is described in detail, it should be noted that in the following description, like components are denoted by the same reference numerals.

Referring to FIG. 1, an embodiment of a servo apparatus is shown. The servo equipment comprises a back plate controller 1, a management bus 2, a back plate storage 3, a front end module 4, a back plate 6 and a plurality of storage modules 7.

The backplane controller 1 includes at least one of a universal backplane management controller (Universal Backplane Management Controller, hereinafter referred to as UBM controller) 11, a complex programmable logic device (Complex Programmable Logic Device, CPLD), a field programmable logic gate array (Field Programmable GATE ARRAY, FPGA), a microprocessor unit (Micro Controller Unit, MCU), and the UBM controller is taken as an example of the backplane controller 1.

The management Bus 2 includes a two-Wire (hereinafter referred to as 2 Wire) protocol interface Bus, where the 2Wire protocol interface is, for example, an integrated circuit Bus (Inter-INTEGRATED CIRCUIT BUS, hereinafter referred to as I2C Bus) protocol interface, a system management Bus (SYSTEM MANAGEMENT Bus, SMBus) protocol interface, and the like, and the two-Wire protocol interface Bus includes a serial data line (SDA) for transmitting data and a serial frequency line (SCL) corresponding to the serial data line and for transmitting clock signals. The management Bus 2 further includes a part of buses belonging to other buses, such as a PCI express Bus (PERIPHERAL COMPONENT INTERCONNECT EXPRESS BUS, PCIe Bus), a high-definition multimedia interface Bus (High Definition Multimedia Interface Bus, HDMI Bus), a digital Display Port (DP) Bus, or other buses that are not 2Wire buses but can be used to support the serial data line (SDA) and serial frequency line (SCL), and the front end module 4 communicates with the back plane controller 1 and the storage module 7 through the management Bus 2. That is, in this embodiment, the management bus 2 may be a separate I2C bus, or may be another bus that is built in another bus and can support communication of I2C.

The back-plate storage 3 includes a Non-Volatile Memory 31 for storing field replaceable Unit (FIELD REPLACE Unit, hereinafter referred to as FRU) information/data, wherein the FRU datagram includes one of a part number, a product number, and a service number, and the Non-Volatile Memory, such as an electrically erasable programmable read-only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, EEPROM), a Non-Volatile random access Memory (NVRAM), or a Flash Memory (Flash Memory), is a Memory that does not erase/lose internal storage data due to power loss.

The front-end module 4 includes several types, for example, a first type of front-end module includes a CPU, PCH and PCIE SWITCH; the second front-end module includes an expansion controller (also referred to as a disk array device controller 41, hereinafter referred to as a RAID controller), where the RAID controller communicates with the backplane controller through an I2C Bus (I2C Bus/integrated circuit Bus), that is, the RAID controller and the backplane controller both support an I2C Bus protocol (integrated circuit Bus protocol), and the RAID controller may also communicate with peripheral devices (e.g., a hard disk or a back-end expansion module) electrically connected to the backplane controller through the I2C Bus and through the backplane controller; the third front-end module comprises at least one controller of another CPLD/FPGA/MCU and other programmable controllers, and a circuit module which can communicate with a plurality of peripheral devices electrically connected with the back-plate controller 1 through the back-plate controller 1. Wherein the storage module 7 comprises a hard disk 71 (e.g. SSD or HDD, etc.).

As shown in FIG. 2, the servo device executes a bus address setting method, which includes steps (S), (A) to (K).

Step (S): the servo device receives Power to execute a Power-up mode, including performing Power sequence detection (Power sequence) to perform a system initialization procedure.

Step (A): in this step, the UBM controller 11 is operated in the master mode by default, each of the plurality of peripheral devices is electrically connected to the management bus 2, and the peripheral devices are operated in the slave mode by default and communicate with the UBM controller 11 through the management bus 2, and the UBM controller 11 scans the bus address of the management bus 2 to find at least one peripheral device, wherein each of the found peripheral devices corresponds to a peripheral device address different from other peripheral devices, and the UBM controller 11 operating in the master mode by default communicates with the peripheral device corresponding to the peripheral device address through the management bus 2 and through the peripheral device address.

Specifically, the available/corresponding bus address of the device connected to the 2Wire interface of the management bus 2 is defined by, but not limited to, 00-11, 000-111, or 0-255, and the bus address of the management bus 2 is 0-255, which is taken as an example of all the bus addresses that may be used by the device connected to the management bus 2. When the UBM controller 1 scans the management bus 2 for a bus address in the master mode, the first aspect of the bus address scan is: the UBM controller 11 sequentially calls all bus addresses corresponding to the peripheral devices through the management bus 2 one by one (for example, the bus addresses may be 0 to 255), for example, by sequentially calling the bus addresses 0 to the addresses 255, to confirm whether other peripheral devices electrically connected to the management bus 2 in the slave mode and controlled by the UBM controller 11 exist on the management bus 2, when the UBM controller 11 calls with one of the bus addresses and has received a response signal transmitted by the corresponding peripheral device, the UBM controller 11 represents the peripheral device address used by the peripheral device for which the one bus location for calling corresponds to the peripheral device transmitting the response signal, that is, the UBM controller 11 can communicate with the corresponding peripheral device by means of the peripheral device address, the UBM controller 11 records the peripheral device address and continues until the address 255 is called, and generates a scan address message defining the peripheral device address corresponding to all the peripheral devices/peripheral devices connected to the management bus 2.

The second aspect of bus address scanning is: the UBM controller 11 transmits a slave bus address request in a broadcast manner through the management bus 2 in a master mode, thereby the UBM controller 11 receives response signals returned from all peripheral devices in a slave mode through the management bus 2 communicating with the UBM controller 11 and corresponding to the UBM controller 11, wherein the response signals include peripheral device addresses used by corresponding peripheral devices, that is, the UBM controller 11 receives and collects response signals returned from all peripheral devices connected to the management bus 2 in a slave mode relative to the UBM controller 11, thereby collecting all peripheral device addresses respectively corresponding to all peripheral devices connected to the management bus 2 in a slave mode relative to the UBM controller 11, and generating the scan address information.

Step (B): the non-volatile memory 31 stores a lock parameter indicating whether a main block of the non-volatile memory 31 stores a lock parameter value (1) corresponding to an invalid state and an unlock parameter value (0) corresponding to a valid state, in which the front-end module 4 operates in a master mode, the UBM controller 11 and the peripheral device are in a slave mode with respect to the front-end module 4, the UBM controller 11 sets a lock parameter of the non-volatile memory 31 to a lock parameter value (1) corresponding to an invalid state, wherein the non-volatile memory 31 stores a target address corresponding to an unverified target address of the UBM controller 11, and a difference between the unverified and verified target addresses is defined: when the content stored in the main block (for example, the content is the target address) has not been verified, the UBM controller 11 sets the lock parameter to the lock parameter value (1) indicating the invalid state, and at this time, the front-end module 4 cannot communicate with the UBM controller 1 using the unverified target address; when the content stored in the main block has been verified (step G will be described in detail later), the UBM controller 1 sets the lock parameter switch to the unlock parameter value (0) indicating the valid state, the main block records the target address of the UBM controller 11, and the front-end module 4 communicates with the UBM controller 11 corresponding to the target address and operating in the slave mode by the verified target address, and communicates with the peripheral device corresponding to the one peripheral device address and operating in the slave mode by one of the peripheral device addresses.

Since in step B, before the UBM controller 11 has not verified the target address, the main block records a default address as the target address, and the lock parameter is set to the lock parameter value (1), for example, the lock parameter corresponding to the main block of the nonvolatile memory 31 storing the FRU data is set to the lock parameter value corresponding to the Invalid state (Invalid), that is, to parameter 1, the lock parameter value (invalid=1) indicates that the main block corresponds to the Invalid state, that is, even if the content of the nonvolatile memory 31 is available for other devices to read and write, in the Invalid state, the FRU data stored in the main block of the nonvolatile memory 31 is the FRU data which has not been verified, for example, the target address in the FRU data is the default address which has not been verified, and is not reference value, even if the front-end module 4 obtains the target address by the nonvolatile memory 31, which can not be communicated with the UBM controller by the controller, since the UBM controller cannot be connected to the corresponding to the target controller 11 by the other controller 11 is not normally, since the UBM controller can be prevented from being in the non-valid state (11) by the controller 11), if other peripheral devices in the slave mode also use the default address as their own peripheral device address, the target address of the UBM controller 11 may verify the target address in order to avoid the same address conflict, and possibly update/change the target address in the verification process, if the locking parameter of the non-volatile memory 31 is set to the locking parameter value (1) corresponding to the invalid state before the UBM controller 11 completes the verification of the target address, the problem that the front-end module 4 (e.g. RAID controller) will have the same address conflict in the communication process with the UBM controller 11 by the target address which has not been verified can be avoided.

Step (C): taking the front-end module 4 as a disk array device (RAID Card) as an example, the UBM controller 11 generates a notification signal (CPRSNT #) to the front-end module 4 through its General-purpose input/output port (GPIO) to enable the disk array device 41 to start executing an initialization mode according to the notification signal, where the front-end module 4 may also be a motherboard, an expansion control Card on the motherboard, a baseboard management controller …, etc., and is electrically connected to the UBM controller 1 of the backplane 6 and may be other controllers that communicate with the UBM controller 11 by reading data stored in the nonvolatile memory 31.

Step (D): the UBM controller 11 switches to a monitor mode to monitor the management bus 2, and because the customized firmware may occur and there is a 2Wire interface address (bus address) calling/signaling (handle) behavior that violates UBM industry specifications, or other unexpected devices (first unexpected devices) perform the same address calling/signaling behavior at this time, the UBM controller 1 monitors the calling/signaling signals corresponding to any 2Wire address (unexpected bus address) during the monitor mode, each calling/signaling signal includes an unexpected bus address, and accumulates and records the unexpected bus address included in the received calling/signaling signal to a monitor address information defined as the unexpected bus address corresponding to the unexpected device connected to the management bus 2 during the monitor mode; the second unexpected device is a new peripheral device that is electrically connected to the management bus 2 and operates in a slave mode with respect to the UBM controller 11 after the UBM controller 1 performs the process of step (a) or after the step (a) is completed, and the new peripheral device address corresponding to the new peripheral device is not recorded in the scan address information, the bus address corresponding to the new peripheral device is the unexpected bus address, and the new peripheral device is electrically connected to the management bus when the UBM controller 11 is in the monitor mode, and a rotation signal including the new peripheral device address corresponding to the new peripheral device is sent to the UBM controller 1, so that the UBM controller 1 records the new peripheral device address in the monitor address information; the third unexpected device may also be other components connected to the same front-end module 4 and not controlled by the UBM controller 1, where other bus addresses corresponding to the other components are unexpected bus addresses, and when the UBM controller 1 is in the monitor mode, the UBM controller 1 will record the other bus addresses in the monitor address information in an accumulated manner after receiving the call/negotiation signal sent by the front-end module 4 and including the other bus addresses.

Step (E): the disc array device 41 generates an access signal to trigger the reading of the locking parameter of the non-volatile memory 31, and obtains a time parameter according to the locking parameter, where the time parameter is defined as an interval time for re-reading the non-volatile memory 31 again next time, and further describes herein that the time parameter is defined as a time parameter that is read together when the disc array device 4 wants to read FRU data from the non-volatile memory 3, although the disc array device 4 will read the locking parameter value (invalid=1) corresponding to the locking parameter value (invalid=1) indicating the Invalid state, invalid=1 indicates that the disc array device 41 will not read an unverified target address (default address) from the non-volatile memory 3, but the non-volatile memory 3 has a temporary block storing a time parameter that is defined as a time length for re-reading the non-volatile memory 31 after the disc array device 41 reads the locking parameter value (invalid=1) indicating the Invalid state from the non-volatile memory 31.

Step (F): the UBM controller 11 stops the monitor mode according to the access signal. Step (G): the UBM controller 11 determines whether the target address which is not verified is identical to one of the scan address information and the monitor address information according to the scan address information and the monitor address information, if the determination result is yes, the UBM controller 11 changes the default address, that is, if any one of the scan address information and the monitor address information is identical to the target address which is not verified (the default address), the UBM controller 11 updates/changes the target address with one of the remaining addresses which is different from the scan address information and the monitor address information as the new target address (excluding the existing scan address and monitor address), wherein the new target address is the verified target address, and if the determination result is no, the UBM controller 11 maintains the target address equal to the default address, and the default address can be continuously used to enable the UBM controller 11 to communicate with the disk array 41, that is, the verified target address is the step G.

Step (H): the UBM controller 11 writes the verified target address to the main block of the nonvolatile memory 31 as the verified target address, and writes the target address to the main block for the disk array device of the front-end module 4 to read. Further describing herein, as mentioned in the foregoing step (E), during a neutral period of the waiting time period of the disk array device 41, the UBM controller 11 starts to execute the verification data writing procedure of the nonvolatile memory 31 by using the neutral period, wherein the verification data writing procedure includes writing the backplane message, the 2Wire address of the UBM controller 11, that is, the verified target data, into the nonvolatile memory 31. The target address of the UBM controller 11 is a bus address recorded avoiding the scan address information and the monitor address information, and is different from the address recorded by the scan address information and the monitor address information, that is, the dedicated target address of the UBM controller 11 which does not conflict with the address corresponding to any device connected to the management bus 2 is written into the nonvolatile memory 3.

Step (I): the UBM controller 11 changes the locking parameter of the nonvolatile memory 31 to an unlocking parameter value corresponding to the valid state, that is, invalid=0, so that the disk array device 4 can read and use the nonvolatile memory 31, and the unlocking parameter is switched to the unlocking parameter value after the main block of the nonvolatile memory 31 records that the target address has been verified.

Step (J): the disk array device 41 reads the unlocking parameter from the nonvolatile memory 31 according to the time parameter, and obtains and adopts the target address stored in the main block according to the unlocking parameter. Step (K): the disk array device 41 communicates with the UBM controller 1 via the management bus 2 according to the verified target address.

In summary, in the above embodiment, before the disk array device 41 of the front-end module 4 has not been operated in the system initialization stage, the UBM controller 11 of the backplane controller 1 connected in series to the same management bus 2 first sets the locking parameter of the non-volatile memory 31 storing the target address corresponding to the UBM controller 11 to be the locking parameter value corresponding to an invalid state, scans the peripheral device addresses of other peripheral devices of the same management bus 2, records the scanned peripheral device addresses in the UBM controller 11 to integrate all scanned peripheral device addresses as the scanning address information, then in the monitor mode, the UBM controller 11 generates the monitoring address information with the non-expected bus addresses of the non-expected devices (including the first to third types of the above), the UBM controller 11 verifies the target address corresponding to itself according to the previously recorded scanning address information and the occupied address of the device corresponding to the monitoring address information, and verifies that the target address corresponding to itself is changed in response to the verification process of the UBM controller 11, and then the address corresponding to the target address corresponding to the UBM controller is changed to the address information, thereby triggering the verification process of the non-volatile memory 31 to be the target address is completed when the address of the volatile memory is changed to the target address corresponding to the address of the UBM controller, and the address of the non-expected device is completely unlocked.

However, the foregoing is only illustrative of the present invention and is not to be construed as limiting the scope of the invention, which is defined by the appended claims and their equivalents.

Claims (9)

1. A bus address setting method executed by a servo device, the servo device including a back-plane controller, a management bus, a back-plane memory and a front-end module, the bus address setting method comprising:

(A) The back panel controller scans the management bus to generate scanning address information, wherein the definition of the scanning address information is the peripheral device address of at least one additional device connected to the management bus;

(D) The back panel controller is switched into a monitoring mode to monitor the management bus and generate monitoring address information, wherein the definition of the monitoring address information is an unexpected bus address of an unexpected device connected to the management bus in the monitoring mode time;

(G) The backboard controller judges whether a target address is identical to one of the scanning address information and the monitoring address information according to the scanning address information and the monitoring address information, and if so, the backboard controller changes the target address by one of the rest addresses different from the scanning address information and the monitoring address information to serve as the verified target address;

(H) The backplane controller writes the verified target address to the primary block of the backplane storage, the target address written to the primary block for reading by the front-end module.

2. The bus address setting method as set forth in claim 1, wherein the step (a) and the step D further comprise:

(B) The back panel controller sets a parameter of the back panel storage to a locking parameter corresponding to an invalid state, wherein the definition of the locking parameter is that the target address of the back panel controller recorded by the back panel storage is not verified yet;

(C) The back panel controller generates a notification signal to the front end module, so that the front end module starts to execute an initialization mode according to the notification signal.

3. The bus address setting method as set forth in claim 2, wherein said step D further comprises, after:

(E) The front-end module generates an access signal to trigger reading the locking parameter of the back-plate storage, and reads a time parameter according to the locking parameter, wherein the definition of the time parameter is to re-read the interval time value of the back-plate storage again;

(F) The back panel controller stops the monitoring mode according to the access signal.

4. The bus address setting method as set forth in claim 3, further comprising:

(I) The backplane controller alters the parameter of the backplane storage to an unlock parameter defined as the primary block of the backplane storage recording that the target address is verified.

5. The bus address setting method as set forth in claim 3, further comprising:

(J) The front-end module reads the unlocking parameter from the back-plate storage according to the time parameter, and obtains and adopts the target address stored in the back-plate storage according to the unlocking parameter.

6. The bus address setting method according to claim 1, further comprising:

(K) The front-end module communicates with the back panel controller via the management bus according to the target address.

7. The bus address setting method as set forth in claim 1, wherein said step (G) further comprises the step of if the determination is negative, said backplane controller maintaining said target address as said verified target address.

8. The bus address setting method as set forth in claim 1, wherein said step (a) further comprises, prior to: (S) the servo device performing a power-up mode.

9. The bus address setting method as set forth in claim 1, wherein the management bus comprises a two-wire protocol interface.