CN118248557A - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents

Method for manufacturing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN118248557A
CN118248557A CN202211665728.7A CN202211665728A CN118248557A CN 118248557 A CN118248557 A CN 118248557A CN 202211665728 A CN202211665728 A CN 202211665728A CN 118248557 A CN118248557 A CN 118248557A
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China
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conductive
chip
back surface
semiconductor structure
chips
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潘效飞
郑明祥
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China Resources Runan Technology Chongqing Co ltd
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China Resources Runan Technology Chongqing Co ltd
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Priority to CN202211665728.7A priority Critical patent/CN118248557A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Ceramic Engineering (AREA)
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Abstract

The application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the steps of mounting a plurality of chips on a carrier plate, wherein adjacent chips are arranged at intervals; the chip comprises a control electrode and a first electrode which are arranged on the front surface of the chip, and a second electrode which is arranged on the back surface of the chip; forming insulating film layers on the side surfaces of the chips, wherein a gap exists between two insulating film layers between two adjacent chips; setting a conductive structure, wherein the conductive structure comprises a first conductive part positioned at the side part of each chip and a second conductive part positioned at the back of each chip, and the first conductive part is positioned outside an insulating layer positioned at the side surface of the chip; the second conductive part at least covers part of the second pole, and the first conductive part at the side part of the chip is connected with the second conductive part at the back side of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane; and forming a protective layer at least on the surface of the conductive structure facing away from the chip.

Description

Method for manufacturing semiconductor structure and semiconductor structure
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
Some existing chips, such as direct contact field effect transistors, have their source and gate on the front side of the chip and drain on the back side of the chip. When the chip is connected to the circuit board, the drain electrode is usually led to the front side of the chip by adopting a copper shell, the bottom wall of the copper shell is electrically connected with the drain electrode of the chip through conductive adhesive, and the side wall of the copper shell extends to one side of the front side of the chip so as to lead the drain electrode of the chip to one side of the front side of the chip, thereby being convenient for the chip to be electrically connected with the circuit board.
By adopting the scheme, the problems of copper shell inclination, chip inclination, copper shell deformation, difficult control of the consumption of conductive adhesive and the like can occur, so that the product yield is lower.
Disclosure of Invention
The embodiment of the application provides a manufacturing method of a semiconductor structure. The manufacturing method comprises the following steps:
Mounting a plurality of chips on a carrier plate, wherein adjacent chips are arranged at intervals; the chip comprises a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces for connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface;
Forming an insulating film layer on the side surface of each chip, wherein a gap exists between two insulating film layers between two adjacent chips;
Providing a conductive structure, wherein the conductive structure comprises a first conductive part positioned at the side part of each chip and a second conductive part positioned at the back of each chip, and the first conductive part is outside an insulating layer positioned at the side surface of each chip; the second conductive part at least covers part of the second pole, and the first conductive part at the side part of the chip is connected with the second conductive part at the back side of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane;
and forming a protective layer, wherein the protective layer is at least positioned on the surface of the conductive structure, which is away from the chip.
In some embodiments, the forming an insulating film layer on a side surface of each chip, where a gap exists between two insulating film layers between two adjacent chips, includes:
and forming an insulating film layer on the side surface of each chip by adopting a spraying process.
In some embodiments, the disposing a conductive structure comprises:
arranging conductive materials on the back surface and at least one side part of each chip to obtain a second conductive part positioned on the back surface of each chip and a conductive block positioned between at least two adjacent chips;
and cutting the conductive block to form two first conductive parts which are arranged at intervals.
In some embodiments, the disposing a conductive material on the back surface and at least one side of each of the chips to obtain a second conductive portion on the back surface of the chip, and to obtain a conductive block at least between two adjacent chips, including:
Arranging a first conductive material on at least one side part of each chip to obtain a conductive block at least between two adjacent chips;
Setting a second conductive material on the back of each chip to obtain a second conductive material layer positioned on the back of each chip and the top surface of each conductive block;
And when the conductive block is cut, cutting the second conductive layer on the surface of the conductive block to form a second conductive part positioned on the top surface of the first conductive part and the back surface of the chip.
In some embodiments, the disposing a conductive material on the back side and at least one side of each of the chips comprises:
a sputtering process is adopted to set conductive materials on the back surface and at least one side part of each chip; or alternatively
Setting conductive materials on the back surface and at least one side part of each chip by adopting a dispensing process; or alternatively
Setting conductive materials on the back surface and at least one side part of each chip by adopting a screen printing process; or alternatively
And setting conductive materials on at least one side part of each chip by adopting a dispensing process, and setting conductive materials on the back surface of each chip by adopting a sputtering process or a screen printing process.
In some embodiments, the disposing a conductive structure comprises:
Arranging a first preset conductive piece on at least one side part of each chip; the first preset conductive piece comprises a conductive block, and the conductive block is arranged between two adjacent chips;
arranging conductive materials on the back surfaces of the chips to form a second conductive material layer positioned on the back surfaces of the chips and the top surfaces of the conductive blocks;
And cutting the conductive block, and cutting the second conductive layer on the surface of the conductive block to form two first conductive parts arranged at intervals, and second conductive parts positioned on the top surface of the first conductive parts and the back surface of the chip.
In some embodiments, before disposing the first predetermined conductive member on at least one side of each of the chips, the method includes:
Forming a first preset conductive member;
a first adhesive material layer is arranged on the side wall of the first preset conductive piece.
In some embodiments, the disposing a conductive structure comprises:
a second preset conductive element is arranged on at least one side part of each chip; the second preset conductive piece comprises a conductive block and an extension part which is electrically connected to the end part of the conductive block and extends transversely; the conductive blocks are positioned between two adjacent chips, and the extending parts are positioned on the back surfaces of the corresponding chips to form corresponding second conductive parts;
And cutting the conductive block to form two first conductive parts which are arranged at intervals, and connecting the end parts of the first conductive parts and the second conductive parts positioned on the back surface of the chip.
In some embodiments, before disposing the second preset conductive member on at least one side of each of the chips, the method includes:
Forming a second preset conductive member;
A second bonding material layer is arranged on the side wall of the second preset conductive piece, and a third bonding material layer is arranged on the surface, which is arranged towards the back surface of the chip, of the extension part; wherein the third bonding material layer is formed by adopting a conductive bonding material.
In some embodiments, before the cutting the conductive block, the manufacturing method further comprises:
removing the carrier plate to obtain a platy semiconductor intermediate assembly;
forming a plurality of conductive balls on one side of the platy semiconductor intermediate assembly, which is far away from the back surface of the chip, by adopting a ball implantation process, wherein the control electrode and the first electrode are respectively and electrically connected with at least one conductive ball; the conductive block is electrically connected with at least two conductive balls;
and cutting the conductive blocks to form two first conductive parts arranged at intervals, and electrically connecting each first conductive part with at least one conductive ball after obtaining a plurality of intermediate semiconductor structures.
After obtaining the plurality of intermediate semiconductor structures, the method of manufacturing comprises:
and forming a protective layer at least on the surface of the conductive structure, which is away from the chip, on the outer side of the formed intermediate semiconductor structure to form the semiconductor structure.
In some embodiments, after the cutting the conductive block, the manufacturing method further comprises:
forming the protective layer outside the first conductive part and the second conductive part;
And removing the carrier plate to form a plurality of semiconductor structures.
In some embodiments, a sputtering process is used to form the protective layer; and/or the number of the groups of groups,
The material of the protective layer is an antioxidant metal material.
In some embodiments, the second conductive portion covers an entire area of the back side of the chip, or the second conductive portion covers a partial area of the back side of the chip.
The embodiment of the application also provides a semiconductor structure, which comprises:
The chip comprises a chip front surface, a chip back surface opposite to the chip front surface and a plurality of side surfaces for connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface and a second electrode which is arranged on the chip back surface;
The insulating film layer is positioned on the side surface of the chip;
The conductive structure comprises a first conductive part positioned at the side part of the chip and a second conductive part positioned at the back of the chip, wherein the second conductive part at least covers part of the second pole, and the first conductive part at the side part of the chip is connected with the second conductive part at the back of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane;
and the protective layer is positioned on the surface of the conductive structure, which is away from the chip.
In some embodiments, the semiconductor structure further includes a plurality of conductive balls on a front side of the chip, and the first conductive portion, the control electrode, and the first electrode are electrically connected to at least one of the conductive balls, respectively.
The embodiment of the application achieves the main technical effects that:
According to the manufacturing method of the semiconductor structure, the second conductive part positioned on the back surface of the chip and the first conductive part positioned on the side surface of the chip are arranged, and the second electrode is electrically connected with the first conductive part through the second conductive part, so that the second electrode can be led to the front surface of the chip through the second conductive part and the first conductive part; the surface of the first conductive part, the surface of the control electrode, and the surface of the first electrode are on the same plane, so that the semiconductor structure is connected with the circuit board. According to the manufacturing method of the semiconductor structure, the chip is mounted on the carrier plate in the manufacturing process, the chip is not easy to incline, the copper shell and the conductive adhesive for electrically connecting the chip and the copper shell are not needed, the problem of low product yield caused by the inclination of the chip, the inclination of the copper shell and the discomfort of the consumption of the conductive adhesive can be avoided, and the connection yield of the semiconductor structure and the circuit board can be ensured. According to the manufacturing method of the semiconductor structure, the protective layer is arranged on the surface, deviating from the chip, of the conductive structure, so that adverse effects caused by oxidization or collision with other structures due to the fact that the conductive structure is exposed are prevented, and the stability of electric connection of the conductive structure can be guaranteed.
Drawings
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an exemplary embodiment of the present application;
FIG. 2 is a partial cross-sectional view of a wafer provided in accordance with an exemplary embodiment of the present application;
FIG. 3 is a cross-sectional view of a chip provided in an exemplary embodiment of the application;
FIG. 4 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;
FIG. 5 is a partial cross-sectional view of a second intermediate structure provided in an exemplary embodiment of the application;
FIG. 6 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;
FIG. 7 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;
FIG. 8 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;
FIG. 9 is a schematic diagram illustrating an assembly of a first preset conductive member and a second intermediate structure according to an exemplary embodiment of the present application;
FIG. 10 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;
FIG. 11 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;
FIG. 12 is a schematic diagram illustrating an assembly of a second preset conductive member and a second intermediate structure according to an exemplary embodiment of the present application;
FIG. 13 is a partial cross-sectional view of an eighth intermediate member provided by an exemplary embodiment of the present application;
FIG. 14 is a partial cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application;
Fig. 15 is a cross-sectional view of a semiconductor structure provided in an exemplary embodiment of the present application;
Fig. 16 is a cross-sectional view of a semiconductor structure provided in another exemplary embodiment of the present application;
FIG. 17 is a partial cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application;
fig. 18 is a cross-sectional view of a semiconductor structure provided by yet another exemplary embodiment of the present application;
Fig. 19 is a cross-sectional view of a semiconductor structure provided in accordance with yet another exemplary embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.
Some embodiments of the application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
The embodiment of the application provides a manufacturing method of a semiconductor structure. Referring to fig. 1, the method for fabricating the semiconductor structure includes the following steps S110 to S140.
In step S110, a plurality of chips are mounted on a carrier, and adjacent chips are arranged at intervals; the chip comprises a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces for connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface.
In step S120, an insulating film layer is formed on each of the chip sides, and a gap is formed between two insulating film layers between two adjacent chips.
In step S130, a conductive structure is provided, where the conductive structure includes a first conductive portion located at a side of each chip and a second conductive portion located at a back of each chip, and the first conductive portion is outside an insulating layer located at a side of the chip; the second conductive part at least covers part of the second pole, and the first conductive part at the side part of the chip is connected with the second conductive part at the back side of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
In step S140, a protective layer is formed, where the protective layer is at least located on a surface of the conductive structure facing away from the chip.
According to the manufacturing method of the semiconductor structure, the second conductive part positioned on the back surface of the chip and the first conductive part positioned on the side surface of the chip are arranged, and the second electrode is electrically connected with the first conductive part through the second conductive part, so that the second electrode can be led to the front surface of the chip through the second conductive part and the first conductive part; the surface of the first conductive part, the surface of the control electrode, and the surface of the first electrode are on the same plane, so that the semiconductor structure is connected with the circuit board. In addition, according to the manufacturing method of the semiconductor structure provided by the embodiment of the application, the chip is attached to the carrier plate in the manufacturing process, the chip is not easy to incline, the copper shell and the conductive adhesive for electrically connecting the chip and the copper shell are not needed, the problem of low product yield caused by the inclination of the chip, the inclination of the copper shell and the uncomfortable consumption of the conductive adhesive can be avoided, and the connection yield of the semiconductor structure and the circuit board can be ensured. In addition, according to the manufacturing method of the semiconductor structure, the protective layer is arranged on the surface, deviating from the chip, of the conductive structure, so that adverse effects caused by oxidization or collision with other structures due to the fact that the conductive structure is exposed are prevented, and stability of electric connection of the conductive structure can be guaranteed.
The following describes each step of the method for manufacturing a semiconductor structure according to the embodiment of the present application in detail.
In step S110, a plurality of chips are mounted on a carrier, and adjacent chips are arranged at intervals; the chip comprises a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of side surfaces for connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface.
In one embodiment, the chip may be manufactured by the following process:
First, a wafer is provided. Referring to fig. 2, wafer 14 has a front side and a back side opposite the front side. The front surface of the wafer 14 is provided with a control electrode 11 and a first electrode 12, and the control electrode 11 and the first electrode 12 are arranged at intervals. The back side of the wafer is provided with a second pole 13.
In one embodiment, a rewiring structure may be formed on the front side of the wafer, the rewiring structure including a rewiring layer on the front side of the wafer and a conductive post on a side of the rewiring layer facing away from the wafer. The rewiring layer includes a plurality of leads, each of the control electrode 11 and the first electrode 12 being electrically connected to one of the leads, each of the leads being electrically connected to one of the conductive posts. Thus, by providing the rewiring structure, the distance between the control electrode 11 and the first electrode 12 can be increased, so that the subsequent chip can be connected with the circuit board conveniently.
Further, after the rewiring structure is formed, an insulating material layer covering the rewiring layer and the side surfaces of the conductive posts can be formed, and the surfaces of the conductive posts facing away from the wafer are flush with the surfaces of the insulating material layer facing away from the wafer. The layer of insulating material may include a rewiring structure.
Subsequently, the wafer 14 is diced. The wafer 14 may be diced along the positions of the dashed lines shown in fig. 2. The wafer 14 may be cut by mechanical dicing or by laser dicing. Through this step, the chip 10 shown in fig. 3 can be obtained. The front side, the side and the back side are all part of the surface of the chip. The die 10 shown in fig. 3 is cube-shaped, the die 10 including four die sides.
In the embodiment of the present application, if the front surface of the wafer is not formed with a rewiring structure, the control electrode 5 and the first electrode of the wafer are the control electrode and the first electrode of the finally obtained chip. If the front surface of the wafer is provided with rewiring
In this embodiment, the first electrode of the chip may be regarded as a conductive column electrically connected to the control electrode of the wafer.
In one embodiment, the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode
Is a gate. Of course, in other embodiments, the first pole may also be the drain and the second pole the source. 0 in one embodiment, the carrier plate 20 may be circular, rectangular, or other shape. The carrier plate 20 can
The substrate may be a small-sized wafer substrate or a larger-sized carrier, such as a stainless steel plate substrate or a polymer substrate.
The first intermediate structure as shown in fig. 4 can be obtained by step S110. The chip 10 may be bonded by an adhesive layer
Is mounted on the carrier plate 20. The adhesive layer may be of a readily peelable material for subsequent peeling of the carrier plate, for example, a 5-adhesive layer may be of a thermally releasable material which is rendered tacky by heating.
In step S120, an insulating film layer is formed on each of the chip sides, and a gap is formed between two insulating film layers between two adjacent chips.
By this step a second intermediate structure as shown in fig. 5 is obtained. As shown in fig. 5, are positioned adjacent to each other
There is a gap 301 between the two insulating film layers 30 between the two chips 10, and there is no other structure between the two insulating film layers 0.
In one embodiment, the step S120 of forming an insulating film layer on a side surface of each chip, where a gap exists between two insulating film layers between two adjacent chips includes the following steps:
and forming an insulating film layer on the side surface of each chip by adopting a spraying process.
By forming an insulating film layer by spraying an insulating material on the side of the chip by a spraying process, the amount of the sprayed material 5 can be controlled to make the thickness of the insulating film layer thinner, thereby forming two chips 10 between two adjacent chips
The insulating film layers are not connected together, that is, a gap exists between two insulating film layers formed between two adjacent chips 10. It is known that the formation process of the insulating film layer can be simplified by forming the insulating film layer by a spray coating process without performing other process treatments such as cutting on the insulating film layer.
In one embodiment, before the step S120 of forming the insulating film layer on the side of each of the chips, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the chips 10 and the carrier 20, so that the insulating film layer 30 can be more closely connected to the chips 10 and the carrier 20 without delamination or cracking.
In one embodiment, the material of the insulating film layer 30 may be a polymer resin, a resin composite, a polymer composite, or the like.
In step S130, a conductive structure is provided, where the conductive structure includes a first conductive portion located at a side of each chip and a second conductive portion located at a back of each chip, and the first conductive portion is outside an insulating layer located at a side of the chip; the second conductive part at least covers part of the second pole, and the first conductive part at the side part of the chip is connected with the second conductive part at the back side of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
A third intermediate structure as shown in fig. 6 or similar to that shown in fig. 6 may be obtained by step S130. As shown in fig. 6, the conductive structure 40 includes a first conductive portion 41 located at a side portion of the chip 10 and a second conductive portion 42 located at a back surface of each chip 10, and the second conductive portion 42 is connected to the first conductive portion 41. The second pole 13 of the chip 10 is led to the chip front side of the chip 10 through the second conductive portion 42 and the first conductive portion 41 in this order. The material of the first conductive portion 41 may be the same as or different from the material of the second conductive portion 42.
In one embodiment, the step 130 of disposing the conductive structure may include the following steps S131 and S132:
First, in step S131, a conductive material is disposed on the back surface and at least one side of each chip to obtain a second conductive portion located on the back surface of the chip, and a conductive block located at least between two adjacent chips and a second conductive portion located on the back surface of the chip are obtained.
Subsequently, in step S132, the conductive block is cut to form two first conductive portions disposed at intervals.
In step S131, a conductive material may be disposed on the back surface and at least one side of each of the chips, so as to obtain a conductive block located between two adjacent chips, a second conductive portion located on the back surface of the chip, and a first conductive portion located on the outside of the chip where the edge region of the carrier is disposed. The outer side of the chip refers to the side of the chip, which is located in the edge area of the carrier plate and is away from other chips, and no other chips exist outside the chip. The conductive material is disposed on the back surface and at least one side of each of the chips, which is understood to mean that the conductive material is disposed on the back surface and at least one side of each of the chips. The term side portion is understood here to mean the outer surface of the insulating layer provided on the side of the chip. The conductive material may be formed in the same process step or may be formed separately on the back surface and at least one side portion of each of the chips. The conductive material is respectively arranged on the back surface and at least one side part of each chip in the same process step, and the conductive material can be arranged on the back surface and at least one side part of each chip by adopting a sputtering process, a dispensing process and a screen printing process. The back surface and at least one side of each chip are respectively provided with conductive materials which are respectively formed by adopting different process steps, and each part can be formed by one of sputtering process, dispensing process and screen printing process. For example, a dispensing process may be used to provide a conductive material on at least one side of each of the chips, and a sputtering process or a screen printing process may be used to provide a conductive material on the back of each of the chips.
The step S131 may be implemented by providing the conductive material on at least one side of each of the chips and providing the conductive material on the back side of each of the chips through different steps, and in one embodiment, the step S1311 and the step S1312 may be implemented as follows:
In step S1311, a first conductive material is disposed on at least one side of each of the chips, so as to obtain at least a conductive block located between two adjacent chips.
In step S1312, a second conductive material is disposed on the back surface of each of the chips, so as to obtain a second conductive material layer on the back surface of the chip and the top surface of the conductive block.
The fourth intermediate structure shown in fig. 7 can be obtained by step S1311, and the fifth intermediate structure shown in fig. 8 can be obtained by step S1312. As shown in fig. 7, taking the case where conductive materials are provided on opposite sides of each of the chips, for the chip 10 located in the edge region of the carrier 20, a first conductive portion 41 is formed on the outside thereof by providing a first conductive material; a conductive bump 43 is formed between any adjacent two of the chips 10 by disposing a first conductive material. As shown in fig. 8, a second conductive material layer 401 is formed on the chip back surface of the chip 10. The second conductive layer 401 is located on the top surface of the conductive block 43 (i.e., the upper end surface of the conductive block 43 shown in fig. 8) in addition to the back surface of the chip 10. Thus, after the step of dicing the conductive blocks, one first conductive portion 41 is formed on each of opposite sides of each of the chips 10. When the step of cutting the conductive block to form two first conductive portions arranged at intervals, the second conductive layer 401 positioned on the top surface of the conductive block is correspondingly cut, so that the second conductive portions positioned on the top surface of the first conductive portion and the back surface of the chip can be formed. After dicing, obtaining a plurality of intermediate semiconductor structures; in the semiconductor structure, the first conductive portions 41 are formed on opposite sides of each of the chips 10, respectively. Even if one of the first conductive portions 41 and the second electrode 13 are not well electrically connected, the other first conductive portion 41 and the second electrode 13 are electrically connected, so that the second electrode 13 can be guided to the front surface of the chip 10, and the reliability of the semiconductor structure can be improved. In some embodiments, the opposite sides of the chip 10 are respectively provided with one of the first conductive portions. Of course, in other embodiments, some of the chips 10 may be provided with the first conductive portions 41 on only one side portion, or all of the side portions of the chips 10 may be provided with the first conductive portions.
By cutting the conductive block, two objectives can be achieved: cutting the same conductive block into two first conductive portions 41; and dicing the plate-like semiconductor intermediate assembly into a plurality of intermediate semiconductor structures. The plurality of intermediate semiconductor structures after dicing can be used as a final semiconductor device or semiconductor device for some products without the need for other structures such as protective layers, ball implants, etc. to be subsequently provided. For the subsequent protection layer to be provided in the present application, the semiconductor structure may be understood as an intermediate (hereinafter referred to as an intermediate semiconductor structure), and the final semiconductor structure or semiconductor device may be formed after the subsequent protection layer formation or after other structures are provided (e.g., as shown in fig. 15, 16, 18, and 19). It will be appreciated that by providing the gap 301 between two insulating film layers between two adjacent chips, the number of cuts during the fabrication of the semiconductor structure can be reduced, which helps to simplify the fabrication process.
After dicing the conductive blocks of the fifth intermediate structure shown in fig. 8, a third semiconductor structure having a plurality of spaced intermediate semiconductor structures therein as shown in fig. 6 can be obtained. In the third intermediate structure shown in fig. 6, the second conductive portion 42 on the chip back surface of the chip 10 covers a part of the area on the chip back surface, so that the second conductive portion 42 covers a part of the area on the chip back surface of the chip 10 in each intermediate semiconductor structure and the finally formed semiconductor structure (for example, fig. 15); and the second conductive portion 42 includes two sub-conductive portions 421 disposed at intervals, and each sub-conductive portion 421 is in contact with one of the first conductive portions 41.
In another embodiment, the second conductive portion 42 covers a part of the area of the back surface of the chip 10, and then the resulting semiconductor structure is shown in fig. 16, where the second conductive portion 42 covers the whole area of the back surface of the chip 10, and the second conductive portion 42 is electrically connected to the two first conductive portions 41, respectively.
In another embodiment, the step 130 of disposing the conductive structure may include the following steps S133 to S135:
In step S133, a first preset conductive member is disposed on at least one side of each of the chips; the first preset conductive piece comprises a conductive block, and the conductive block is arranged between two adjacent chips.
In step S134, a conductive material is disposed on the back surface of each of the chips, and a second conductive material layer is formed on the back surface of the chip and the top surface of the conductive block.
In step S135, the conductive block is cut, and the second conductive layer on the surface of the conductive block is cut, so as to form two first conductive portions disposed at intervals, and second conductive portions disposed on the top surface of the first conductive portions and on the back surface of the chip, thereby obtaining a plurality of intermediate semiconductor structures.
The first preset conductive member may be prepared in advance according to the size of the gap between the adjacent chips, the size of the first conductive portion, and the like. As shown in fig. 9, the first preset conductive member includes a conductive block 43 that can be disposed between two adjacent chips, and may further include a first conductive portion 41 for being disposed outside the chip in the edge area.
Accordingly, before step S133, the method may further include forming a first preset conductive member.
Optionally, in some embodiments, after the first preset conductive member is formed, before step S133, a first adhesive material layer 51 may be further disposed on a sidewall of the first preset conductive member, so that the first preset conductive member may be adhered to the second intermediate structure obtained in step S120 through the first adhesive material layer. Of course, in other embodiments, the first adhesive layer may not be provided, and the bonding may be achieved by providing an adhesive on the chip side of the second intermediate structure.
As shown in fig. 9 to 11, a sixth intermediate structure as shown in fig. 10 can be obtained through step S133. As shown in fig. 10, taking the example that the opposite sides of the chip are provided with the first conductive parts, for the chip 10 located in the edge area of the carrier 20, the outside of the chip is provided with the preset first conductive parts 41; a preset conductive block 43 is disposed between any two adjacent chips 10 to form a sixth intermediate structure similar to the fourth intermediate structure shown in fig. 7. Accordingly, a seventh intermediate structure as shown in fig. 11 can be obtained through step S134. This seventh intermediate structure is similar to the fifth intermediate structure shown in fig. 8. A third intermediate structure similar to that shown in fig. 6 can be obtained by step S135. Similar or identical to the above, reference is made to the above related description, which is not described in detail here. In some embodiments, the opposite sides of the chip 10 are respectively provided with one of the first conductive portions. Likewise, in other embodiments, some of the chips 10 may be provided with the first conductive portions 41 on only one side portion, or all of the side portions of the chips 10 may be provided with the first conductive portions.
In yet another embodiment, the step 130 of disposing the conductive structure may include the following steps S136 to S137:
In step S136, a second preset conductive member is disposed on at least one side of each of the chips; the second preset conductive piece comprises a conductive block and an extension part which is electrically connected to the end part of the conductive block and extends transversely; the conductive blocks are positioned between two adjacent chips, and the extending parts are positioned on the back surfaces of the corresponding chips to form corresponding second conductive parts;
In step S137, the conductive block is cut to form two first conductive portions disposed at intervals, and a second conductive portion connected to an end of the first conductive portion and located on the back surface of the chip, so as to obtain a plurality of intermediate semiconductor structures.
The second preset conductive member may be prepared in advance according to the size of the gap between the adjacent chips, the size of the first conductive portion, and the like. As shown in fig. 12, the second preset conductive member includes a conductive block 43 capable of being disposed between two adjacent chips and an extension 402 electrically connected to an end of the conductive block and extending in a lateral direction. The second preset conductive element 44 may further include preset conductive structures 40 for placement outside the edge area chip.
Accordingly, before step S136, the method may further include forming a second preset conductive member.
Optionally, in some embodiments, after the second preset conductive element is formed, before step S136, a second adhesive material layer 52 may be further disposed on a sidewall of the second preset conductive element, and a third adhesive material layer 53 may be disposed on a surface of the extension 402 disposed toward the back surface of the chip, so that the second preset conductive element may be adhered to the second intermediate structure obtained in step S120 through the second adhesive material layer 52 and the third adhesive material layer 53. Here, the materials of both the second adhesive layer 52 and the third adhesive layer 53 may be the same or different. The third adhesive layer 53 is formed of a conductive adhesive. The material conductivity of the second adhesive layer 52 is not limited. The second adhesive layer 52 and the third adhesive layer 53 may be provided separately or may be formed in the same process. Of course, in other embodiments, the second and third adhesive layers may not be provided, and the bonding may be achieved by providing an adhesive on the die side of the second intermediate structure.
As shown in fig. 12 and 13, an eighth intermediate structure as shown in fig. 13 can be obtained by step S136. As shown in fig. 13, this eighth intermediate structure is similar to the fifth intermediate structure shown in fig. 8, taking here the example that the opposite sides of the chip are provided with the first conductive portions. A third intermediate structure similar to that shown in fig. 6 can be obtained by step S137. Similar or identical to the above, reference is made to the above related description, which is not described in detail here. Likewise, in other embodiments, only one of the opposite sides of some of the chips 10 may be provided with the first conductive portions 41.
In step S140, a protective layer is formed, where the protective layer is at least located on a surface of the conductive structure facing away from the chip.
In some embodiments, after the third intermediate structure shown in fig. 6 is formed in step S130, a protective layer 60 may be disposed on each intermediate semiconductor structure on the carrier in the third intermediate structure, forming a ninth intermediate structure shown in fig. 14.
The protective layer 60 may be provided here by sputtering or otherwise on each intermediate semiconductor structure. The material of the protection layer 60 is an oxidation-resistant metal material. For example, the material may be stainless steel.
Further, the carrier plate is removed, and a plurality of semiconductor structures are formed.
For example, in some embodiments, after removing the carrier 20 of the ninth intermediate structure shown in fig. 14, a plurality of semiconductor structures shown in fig. 15 may be formed. For the second conductive portion 42 covering the entire area of the chip back surface, the semiconductor structure as shown in fig. 16 may be correspondingly formed after removing the carrier plate 20. The control electrode 11, the first electrode 12 and the first conductive portion 41 of the semiconductor structure shown in fig. 15 or 16 may be directly soldered on a circuit board as a semiconductor product or a semiconductor device (such as a wafer level power device).
In this embodiment, after the conductive block is cut, the protective layer 60 is formed first, and then the carrier plate is removed. I.e. the protective layer 60 is formed before removing the carrier plate 20. In other embodiments, the carrier plate may also be removed prior to cutting the conductive bumps, or after cutting the conductive bumps, and prior to forming the protective layer 60. I.e. the protective layer 60 is formed after removal of the carrier 20.
For example, in one embodiment, the carrier plate may be removed prior to the step of dicing the conductive block to obtain a plate-like semiconductor intermediate assembly. The conductive blocks of the plate-shaped semiconductor intermediate assembly are cut to obtain a plurality of intermediate semiconductor structures, and then a protective layer is arranged outside the intermediate semiconductor structures to form a final semiconductor structure (such as the semiconductor structures shown in fig. 15 and 16).
Some semiconductor structures, such as conductive balls, are disposed on the bottom of the first semiconductor and on the surfaces of the first electrode 12 and the control electrode 11, as required by the product. Accordingly, in one embodiment, before the conductive block is cut in the process of performing step 130, the manufacturing method further includes the following process:
firstly, removing the carrier plate to obtain a plate-shaped semiconductor intermediate assembly.
Then, forming a plurality of conductive balls on one side of the platy semiconductor intermediate component, which is far away from the back surface of the chip, by adopting a ball implantation process, wherein the control electrode and the first electrode are respectively and electrically connected with at least one conductive ball; the conductive block is electrically connected with at least two conductive balls.
A tenth intermediate structure as shown in fig. 17 can be obtained by the above steps. As shown in fig. 17, a plurality of conductive balls 70 are formed on the plate-like semiconductor intermediate member on the side of the chip back surface facing away from the chip 10. The first conductive portion 41 is connected to one conductive ball 70, the control electrode 11 and the first electrode 12 are connected to two conductive balls 70, and the conductive block 43 is connected to two conductive balls 70.
Accordingly, after dicing the conductive bumps 43, a plurality of intermediate semiconductor structures with conductive balls 70 may be obtained.
In the intermediate semiconductor structure obtained by cutting the conductive blocks, each of the first conductive portions 41 is electrically connected to at least one of the conductive balls 70.
After obtaining a plurality of intermediate semiconductor structures with conductive balls, the method of manufacturing includes:
and forming a protective layer at least on the surface of the conductive structure, which is away from the chip, on the outer side of the formed intermediate semiconductor structure to form the semiconductor structure.
The semiconductor structure having the protective layer 60 as shown in fig. 18 and 19 can be formed through the above steps. The first conductive portion 41 is connected to one conductive ball 70, and the control electrode 11 and the first electrode 12 are connected to two conductive balls 70, respectively. The control electrode 11, the first electrode 12 and the first conductive portion 41 of the semiconductor structure can be soldered on the circuit board through the conductive balls 70, so as to facilitate connection of the semiconductor structure and the circuit board. The material of the conductive balls 70 may be metallic tin.
In the tenth intermediate structure shown in fig. 17, the second conductive portion 42 covers a part of the area of the back surface of the chip 10, and in the semiconductor structure shown in fig. 18 obtained by cutting the tenth intermediate structure shown in fig. 17 and providing the protective layer 60, the second conductive portion 42 covers a part of the area of the back surface of the chip 10, and the second conductive portion 42 includes two sub-conductive portions 421 disposed at intervals, each sub-conductive portion 421 being in contact with one of the first conductive portions 41. When the second conductive portion 42 covers the entire area of the back surface of the chip, the semiconductor structure shown in fig. 19 can be finally obtained.
The embodiment of the application also provides a semiconductor structure. As shown in fig. 15, 16, 18 and 19, the semiconductor structure includes a chip 10, an insulating film layer 30 located on at least one side of the chip 10, a conductive structure 40 and a protective layer 60. The chip 10 includes a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of sides connecting the chip front surface and the chip back surface, and the chip 10 includes a control electrode 11 and a first electrode 12 disposed on the chip front surface, and a second electrode 13 disposed on the chip back surface. The conductive structure 40 includes a first conductive portion 41 located at a side of the chip (i.e., at a side of the insulating film layer 30 away from the chip 10) and a second conductive portion 42 located at a back surface of the chip 10, where the second conductive portion 42 covers at least a portion of the second pole 13, and the first conductive portion 41 is connected to the second conductive portion 42 at the back surface of the chip. The surface of the first conductive part 41 facing away from the back surface of the chip, the surface of the control electrode 11 facing away from the back surface of the chip, and the surface of the first electrode 12 facing away from the back surface of the chip are on the same plane. The protective layer 60 is at least located on a surface of the conductive structure facing away from the chip 10.
In one embodiment, the opposite sides of the core 10 are respectively provided with a first conductive portion 41, and the second conductive portion 42 on the back surface of the chip 10 is respectively connected to both the first conductive portions 41.
In one embodiment, as shown in fig. 18 and 19, the semiconductor structure further includes a plurality of conductive balls 70 located on the front side of the chip 10, and the first conductive portion 41, the control electrode 11, and the first electrode 12 are electrically connected to at least one of the conductive balls 70, respectively.
In some embodiments, the protective layer 60 is a structural layer formed of an oxidation resistant material.
In one embodiment, the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode. Of course, in other embodiments, the first pole may also be the drain and the second pole the source.
Embodiments of the method for manufacturing a semiconductor structure provided in the embodiments of the present application and embodiments of the semiconductor structure belong to the same inventive concept, and descriptions of related details and beneficial effects may be referred to each other, and are not repeated here.
It is noted that in the drawings, the size of layers and regions may be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer or element may also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (16)

1. A method of manufacturing a semiconductor structure, the method comprising:
Mounting a plurality of chips on a carrier plate, wherein adjacent chips are arranged at intervals; the chip comprises a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces for connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface;
Forming an insulating film layer on the side surface of each chip, wherein a gap exists between two insulating film layers between two adjacent chips;
Providing a conductive structure, wherein the conductive structure comprises a first conductive part positioned at the side part of each chip and a second conductive part positioned at the back of each chip, and the first conductive part is outside an insulating layer positioned at the side surface of each chip; the second conductive part at least covers part of the second pole, and the first conductive part at the side part of the chip is connected with the second conductive part at the back side of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane;
and forming a protective layer, wherein the protective layer is at least positioned on the surface of the conductive structure, which is away from the chip.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein forming an insulating film layer on a side surface of each of the chips with a gap between two of the insulating film layers between two adjacent chips, comprises:
and forming an insulating film layer on the side surface of each chip by adopting a spraying process.
3. The method of manufacturing a semiconductor structure according to claim 1, wherein the disposing a conductive structure comprises:
arranging conductive materials on the back surface and at least one side part of each chip to obtain a second conductive part positioned on the back surface of each chip and a conductive block positioned between at least two adjacent chips;
and cutting the conductive block to form two first conductive parts which are arranged at intervals.
4. A method of fabricating a semiconductor structure according to claim 3, wherein said providing conductive material on the back side and at least one side of each of said chips to provide a second conductive portion on the back side of said chip and to provide a conductive bump between at least two adjacent ones of said chips, comprises:
Arranging a first conductive material on at least one side part of each chip to obtain a conductive block at least between two adjacent chips;
Setting a second conductive material on the back of each chip to obtain a second conductive material layer positioned on the back of each chip and the top surface of each conductive block;
And when the conductive block is cut, cutting the second conductive layer on the surface of the conductive block to form a second conductive part positioned on the top surface of the first conductive part and the back surface of the chip.
5. The method of manufacturing a semiconductor structure according to claim 3, wherein said disposing a conductive material on a back surface and at least one side portion of each of said chips comprises:
a sputtering process is adopted to set conductive materials on the back surface and at least one side part of each chip; or alternatively
Setting conductive materials on the back surface and at least one side part of each chip by adopting a dispensing process; or alternatively
Setting conductive materials on at least one side part of each chip and the back of the chip by adopting a screen printing process; or alternatively
And setting conductive materials on at least one side part of each chip by adopting a dispensing process, and setting conductive materials on the back surface of each chip by adopting a sputtering process or a screen printing process.
6. The method of manufacturing a semiconductor structure according to claim 1, wherein the disposing a conductive structure comprises:
Arranging a first preset conductive piece on at least one side part of each chip; the first preset conductive piece comprises a conductive block, and the conductive block is arranged between two adjacent chips;
arranging conductive materials on the back surfaces of the chips to form a second conductive material layer positioned on the back surfaces of the chips and the top surfaces of the conductive blocks;
And cutting the conductive block, and cutting the second conductive layer on the surface of the conductive block to form two first conductive parts arranged at intervals, and second conductive parts positioned on the top surface of the first conductive parts and the back surface of the chip.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein before disposing the first predetermined conductive member on at least one side of each of the chips, the method comprises:
Forming a first preset conductive member;
a first adhesive material layer is arranged on the side wall of the first preset conductive piece.
8. The method of manufacturing a semiconductor structure according to claim 1, wherein the disposing a conductive structure comprises:
a second preset conductive element is arranged on at least one side part of each chip; the second preset conductive piece comprises a conductive block and an extension part which is electrically connected to the end part of the conductive block and extends transversely; the conductive blocks are positioned between two adjacent chips, and the extending parts are positioned on the back surfaces of the corresponding chips to form corresponding second conductive parts;
And cutting the conductive block to form two first conductive parts which are arranged at intervals, and connecting the end parts of the first conductive parts and the second conductive parts positioned on the back surface of the chip.
9. The method of manufacturing a semiconductor structure according to claim 8, comprising, before disposing a second predetermined conductive member on at least one side of each of the chips:
Forming a second preset conductive member;
A second bonding material layer is arranged on the side wall of the second preset conductive piece, and a third bonding material layer is arranged on the surface, which is arranged towards the back surface of the chip, of the extension part; wherein the third bonding material layer is formed by adopting a conductive bonding material.
10. The method of manufacturing a semiconductor structure according to any one of claims 3, 6, and 8, wherein before the dicing the conductive block, the method further comprises:
removing the carrier plate to obtain a platy semiconductor intermediate assembly;
forming a plurality of conductive balls on one side of the platy semiconductor intermediate assembly, which is far away from the back surface of the chip, by adopting a ball implantation process, wherein the control electrode and the first electrode are respectively and electrically connected with at least one conductive ball; the conductive block is electrically connected with at least two conductive balls;
After the conductive blocks are cut, a plurality of intermediate semiconductor structures are obtained, and each first conductive part is electrically connected with at least one conductive ball.
11. The method of manufacturing a semiconductor structure according to claim 10, wherein after obtaining a plurality of intermediate semiconductor structures, the method of manufacturing comprises:
and forming a protective layer at least on the surface of the conductive structure, which is away from the chip, on the outer side of the formed intermediate semiconductor structure to form the semiconductor structure.
12. The method for manufacturing a semiconductor structure according to any one of claims 3, 6, and 8, wherein after the dicing the conductive block, the method further comprises:
forming the protective layer outside the first conductive part and the second conductive part;
And removing the carrier plate to form a plurality of semiconductor structures.
13. The method of manufacturing a semiconductor structure according to claim 1, wherein the protective layer is formed by a sputtering process; and/or the number of the groups of groups,
The material of the protective layer is an antioxidant metal material.
14. The method of manufacturing a semiconductor structure according to claim 1, wherein the second conductive portion covers an entire area of the back surface of the chip or a partial area of the back surface of the chip.
15. A semiconductor structure, the semiconductor structure comprising:
The chip comprises a chip front surface, a chip back surface opposite to the chip front surface and a plurality of side surfaces for connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface and a second electrode which is arranged on the chip back surface;
The insulating film layer is positioned on the side surface of the chip;
The conductive structure comprises a first conductive part positioned at the side part of the chip and a second conductive part positioned at the back of the chip, wherein the second conductive part at least covers part of the second pole, and the first conductive part at the side part of the chip is connected with the second conductive part at the back of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane;
and the protective layer is positioned on the surface of the conductive structure, which is away from the chip.
16. The semiconductor structure of claim 15, further comprising a plurality of conductive balls on a front side of the die, the first conductive portion, the control electrode, and the first electrode each being electrically connected to at least one of the conductive balls.
CN202211665728.7A 2022-12-23 2022-12-23 Method for manufacturing semiconductor structure and semiconductor structure Pending CN118248557A (en)

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