CN118248216A - Verification analysis method and device, electronic equipment and storage medium - Google Patents
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Abstract
The disclosure provides a method, a device, electronic equipment and a storage medium for verification analysis, wherein the method, the device, the electronic equipment and the storage medium are used for processing a sample on-off information table according to an input sample on-off information table to obtain first sample information; verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification; analyzing the second sample information to obtain a quality inspection result of each sample; and generating the verification result based on the quality inspection result. Compared with the related art, the quality inspection method and device for the input samples are characterized in that after the input samples are analyzed in the machine-off information table, detection and analysis are carried out according to the obtained sample information, and quality inspection results of each sample are obtained; and judging whether the sequencer is qualified or not according to the obtained quality inspection result. The automatic analysis of verification and confirmation of the sequencer can be realized, and the investment of human resources is further reduced.
Description
Technical Field
The disclosure relates to the technical field of data processing, and in particular relates to a method and device for verification analysis, electronic equipment and a storage medium.
Background
High throughput sequencing techniques are also known as "next generation" sequencing techniques or large-scale parallel sequencing. In contrast to traditional dideoxy (Sanger) sequencing, high throughput sequencing techniques can sequence hundreds of thousands to millions of DNA molecules at a time; has the advantages of high flux, low cost, accurate sequencing, and the like.
The high-throughput sequencer is subjected to strict Verification and Validation (V & V) on the aspects of equipment, reagents, algorithms, processes and the like every time, because any form of change and upgrade can bring about positive or negative influence on the output, quality and stability of the off-machine data of the sequencer; therefore, only the changes and upgrades after verification and validation can be released on the market.
In general, a sequencer can be applied to various scenes, especially to a high-flux sequencer, the application fields related to the sequencer are very wide, and the sequencer can be applied to the application scenes such as whole genome sequencing, whole exon sequencing, tumor Panel sequencing, common transcriptome and microbial genome sequencing, environmental sample pathogen detection, single cell sequencing, noninvasive prenatal detection and the like, and the sequencer can cover the fields such as agriculture, medicine, scientific research and judicial. However, for testing and verification, a wide application scenario brings great trouble to verification and validation, and because the analysis method and quality control standard of each application type are different, the steps of manual participation are very numerous, and the workload is very large.
Disclosure of Invention
The present disclosure provides a method, apparatus, electronic device, and storage medium for verification analysis. The method is mainly used for realizing automatic analysis during verification and confirmation of the high-throughput sequencer.
According to a first aspect of the present disclosure, there is provided a method of validating an analysis, comprising:
processing the sample on-machine information table according to the recorded sample on-machine information table to obtain first sample information;
Verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification;
analyzing the second sample information to obtain a quality inspection result of each sample;
And generating a verification result of the sequencer based on the quality inspection result.
Optionally, before the sample on-hook information table is processed according to the entered sample on-hook information table to obtain the first sample information, the method further includes:
Constructing a standard sample off-machine information table according to different sequencing types; wherein, the standard sample machine-off information table includes: sample number, sample name, sequencing platform, chip number, flow cell number, barcode number, sequencing strategy, analysis type, library building mode, species information, standard, capture probe, off-chip data path.
Optionally, the processing the sample unloading information table according to the entered sample unloading information table to obtain first sample information includes:
Generating a hash table taking the sample number as a key value according to the sample off-machine information table;
Acquiring first sample information based on the hash table; wherein the first sample information includes: the sample sequencing data, sample sequencing data path, and sequencing type corresponding to each sample.
Optionally, the verifying the first sample information, and obtaining second sample information includes:
determining whether the sample sequencing data path is present;
If so, determining that the verification passes;
If the verification is not successful, the verification is stopped, and the verification failure reason is returned.
Optionally, the analyzing the second sample information to obtain a quality inspection result of each sample includes:
Respectively selecting corresponding preset letter analysis flows according to the sequencing types of each sample;
Analyzing sample sequencing data of each sample according to the selected preset raw message analysis flow;
And carrying out quality detection on the analysis result of the sample sequencing data based on a preset quality detection algorithm, and generating a quality detection result.
Optionally, generating the verification result of the sequencer based on the quality inspection result includes:
And judging whether the sequencer is qualified or not based on the quality inspection result, and generating a verification report.
Optionally, after processing the sample on-hook information table according to the entered sample on-hook information table to obtain the first sample information, the method further includes:
And analyzing the data quantity, the resolution ratio and the sequencing error rate of each flow channel in each chip based on the off-chip data path, and generating a chip quality report.
According to a second aspect of the present disclosure, there is provided an apparatus for verification analysis, comprising:
The processing unit is used for processing the sample on-off information table according to the recorded sample on-off information table to obtain first sample information;
the verification unit is used for verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification;
the analysis unit is used for analyzing the second sample information to obtain a quality inspection result of each sample;
the first generation unit is used for generating the verification result based on the quality inspection result.
Optionally, the apparatus further includes:
The construction unit is used for constructing a standard sample off-machine information table according to different sequencing types before the processing unit processes the sample off-machine information table to obtain first sample information; wherein, the standard sample machine-off information table includes: sample number, sample name, sequencing platform, chip number, flow cell number, barcode number, sequencing strategy, analysis type, library building mode, species information, standard, capture probe, off-chip data path.
Optionally, the processing unit includes:
the generation module is used for generating a hash table taking the sample number as a key value according to the sample off-machine information table;
The acquisition module is used for acquiring first sample information based on the hash table; wherein the first sample information includes: the sample sequencing data, sample sequencing data path, and sequencing type corresponding to each sample.
Optionally, the verification unit includes:
A first judgment module for judging whether the sample sequencing data path exists;
the determining module is used for determining that the verification passes when the first judging module judges that the sample sequencing data path exists;
And the feedback module is used for determining that the verification fails when the first judging module judges that the sample sequencing data path does not exist, stopping verification and returning the verification failure reason.
Optionally, the analysis unit includes:
The selection module is used for respectively selecting corresponding preset raw message analysis flows according to the sequencing type of each sample;
The analysis module is used for respectively analyzing the sample sequencing data of each sample according to the selected preset raw message analysis flow;
The detection module is used for carrying out quality detection on the analysis result of the sample sequencing data based on a preset quality detection algorithm and generating a quality detection result.
Optionally, the first generating unit is further configured to:
And judging whether the sequencer is qualified or not based on the quality inspection result, and generating a verification report.
Optionally, the apparatus further includes:
The second generating unit is used for analyzing the data volume, the resolution ratio and the sequencing error rate of each flow slot in each chip based on the chip on-machine-down data path after the processing unit processes the sample on-machine-down information table to obtain the first sample information, and generating a chip quality report.
According to a third aspect of the present disclosure, there is provided an electronic device comprising:
at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of the first aspect.
According to a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of the preceding first aspect.
According to a fifth aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the method of the first aspect described above.
The disclosure provides a method, a device, electronic equipment and a storage medium for verification analysis, wherein the method, the device, the electronic equipment and the storage medium are used for processing a sample on-off information table according to an input sample on-off information table to obtain first sample information; verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification; analyzing the second sample information to obtain a quality inspection result of each sample; and generating the verification result based on the quality inspection result. Compared with the related art, the quality inspection method and device for the input samples are characterized in that after the input samples are analyzed in the machine-off information table, detection and analysis are carried out according to the obtained sample information, and quality inspection results of each sample are obtained; and judging whether the sequencer is qualified or not according to the obtained quality inspection result. The automatic analysis of verification and confirmation of the sequencer can be realized, and the investment of human resources is further reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows.
Drawings
The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:
FIG. 1 is a flow chart of a method of verification analysis provided in an embodiment of the present disclosure;
FIG. 2 is a flow chart of another method of verification analysis provided by an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of an apparatus for verification analysis according to an embodiment of the present disclosure;
FIG. 4 is a schematic structural diagram of another device for verification analysis according to an embodiment of the present disclosure;
Fig. 5 is a schematic block diagram of an example electronic device 400 provided by an embodiment of the disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Methods, apparatuses, electronic devices, and storage media for verification analysis of embodiments of the present disclosure are described below with reference to the accompanying drawings.
Fig. 1 is a flow chart of a method for verifying analysis according to an embodiment of the disclosure.
As shown in fig. 1, the method comprises the steps of:
And step 101, processing the sample on-line information table according to the recorded sample on-line information table to obtain first sample information.
At present, no standardized automatic flow for sequencer data V & V is available, basically manual operation is adopted, input files are arranged according to basic information of samples, such as chips, flow channels (Lane), bar codes (barcode), data paths and the like, flow configuration files are prepared according to differences of analysis types, and tasks are submitted manually after verification of the input information is correct.
In the embodiment of the disclosure, a standard sample machine-entering information table is designed, which can be an Excel table (xlsx standard format) without limitation, and the form template is fixed, and only information needs to be filled in according to the requirement according to the actual test condition. And inputting the test result into a sample unloading information table, and processing the sample unloading information table to obtain sample information about the test sample.
Step 102, verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification.
After the first sample information is acquired, the sample information needs to be judged. If the test staff leaks or misplaces part of the machine-starting results, the accuracy of the subsequent test results can be caused; for example, a sample may correspond to a plurality of barcode, and a tester may fill in a plurality of barcode with errors, which may result in the accuracy of the subsequent test results. The first sample information contains the error sample information; and checking the first sample information to obtain second sample information. And carrying out next quality detection analysis by using the second sample information.
And step 103, analyzing the second sample information to obtain a quality inspection result of each sample.
And extracting the analysis type recorded in the second sample information according to the obtained second sample information. And obtaining the analysis type corresponding to each sample, and placing samples with consistent analysis types together for batch analysis due to different analysis methods of different application types. As shown in table 1, the embodiment of the disclosure has 8 sequencing types, according to the sequencing type of each sample, 8 different running task scripts are automatically divided, input files and parameter files of 8 corresponding analysis flows are automatically configured, then tasks are automatically triggered, and the whole task running adopts a parallel mode, so that the whole running time is saved. And carrying out quality inspection on the result file generated by the task script according to the formulated quality inspection standard, and generating a quality inspection result file. It should be noted that the sequencing types in the embodiments of the present disclosure are illustrated by 8 examples, but this is merely exemplary and does not constitute a limitation on the number of sequencing types.
TABLE 1
| Sequencing type | Number of samples |
| Whole genome sequencing | 4 |
| Full exon sequencing | 3 |
| Transcriptome sequencing | 3 |
| Tumor Panel sequencing | 3 |
| Single cell sequencing | 7 |
| Non-invasive prenatal detection sequencing | 12 |
| Single-cell sequencing | 5 |
| Environmental microbiological sequencing | 6 |
And 104, generating a verification result of the sequencer based on the quality inspection result.
The quality inspection result file obtained in the step 103 can intuitively display the quality of a certain sequencing function of the sequencer, and can also reflect the quality of a certain sequencing function in a scoring evaluation mode; the quality inspection result file reflects a certain sequencing function of the sequencer, and one sequencer can perform various sequencing works, so that whether the sequencer is qualified or not needs to be judged according to the quality inspection result files corresponding to all the sequencing functions of the sequencer.
The disclosure provides a verification analysis method, which is used for processing a sample on-off information table according to an input sample on-off information table to obtain first sample information; verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification; analyzing the second sample information to obtain a quality inspection result of each sample; and generating the verification result based on the quality inspection result. Compared with the related art, the quality inspection method and device for the input samples are characterized in that after the input samples are analyzed in the machine-off information table, detection and analysis are carried out according to the obtained sample information, and quality inspection results of each sample are obtained; and judging whether the sequencer is qualified or not according to the obtained quality inspection result. The automatic analysis of verification and confirmation of the sequencer can be realized, and the investment of human resources is further reduced.
As an achievable manner of the embodiment of the disclosure, before processing the sample on-coming information table according to the entered sample on-coming information table to obtain the first sample information, the method further includes:
Constructing a standard sample off-machine information table according to different sequencing types; wherein, the standard sample machine-off information table includes: sample number, sample name, sequencing platform, chip number, flow cell number, barcode number, sequencing strategy, analysis type, library building mode, species information, standard, capture probe, off-chip data path.
Specifically, in the embodiment of the disclosure, according to different sequencing types, filling templates of different standard sample unloading information tables are designed, for example:
1) For whole genome sequencing/transcriptome sequencing/single cell sequencing
The sample machine-off information table comprises: sample number, sample name, sequencing platform, chip number, lane number, barcode number, sequencing strategy, analysis type, database building mode, species information, standard, off-chip data path and other fields.
2) For whole exon sequencing/tumor Panel sequencing
The sample machine-off information table comprises: sample number, sample name, sequencing platform, chip number, lane number, barcode number, sequencing strategy, analysis type, database creation mode, species information, standard, capture probe, off-chip data path and other fields.
3) Microbial sequencing of environmental samples
The sample machine-off information table comprises: sample number, sample name, sequencing platform, chip number, lane number, barcode number, sequencing strategy, analysis type, database creation mode, species information, standard, host information, off-chip data path and other fields.
4) For non-invasive prenatal detection sequencing
The sample machine-off information table comprises: sample number, sample name, sequencing platform, chip number, lane number, barcode number, sequencing strategy, analysis type, database building mode, standard, off-chip data path and other fields.
As an achievable manner of the embodiment of the disclosure, after processing the sample on-machine information table according to the entered sample on-machine information table to obtain the first sample information, the method further includes:
And analyzing the data quantity, the resolution ratio and the sequencing error rate of each flow channel in each chip based on the off-chip data path, and generating a chip quality report.
Specifically, according to the off-chip data path, counting and analyzing the data quantity, the resolution ratio and the sequencing error rate of each Lane of each chip; the generated chip quality report is used for presenting the overall data output and the data quality condition of the chip.
Fig. 2 is a flow chart of another method for verification analysis provided in an embodiment of the present disclosure.
As shown in fig. 1, the method comprises the steps of:
Step 201, generating a hash table taking the sample number as a key value according to the sample off-machine information table.
Firstly, analyzing an entered sample unloading information table, and then generating a hash table taking a sample number as a key value, so that the mapping relation between the sample number and each field in the sample unloading information table can be obtained; by using the method for establishing the hash table, the subsequent analysis and processing of the sample information can be facilitated.
Step 202, acquiring first sample information based on the hash table; wherein the first sample information includes: the sample sequencing data, sample sequencing data path, and sequencing type corresponding to each sample.
Sample information corresponding to the sample number can be obtained by utilizing the hash table; furthermore, sample sequencing data can be captured by using a chip number, a Lane number and a barcode number, a data path corresponding to each sample is obtained, a corresponding application type is captured according to an 'analysis type' field, and other information can be captured in the same way.
Step 203, determining whether the sample sequencing data path exists.
The verification of the sample information table is to search according to the sample sequencing data path, and the system verifies the sample sequencing data path obtained in the step 202;
step 204, if present, determining that the verification passes.
If the sample sequencing data path is found to be present, it is interpreted that the sample information is filled out without error, and the process continues to step 206.
Step 205, if not, determining that the verification is not passed, stopping the verification, and returning to the verification failure reason.
If the sample sequencing data path is found to be absent, the sample information is filled in error, the system can interrupt exiting, and the error reason is returned for checking. Until the submitted sample list is correct, the process can not be used for the next link.
Step 206, selecting corresponding preset letter analysis flows according to the sequencing types of each sample.
The samples are classified according to the sequencing types, and samples with consistent sequencing types are put together for batch analysis due to different analysis methods of different sequencing types.
Step 207, analyzing the sample sequencing data of each sample according to the selected preset biological analysis procedure.
Each sequencing type has a corresponding raw message analysis flow, and the corresponding raw message analysis flow is selected according to the sequencing type of the sample. By using one or more preset letter analysis software, the whole genome sequencing letter analysis, the whole exon sequencing letter analysis, the tumor Panel sequencing letter analysis, the single cell sequencing letter analysis, the environmental microorganism sequencing letter analysis, the transcriptome sequencing letter analysis and the noninvasive prenatal detection analysis can be realized.
And step 208, performing quality detection on the analysis result of the sample sequencing data based on a preset quality detection algorithm, and generating a quality detection result.
The preset quality inspection algorithm is to process an analysis result generated by using the raw information analysis software according to a preset quality inspection standard and generate a quality inspection result file. The sequencing functions which can be realized by different sequencers are different, and the corresponding raw letter analysis is different. It should be noted that the embodiments of the present disclosure are not limited to the pre-established quality inspection standards.
Step 209, based on the quality inspection result, judging whether the sequencer is qualified, and generating a verification report.
The quality inspection result file can intuitively display the quality of a certain sequencing function of the sequencer, and can also reflect the quality of the certain sequencing function in a scoring evaluation mode; the quality inspection result file reflects a certain sequencing function of the sequencer, and one sequencer can perform various sequencing works, so that whether the sequencer is qualified or not needs to be judged according to the quality inspection result files corresponding to all the sequencing functions of the sequencer.
Corresponding to the method for verifying and analyzing, the invention also provides a device for verifying and analyzing. Since the device embodiment of the present invention corresponds to the above-mentioned method embodiment, details not disclosed in the device embodiment may refer to the above-mentioned method embodiment, and details are not described in detail in the present invention.
Fig. 3 is a schematic structural diagram of an apparatus for verification and analysis according to an embodiment of the disclosure, as shown in fig. 3, including: a processing unit 31, a verification unit 32, an analysis unit 33 and a first generation unit 34.
The processing unit 31 is configured to process the sample on-machine information table according to the entered sample on-machine information table, so as to obtain first sample information;
A verification unit 32, configured to verify the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification;
An analysis unit 33, configured to analyze the second sample information to obtain a quality inspection result of each sample;
A first generating unit 34, configured to generate a verification result of the sequencer based on the quality inspection result.
Further, in a possible implementation manner of this embodiment, as shown in fig. 4, the apparatus further includes:
A construction unit 35, configured to construct a standard sample unloading information table according to different sequencing types before the processing unit 31 processes the sample unloading information table to obtain first sample information; wherein, the standard sample machine-off information table includes: sample number, sample name, sequencing platform, chip number, flow cell number, barcode number, sequencing strategy, analysis type, library building mode, species information, standard, capture probe, off-chip data path.
Further, in one possible implementation manner of this embodiment, as shown in fig. 4, the processing unit 31 includes:
a generating module 311, configured to generate a hash table with a sample number as a key value according to the sample off-machine information table;
An obtaining module 312, configured to obtain first sample information based on the hash table; wherein the first sample information includes: the sample sequencing data, sample sequencing data path, and sequencing type corresponding to each sample.
Further, in one possible implementation manner of the present embodiment, as shown in fig. 4, the verification unit 32 includes:
A judging module 321 for judging whether the sample sequencing data path exists;
a determining module 322 for determining that the verification passes when the judging module 321 judges that the sample sequencing data path exists;
and a feedback module 323, configured to determine that the verification fails when the judging module 321 judges that the sample sequencing data path does not exist, and stop the verification and return to the verification failure cause.
Further, in one possible implementation manner of this embodiment, as shown in fig. 4, the analysis unit 33 includes:
The selection module 331 is configured to select a corresponding preset raw message analysis procedure according to the sequencing type of each sample;
The analysis module 332 is configured to analyze sample sequencing data of each sample according to the selected preset raw message analysis procedure;
the detection module 333 is configured to perform quality detection on an analysis result of the sample sequencing data based on a preset quality detection algorithm, and generate a quality detection result.
Further, in a possible implementation manner of this embodiment, the first generating unit 34 is further configured to:
And judging whether the sequencer is qualified or not based on the quality inspection result, and generating a verification report.
Further, in a possible implementation manner of this embodiment, as shown in fig. 4, the apparatus further includes:
The second generating unit 36 is configured to analyze the data amount, the splitting rate, and the sequencing error rate of each flow channel in each chip based on the on-chip data path after the processing unit 31 processes the on-chip information table to obtain the first sample information, and generate a chip quality report.
The foregoing explanation of the method embodiment is also applicable to the apparatus of this embodiment, and the principle is the same, and this embodiment is not limited thereto.
According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.
Fig. 5 shows a schematic block diagram of an example electronic device 400 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 5, the apparatus 400 includes a computing unit 401 that can perform various appropriate actions and processes according to a computer program stored in a ROM (Read-Only Memory) 402 or a computer program loaded from a storage unit 408 into a RAM (Random Access Memory ) 403. In RAM 403, various programs and data required for the operation of device 400 may also be stored. The computing unit 401, ROM 402, and RAM 403 are connected to each other by a bus 404. An I/O (Input/Output) interface 405 is also connected to bus 404.
Various components in device 400 are connected to I/O interface 405, including: an input unit 406 such as a keyboard, a mouse, etc.; an output unit 407 such as various types of displays, speakers, and the like; a storage unit 408, such as a magnetic disk, optical disk, etc.; and a communication unit 409 such as a network card, modem, wireless communication transceiver, etc. The communication unit 409 allows the device 400 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The computing unit 401 may be a variety of general purpose and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 401 include, but are not limited to, a CPU (Central Process ing Unit ), a GPU (Graphic Processing Units, graphics processing unit), various specialized AI (ART IFICIAL INTELL IGENCE ) computing chips, various computing units running machine learning model algorithms, a DSP (DIGITAL SIGNAL Processor ), and any suitable Processor, controller, microcontroller, etc. The computing unit 401 performs the respective methods and processes described above, for example, a method of verification analysis. For example, in some embodiments, the method of validation analysis may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 400 via the ROM 402 and/or the communication unit 409. When the computer program is loaded into RAM 403 and executed by computing unit 401, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform the method of verification analysis described previously by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above can be implemented in digital electronic circuitry, integrated Circuit System, FPGA (Field Programmable GATE ARRAY ), ASIC (application-specific integrated Circuit), ASSP (application-specific standard Product), SOC (System On Chip), CPLD (Complex Programmable Logic Device ), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, RAM, ROM, EPROM (ELECTRICALLY PROGRAMMABLE READ-Only-Memory, erasable programmable read-Only Memory) or flash Memory, an optical fiber, a CD-ROM (Compact Di sc Read-Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., CRT (Cathode-Ray Tube) or LCD (LiquidCrystal Display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: LAN (Local Area Network ), WAN (Wide Area Network, wide area network), internet and blockchain networks.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service ("Virtual PRIVATE SERVER" or simply "VPS") are overcome. The server may also be a server of a distributed system or a server that incorporates a blockchain.
It should be noted that, artificial intelligence is a subject of studying a certain thought process and intelligent behavior (such as learning, reasoning, thinking, planning, etc.) of a computer to simulate a person, and has a technology at both hardware and software level. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing, and the like; the artificial intelligence software technology mainly comprises a computer vision technology, a voice recognition technology, a natural language processing technology, a machine learning/deep learning technology, a big data processing technology, a knowledge graph technology and the like.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.
The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (11)
1.A method of validating an analysis, comprising:
processing the sample on-machine information table according to the recorded sample on-machine information table to obtain first sample information;
Verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification;
analyzing the second sample information to obtain a quality inspection result of each sample;
And generating a verification result of the sequencer based on the quality inspection result.
2. The method of claim 1, wherein prior to processing the sample offboard information table according to the entered sample offboard information table to obtain the first sample information, the method further comprises:
Constructing a standard sample off-machine information table according to different sequencing types; wherein, the standard sample machine-off information table includes: sample number, sample name, sequencing platform, chip number, flow cell number, barcode number, sequencing strategy, analysis type, library building mode, species information, standard, capture probe, off-chip data path.
3. The method of claim 1, wherein processing the sample offboard information table according to the entered sample offboard information table to obtain first sample information comprises:
Generating a hash table taking the sample number as a key value according to the sample off-machine information table;
Acquiring first sample information based on the hash table; wherein the first sample information includes: the sample sequencing data, sample sequencing data path, and sequencing type corresponding to each sample.
4. The method of claim 3, wherein said verifying said first sample information to obtain second sample information comprises:
determining whether the sample sequencing data path is present;
If so, determining that the verification passes;
If the verification is not successful, the verification is stopped, and the verification failure reason is returned.
5. The method of claim 4, wherein analyzing the second sample information to obtain quality inspection results for each sample comprises:
Respectively selecting corresponding preset letter analysis flows according to the sequencing types of each sample;
Analyzing sample sequencing data of each sample according to the selected preset raw message analysis flow;
And carrying out quality detection on the analysis result of the sample sequencing data based on a preset quality detection algorithm, and generating a quality detection result.
6. The method of claim 5, wherein generating a verification result for a sequencer based on the quality inspection result comprises:
And judging whether the sequencer is qualified or not based on the quality inspection result, and generating a verification report.
7. The method of claim 2, wherein after processing the sample offboard information table according to the entered sample offboard information table to obtain the first sample information, the method further comprises:
And analyzing the data quantity, the resolution ratio and the sequencing error rate of each flow channel in each chip based on the off-chip data path, and generating a chip quality report.
8. An apparatus for verification analysis, comprising:
The processing unit is used for processing the sample on-off information table according to the recorded sample on-off information table to obtain first sample information;
the verification unit is used for verifying the first sample information to obtain second sample information; wherein the second sample information is the first sample information that passes verification;
the analysis unit is used for analyzing the second sample information to obtain a quality inspection result of each sample;
the first generation unit is used for generating a verification result of the sequencer based on the quality inspection result.
9. An electronic device, comprising:
at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.
10. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-7.
11. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 1-7.
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