CN118245512A - Prefetch control method and device, electronic equipment and readable storage medium - Google Patents
Prefetch control method and device, electronic equipment and readable storage medium Download PDFInfo
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Abstract
The embodiment of the invention provides a prefetch control method, a prefetch control device, electronic equipment and a readable storage medium, and relates to the technical field of computers, wherein the prefetch control method comprises the following steps: dividing an address space of a target cache into at least two cache areas; dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period; under the condition that a target prefetcher corresponding to the target cache meets a throttling condition, determining the allowable prefetching quantity in the cache region according to the cache miss heat and the first prefetching accuracy; and in the next period, controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity. The embodiment of the invention can reduce the flow overhead caused by prefetching while ensuring the performance of the prefetcher, and improve the overall performance of a processor system.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a prefetch control method, a prefetch control device, an electronic device, and a readable storage medium.
Background
In modern processors, a hardware prefetcher (HARDWARE PREFETCHER) fetches data into cache in advance by predicting the locations of such data that will likely be accessed in the future, thereby reducing the data access latency when an actual memory access occurs. The prefetch request produced by the hardware prefetcher is not different from the access request produced by the access instruction in terms of the implemented flow and the used resources, but the prefetch has the problems of occupying access resources, polluting a cache, increasing the bandwidth of a memory bus and the like.
Disclosure of Invention
The embodiment of the invention provides a prefetching control method, a prefetching control device, electronic equipment and a readable storage medium, which can ensure the performance of a prefetcher, reduce the flow overhead caused by prefetching and improve the overall performance of a processor system.
In order to solve the above problems, an embodiment of the present invention discloses a prefetch control method, which includes:
Dividing an address space of a target cache into at least two cache areas;
dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period;
under the condition that a target prefetcher corresponding to the target cache meets a throttling condition, determining the allowable prefetching quantity of the cache region according to the cache miss heat and the first prefetching accuracy;
and in the next period, controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity.
Optionally, before the sending of the prefetch request corresponding to the cache area is controlled according to the allowed prefetch quantity in the next period, the method further includes:
Recording cache miss heat, first prefetch accuracy and allowed prefetch number of the cache region in a cache region heat table;
And in the next period, controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity, including:
under the condition that a prefetch request sent by the target prefetcher is monitored, inquiring the cache region heat table according to a prefetch address carried by the prefetch request;
If a first cache area matched with the prefetching address exists in the cache area heat table, reading the allowable prefetching quantity and the first prefetching accuracy of the first cache area;
And sending the prefetch request to a prefetch queue and subtracting n from the value of the allowed prefetch number of the first cache region in the cache region heat table, wherein n is greater than 0, when the allowed prefetch number is greater than 0 and the first prefetch accuracy is greater than or equal to a first threshold.
Optionally, the method further comprises:
Intercepting the prefetch request if a first condition is satisfied;
Wherein the first condition includes at least one of:
The cache region heat table does not have a first cache region matched with the prefetch address;
The allowable prefetching number of the first cache region is equal to 0;
the first prefetch accuracy of the first cache region is less than the first threshold.
Optionally, the dividing the address space of the target cache into at least two cache areas includes:
Grouping the cache addresses in the target cache by taking the address high bits of the cache addresses as labels to obtain at least two cache areas; the labels of the cache addresses contained in the same cache area are the same.
Optionally, the dynamically monitoring the cache miss heat and the first prefetch accuracy of each cache region in a preset period includes:
In a prefetching period, monitoring the cache miss times, the first prefetching sending times and the first prefetching hit times corresponding to each cache region;
Determining cache miss heats of the cache region according to the cache miss times;
And calculating the first prefetch accuracy in the cache area according to the first prefetch sending times and the first prefetch hit times.
Optionally, the method further comprises:
acquiring the request proportion from the target prefetcher in a memory access request sent by a first cache to a memory in the preset period; the first cache is the cache closest to the memory in the processor system;
Monitoring second prefetch sending times and second prefetch hit times of the target prefetcher in the preset period;
determining a second prefetch accuracy of the target prefetcher according to the second prefetch issue times and the second prefetch hit times;
Calculating the prefetching flow of the target prefetcher according to the request proportion and the second prefetching accuracy; the prefetching flow is used for indicating the extra memory bus bandwidth flow caused by the error prefetching sent by the target prefetcher;
and determining that the prefetcher meets a throttling condition under the condition that the prefetching flow is larger than a second threshold value.
In another aspect, an embodiment of the present invention discloses a prefetch control apparatus, including:
The dividing module is used for dividing the address space of the target cache into at least two cache areas;
the first monitoring module is used for dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period;
the first determining module is used for determining the allowable prefetching quantity of the cache area according to the cache miss heat and the first prefetching accuracy under the condition that the target prefetcher corresponding to the target cache meets a throttling condition;
And the control module is used for controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity in the next period.
Optionally, the apparatus further comprises:
The recording module is used for recording cache miss heat, first prefetch accuracy and the number of prefetches allowed in the cache region in a cache region heat table;
The control module comprises:
The inquiring submodule is used for inquiring the cache region heat table according to the prefetch address carried by the prefetch request under the condition that the prefetch request sent by the target prefetcher is monitored;
the reading submodule is used for reading the allowable prefetching quantity and the first prefetching accuracy of the first cache region if the first cache region matched with the prefetching address exists in the cache region heat table;
And the sending submodule is used for sending the prefetch request to a prefetch queue and subtracting n from the value of the allowed prefetch number of the first cache area in the cache area heat meter when the allowed prefetch number is larger than 0 and the first prefetch accuracy is larger than or equal to a first threshold value, wherein n is larger than 0.
Optionally, the control module further comprises:
The interception sub-module is used for intercepting the prefetch request under the condition that the first condition is met;
Wherein the first condition includes at least one of:
The cache region heat table does not have a first cache region matched with the prefetch address;
The allowable prefetching number of the first cache region is equal to 0;
the first prefetch accuracy of the first cache region is less than the first threshold.
Optionally, the segmentation module includes:
the segmentation submodule is used for grouping the cache addresses in the target cache by taking the address high bits of the cache addresses as labels to obtain at least two cache areas; the labels of the cache addresses contained in the same cache area are the same.
Optionally, the first monitoring module includes:
the monitoring submodule is used for monitoring the cache miss times, the first prefetch sending times and the first prefetch hit times corresponding to each cache region in the prefetch period;
A cache miss heat determination submodule, configured to determine a cache miss heat of the cache region according to the cache miss times;
And the prefetch accuracy computing sub-module is used for computing the first prefetch accuracy in the cache area according to the first prefetch sending times and the first prefetch hit times.
Optionally, the apparatus further comprises:
The acquisition module is used for acquiring the request proportion from the target prefetcher in the memory access request sent by the first cache to the memory in the preset period; the first cache is the cache closest to the memory in the processor system;
the second monitoring module is used for monitoring second prefetch sending times and second prefetch hit times of the target prefetcher in the preset period;
The second determining module is used for determining a second prefetch accuracy of the target prefetcher according to the second prefetch sending times and the second prefetch hit times;
The flow calculation module is used for calculating the prefetching flow of the target prefetcher according to the request proportion and the second prefetching accuracy; the prefetching flow is used for indicating the extra memory bus bandwidth flow caused by the error prefetching sent by the target prefetcher;
And the throttling judgment module is used for determining that the prefetcher meets a throttling condition under the condition that the prefetching flow is larger than a second threshold value.
In still another aspect, the embodiment of the invention also discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions which enable the processor to execute the prefetching control method.
The embodiment of the invention also discloses a readable storage medium, which enables the electronic equipment to execute the prefetching control method when the instructions in the readable storage medium are executed by the processor of the electronic equipment.
The embodiment of the invention has the following advantages:
The embodiment of the invention provides a prefetch control method, which divides the address space of a target cache, periodically monitors the cache miss heat and the first prefetch accuracy in each cache region, determines how many prefetch requests are sent to the cache region in the next period based on the cache miss heat and the first prefetch accuracy of the cache region under the condition that a target prefetcher meets a throttling condition, realizes the independent control of the prefetch quantity of each cache region, throttles a certain cache region, does not influence the normal prefetch flow of other cache regions in the target cache, avoids the blindness of global throttling of the target cache, and improves the prefetch control precision. In addition, the embodiment of the invention triggers the throttling control only when the target prefetcher meets the throttling condition, can ensure that the prefetch request generated by the target prefetcher is kept as far as possible when the target prefetcher has no flow problem, reduces the flow overhead caused by prefetching while ensuring the prefetching performance of the target prefetcher, and is beneficial to improving the overall performance of a processor system.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of an embodiment of a prefetch control method of the present invention;
FIG. 2 is a schematic diagram of the architecture of a processor system of the present invention;
FIG. 3 is a block diagram illustrating an embodiment of a prefetch control apparatus according to the present invention;
Fig. 4 is a block diagram of an electronic device according to an example of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
Method embodiment
Referring to fig. 1, a flowchart illustrating steps of an embodiment of a prefetch control method according to the present invention may include the steps of:
step 101, dividing an address space of a target cache into at least two cache areas;
Step 102, dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period;
step 103, determining the allowable prefetching quantity of the cache region according to the cache miss heat and the first prefetching accuracy under the condition that a target prefetcher corresponding to the target cache meets a throttling condition;
and 104, controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity in the next period.
The prefetching control method provided by the embodiment of the invention can perform throttling control on the hardware prefetcher (namely the target prefetcher in the invention). The prefetch control method provided by the embodiment of the invention can be applied to a prefetch control device, wherein the prefetch control device and a target prefetcher are deployed on the same layer of cache, can monitor cache miss events and cache hit events occurring in the layer of cache, and receive prefetch requests generated by the target prefetcher to determine whether to transmit the prefetch requests to subsequent access components, such as a prefetch queue. The target prefetcher is used for generating a prefetch request according to access information of the target cache. The prefetch control device can prevent the access to the cache of the next layer triggered by any prefetch request according to the throttle strategy, thereby achieving the purpose of throttle prefetch.
Referring to fig. 2, a schematic architecture diagram of a processor system according to an embodiment of the present invention is shown. As shown in FIG. 2, the processor system includes a processor core, a cache, a memory, a target prefetcher, a miss status handling register (Miss Status Holding Register, MSHR), a prefetch queue, and prefetch control. The high-speed buffer comprises a plurality of levels of high-speed buffer, wherein the high-speed buffer comprises a target buffer, the target buffer is any one level of high-speed buffer in the plurality of levels of high-speed buffer, and when the target buffer is the high-speed buffer closest to the processor, the target buffer is respectively connected with the processor core and the next level of high-speed buffer; when the target cache is the cache closest to the memory end, the target cache is respectively connected with the upper-level cache and the memory. The MSHR is used for recording the incomplete access requests in the cache, and can combine a plurality of requests of the same cache line to prevent repeated transmission. The prefetch queue is used for temporarily storing prefetch requests and sending the prefetch requests to the MSHR so as to trigger the target cache to prefetch data from the next-level cache or memory.
There is a great difference in the effectiveness and number distribution of prefetching in different address areas, which results from the spatial locality characteristics that the application behavior and the prefetch algorithm design itself have, i.e., the application tends to centrally access and use data, as are often included in prefetch strategies designed according to the application characteristics. The embodiment of the invention divides the address space of the target cache into at least two cache areas based on the area difference of the prefetching, and performs independent prefetching throttling control on each cache area.
Specifically, the embodiment of the invention dynamically monitors the cache miss heat and the first prefetch accuracy of each cache region in a preset period. The cache miss heat is used to indicate the frequency of occurrence of cache miss in the cache region, and may be determined according to the number of cache miss times occurring in the cache region in a preset period. For example, the number of cache misses occurring in the cache region in the preset period may be directly used as a value of the cache miss heat of the cache region, or the cache miss heat may be calculated according to a ratio of the number of accesses received by the cache region in the preset period to the number of cache misses, or the like. The cache miss heat may be used to estimate the space in which the potential prefetches of the cache region may function, and if the cache miss heat of the cache region is low within a predetermined period, the number of prefetches of the cache region may be limited to a relatively low range; otherwise, if the cache miss heat of the cache region in the preset period is higher, the prefetch requirement of the cache region is higher, and multiple prefetches are needed to meet the data requirement of the received access request. The first prefetch accuracy is used for indicating the ratio of the effective prefetching of the cache area in the preset period to all the prefetches sent out, and can be determined according to the prefetch hit number and prefetch sending number of the cache area in the preset period. Wherein, the prefetch hit refers to that the prefetched data block is accessed later, and the prefetch issue number refers to the number of prefetch requests issued by the target prefetcher for the cache region. The first prefetch accuracy can be used for estimating the prefetch quality of the target prefetcher for the cache region, if the first prefetch accuracy of the cache region in a preset period is lower, the prefetch quality of the target prefetcher for the cache region is lower, and the issuing of prefetch requests of the cache region can be reduced, so that the expenditure caused by error prefetching is reduced, and the prefetch performance of the target prefetcher is improved; if the first prefetching accuracy of the cache region in the preset period is higher, the prefetching quality of the target prefetcher for the cache region is higher, and the prefetching request of the cache region can be normally sent out.
It should be noted that, in the embodiment of the present invention, the preset period may be a preset time period, and the time span corresponding to each period is the same; the cycle length of the preset cycle may also be defined according to the event, and the number of times of occurrence of a specific event in each cycle is the same, for example, 128 cache misses of the target cache may be set to be one cycle, and so on.
If the target prefetcher meets the throttling condition, the allowable prefetching quantity of each cache region can be determined according to the cache miss heat and the first prefetching accuracy of each cache region, and then the sending of the prefetching request of each cache region is independently controlled according to the allowable prefetching quantity.
Wherein the throttle condition is used to determine whether a target prefetcher needs to be throttled. By way of example, the number of prefetch requests and the number of prefetch hits sent by the target prefetcher may be monitored, so as to determine the prefetch accuracy of the target prefetcher, and if the prefetch accuracy of the target prefetcher is less than a certain threshold, for example, the prefetch accuracy is less than 20%, the target prefetcher may be considered to satisfy the throttling condition, and the number of false prefetches may be reduced by performing throttling control on the target prefetcher, so as to reduce pollution and access overhead of the target cache caused by the false prefetching triggered by the target prefetcher, thereby improving the prefetch performance of the target prefetcher. In another embodiment, the ratio of the prefetch request sent by the target prefetcher in the access request causing the cache miss in the cache closest to the memory end may be monitored, the memory bus bandwidth flow generated by the target prefetcher is estimated according to the ratio, and if the memory bus bandwidth flow generated by the target prefetcher is greater than a certain threshold, for example greater than 50%, the target prefetcher may be considered to meet the throttling condition, and the memory bus bandwidth flow generated by the target prefetcher may be reduced by performing throttling control on the target prefetcher, so as to improve the overall performance of the processor system.
The number of allowed prefetches for a cache region may be calculated based on the cache miss heat and the first prefetch accuracy for the cache region. As an example, the prefetch count=a×cache miss heat×first prefetch accuracy is allowed, where a is a preset coefficient, and the value of a may be set according to actual requirements.
After determining the allowed prefetch number of each cache area, in the next period, the sending of the prefetch request corresponding to each cache area can be controlled according to the allowed prefetch number. In the next period, the number of prefetch requests corresponding to each cache area is smaller than or equal to the allowed prefetch number of the cache area.
Taking the processor system shown in fig. 2 as an example, after the target cache receives an access request (including a prefetch request of a previous level cache), the target cache feeds back a cache hit condition to the target prefetcher, and the target prefetcher predicts data which may be accessed in the future according to the cache hit condition of the target cache and generates a prefetch request so as to prefetch the data into the target cache in advance. The target cache prefetches data from the next level of cache or memory according to the prefetch request and backfills the next level of cache. The MSHR merges the requests of the same cache line in the target cache, and avoids repeatedly sending the same request to the next-level cache or the memory. The target cache feeds back the hit condition (namely prefetch hit) and cache hit condition of the prefetched data in the subsequent access to the prefetch control device, the prefetch control device determines the first prefetch accuracy of each cache region in the target cache according to the prefetch hit condition of the target cache, and determines the cache miss heat of the target cache according to the cache hit condition of the target cache.
In the processor system shown in fig. 2, the prefetch control module monitors prefetch requests issued by the target prefetcher. Under the condition that the target prefetcher meets the throttling condition, the prefetching control module can determine a cache area corresponding to each prefetching request according to a prefetching address carried in each prefetching request sent by the target prefetcher, if the allowable prefetching number of the cache area corresponding to the prefetching request is not 0, the transmission of the prefetching request can not be interfered, the prefetching request can be normally sent to a prefetching queue, and the prefetching queue waits to be sent to the MSHR to carry out a subsequent prefetching process. And, the prefetch control module may reduce the allowed prefetch number of a certain cache area by 1 after the prefetch request corresponding to the cache area is normally issued. If the allowed prefetch number of the cache area corresponding to the prefetch request is equal to 0, the prefetch request is intercepted, and the prefetch request intercepted by the prefetch control module is not sent to the prefetch queue any more, and the subsequent prefetch flow is not triggered any more.
According to the prefetching control method provided by the embodiment of the invention, the address space of the target cache is divided, the cache miss heat and the first prefetching accuracy in each cache region are periodically monitored, and under the condition that the target prefetcher meets the throttling condition, the prefetching request is determined to be sent to the cache region in the next period based on the cache miss heat and the first prefetching accuracy of the cache region, so that the independent control of the prefetching quantity of each cache region is realized, the throttling of a certain cache region is realized, the normal prefetching flow of other cache regions in the target cache is not influenced, the blindness of global throttling of the target cache is avoided, and the prefetching control precision is improved. In addition, the embodiment of the invention triggers the throttling control only when the target prefetcher meets the throttling condition, can ensure that the prefetch request generated by the target prefetcher is kept as far as possible when the target prefetcher has no flow problem, reduces the flow overhead caused by prefetching while ensuring the prefetching performance of the target prefetcher, and is beneficial to improving the overall performance of a processor system.
It should be noted that many active prefetch throttling techniques in the related art control the Aggressiveness (AGGRESSIVENESS) and the prefetch distance of prefetchers based on the metrics of the prefetch accuracy, the coverage, the last level cache (LAST LEVEL CACHE, LLC) pollution, and the dynamic random access memory (Dynamic Random Access Memory, DRAM) bandwidth, and a scheme for controlling the aggressiveness and the prefetch distance needs to be proposed specifically for each prefetcher, which is generally shown as specifically adjusting the threshold. These throttling techniques have mainly the following problems:
(1) Throttling aggressively may result in too many valid prefetches being blocked, resulting in performance degradation of the prefetcher.
(2) The conservation of throttling may result in invalid prefetches being issued further, which may not be effective in alleviating cache pollution and other problems.
Before throttling a target prefetcher, the prefetching control method provided by the embodiment of the invention judges whether the target prefetcher meets the throttling condition, if so, a throttling mechanism is triggered, and the sending of prefetch requests is controlled according to the allowed prefetching quantity of each cache area in a target cache; if the target prefetcher does not meet the throttle condition, the prefetching is triggered directly according to the prefetch request. Compared with the active throttling technology in the related art, the embodiment of the invention can keep the prefetch request as much as possible when the target prefetcher has no flow problem, avoid excessive effective prefetching from being blocked caused by aggressive throttling, and ensure the prefetching performance of the target prefetcher. In addition, the embodiment of the invention divides the target cache into areas, calculates the allowed prefetching quantity through the cache miss heat and the prefetching accuracy of the cache area, and does not directly disable or start the prefetching of the area, thereby avoiding blindness of global throttling and improving the precision of throttling control.
In addition, the embodiment of the invention can judge whether the cache area needs to solve the storage problem by prefetching based on the cache miss heat of the cache area, and can avoid prefetching the invalid target; the first prefetch accuracy based on the cache region may evaluate whether the prefetch is effective to address the storage problem of the cache region. By combining the two information to determine the allowed prefetching quantity of the cache area, the issuing of invalid prefetching can be reduced, the pollution of the error prefetching to the cache is relieved, and the memory access overhead is reduced, so that the overall performance of the processor system is improved.
Optionally, in step 101, dividing the address space of the target cache into at least two cache areas includes: grouping the cache addresses in the target cache by taking the address high bits of the cache addresses as labels to obtain at least two cache areas; the labels of the cache addresses contained in the same cache area are the same.
In the embodiment of the invention, the cache addresses can be grouped according to the address high-order bits of the cache addresses in the target cache, so that the address space of the target cache is directly divided into at least two cache areas. Illustratively, the cache address may be grouped as a tag with the upper address bits, e.g., the upper 18 bits, of the cache address.
It can be understood that the number of bits corresponding to the tag can be set according to actual requirements, so that the size of the cache area to be segmented can be adjusted by adjusting the number of bits of the tag.
Optionally, the dynamically monitoring the cache miss heat and the first prefetch accuracy of each cache region in the preset period in step 102 includes:
Step S11, monitoring the cache miss times, the first prefetch sending times and the first prefetch hit times corresponding to each cache region in a prefetch period;
step S12, determining cache miss heat of the cache region according to the cache miss times;
Step S13, calculating a first prefetch accuracy in the cache area according to the first prefetch sending times and the first prefetch hit times.
In the embodiment of the invention, the cache miss frequency generated in the cache region in the preset period can be directly used as the value of the cache miss heat of the cache region, or the cache miss heat can be calculated according to the ratio of the access frequency received by the cache region in the preset period to the cache miss frequency, and the like.
The first prefetch hit number refers to the number of times that the prefetched data block in the cache area is accessed subsequently. The first prefetch issue number refers to the number of prefetch requests issued by the target prefetcher for the cache region. The first prefetch accuracy of the cache region may be determined according to the first prefetch issue number and the first prefetch hit number of the cache region, where the first prefetch accuracy=the first prefetch hit number/the first prefetch issue number.
In an optional embodiment of the present invention, before controlling, in step 103, sending of the prefetch request corresponding to the cache area according to the allowed prefetch count in the next prefetch cycle, the method further includes:
step S21, recording cache miss heat, first prefetching accuracy and allowable prefetching quantity of a cache region in a cache region heat table;
Step 103, in the next prefetch period, sending a prefetch request corresponding to the cache area according to the allowed prefetch number, including:
step S22, under the condition that a prefetch request sent by the target prefetcher is monitored, inquiring the cache region heat table according to a prefetch address carried by the prefetch request;
Step S23, if a first cache area matched with the prefetching address exists in the cache area heat table, reading the allowable prefetching quantity and the first prefetching accuracy of the first cache area;
Step S24, when the number of allowed prefetches is greater than 0 and the first prefetch accuracy is greater than or equal to a first threshold, the prefetch request is sent to a prefetch queue, and the value of the number of allowed prefetches of the first cache region in the cache region hotlist is subtracted by n, where n is greater than 0.
In the embodiment of the invention, the cache miss heat (or the cache miss times), the first prefetch hit times, the first prefetch issue times and the allowed prefetch number of each cache region can be recorded through a cache region heat table. Referring to table 1, a cache area heat meter provided in an embodiment of the present invention is shown.
In table 1, the number of allowed prefetches=a×the number of cache misses× (first prefetch hit number/first prefetch issue number), a=2.
In the embodiment of the invention, if the prefetch request sent by the target prefetcher is monitored and the target prefetcher meets the throttling condition, the cache region hotlist can be queried according to the prefetch address carried by the prefetch request. If there is a first cache region Ri matching the prefetch address in the cache region hotlist, the allowable prefetch number and the first prefetch accuracy of the first cache region Ri can be read from the cache region hotlist to determine whether to issue the prefetch request. If the current allowed prefetch number of the first cache area Ri is greater than 0 and the first prefetch accuracy is greater than or equal to the first threshold, the prefetch request can be normally sent to the prefetch queue to trigger a subsequent prefetch flow. Then, the value of the allowable prefetch number of the first cache region Ri in the cache region hotlist is subtracted by n, n being greater than 0. Wherein, the value of n can be determined according to the initial value of the allowed prefetching quantity. For example, when the calculated allowable prefetch number=a×cache miss heat×first prefetch accuracy, and the value of the coefficient a is greater, n may be an integer greater than 1, for example, 2, 3, so as to correct the coefficient a, so as to avoid that when the value of a is greater, the number of prefetch requests actually issued is greater, which results in the effect that throttling is not achieved. In the case where the value of the coefficient a is small, n may be equal to 1.
The first threshold may be set according to actual requirements, for example, the first threshold may be 20%.
Optionally, the method further comprises: the prefetch request is intercepted if a first condition is satisfied.
Wherein the first condition includes at least one of:
a1, a first cache area matched with the prefetching address does not exist in the cache area heat table;
a2, the allowed prefetching quantity of the first cache area is equal to 0;
A3, the first prefetching accuracy of the first cache region is smaller than the first threshold.
It should be noted that if the prefetch address of the prefetch request belongs to the address space of a certain cache area, the prefetch request may be considered to match the cache area. For example, the address high order bits of the prefetch address may be compared to the tag of the cache region, and if the address high order bits of the prefetch address are the same as the tag of the cache region, the prefetch request may be considered to match the cache region.
In the embodiment of the invention, if the first cache area matched with the prefetch address carried in the prefetch request does not exist in the cache area heat table, the prefetch request can be intercepted. Or if the first cache area matched with the prefetch address carried in the prefetch request exists in the cache area heat table, but the current allowed prefetch number of the first cache area is 0, or the first prefetch accuracy is smaller than a first threshold value, intercepting the prefetch request.
Illustratively, in the processor system shown in fig. 2, the prefetch control module monitors the prefetch request issued by the target prefetcher, and if it is determined that interception is required, the prefetch request is not sent to the prefetch queue, and the subsequent prefetch flow is not triggered.
The embodiment of the invention judges whether to send out the prefetch request according to the allowed prefetch quantity and the first prefetch accuracy rate of the cache area, and can reduce the prefetch flow and the number of times of wrong prefetch, thereby reducing access expenditure caused by wrong prefetch and improving the prefetch performance of the target prefetcher.
Optionally, the method further comprises:
Step S31, obtaining the request proportion from the target prefetcher in a memory access request sent by a first cache to a memory in the preset period; the first cache is the cache closest to the memory in the processor system;
step S32, monitoring the second prefetch sending times and the second prefetch hit times of the target prefetcher in the preset period;
step S33, determining a second prefetch accuracy of the target prefetcher according to the second prefetch issue times and the second prefetch hit times;
Step S34, calculating the prefetching flow of the target prefetcher according to the request proportion and the second prefetching accuracy; the prefetching flow is used for indicating the extra memory bus bandwidth flow caused by the error prefetching sent by the target prefetcher;
and step S35, determining that the prefetcher meets a throttling condition under the condition that the prefetching flow is larger than a second threshold value.
In the embodiment of the invention, the second prefetch sending times and the second prefetch hit times of the target prefetcher in the preset period can be monitored, and the second prefetch accuracy rate can be calculated. Where the second prefetch issue number refers to the number of prefetch requests that the target prefetcher sends to a subsequent access means (e.g., prefetch queue). The second prefetch hit number refers to the number of times that data prefetched into the target cache by a prefetch request issued by the target prefetcher is accessed in a subsequent access. Second prefetch accuracy = second prefetch hit/second prefetch issue.
The first cache refers to the cache closest to the memory in the processor system. And counting the ratio of the prefetch requests sent by the first cache to the memory, wherein the ratio is the ratio of the requests from the target prefetcher in the access requests sent by the first cache to the memory. Then, based on the request proportion and the second prefetch accuracy of the target prefetcher, the additional memory bus bandwidth flow caused by the error prefetch triggered by the target prefetcher is estimated. For example, when the second prefetch accuracy of the target prefetcher is 20% and the proportion of requests from the target prefetcher among the requests causing cache misses of the first cache is 50%, it may be estimated that an erroneous prefetch caused prefetch traffic of about 50% × (1-20%) =40% at this time. It should be noted that the correct prefetch replaces the normal access role and therefore does not cause additional memory bus bandwidth traffic.
According to the prefetching flow of the target prefetcher, whether the target prefetcher needs to be throttled or not can be judged. For example, if the prefetch traffic is greater than the second threshold, it may be determined that the target prefetcher satisfies a throttle condition, at which point throttle control of the target prefetcher may be triggered. The second threshold may be set according to actual control requirements, for example, the second threshold may be 30%.
In summary, the embodiment of the invention provides a prefetch control method, which divides the address space of a target cache, periodically monitors the cache miss heat and the first prefetch accuracy in each cache region, determines how many prefetch requests are sent to the cache region in the next period based on the cache miss heat and the first prefetch accuracy of the cache region under the condition that the target prefetcher meets the throttling condition, realizes the independent control of the prefetch quantity of each cache region, throttles a certain cache region, does not influence the normal prefetch flow of other cache regions in the target cache, avoids the blindness of global throttling of the target cache, and improves the prefetch control accuracy. In addition, the embodiment of the invention triggers the throttling control only when the target prefetcher meets the throttling condition, can ensure that the prefetch request generated by the target prefetcher is kept as far as possible when the target prefetcher has no flow problem, reduces the flow overhead caused by prefetching while ensuring the prefetching performance of the target prefetcher, and is beneficial to improving the overall performance of a processor system.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Device embodiment
Referring to fig. 3, there is shown a block diagram of a prefetch control apparatus of the present invention, which may include:
A dividing module 301, configured to divide an address space of the target cache into at least two cache areas;
A first monitoring module 302, configured to dynamically monitor a cache miss heat and a first prefetch accuracy of each cache region in a preset period;
a first determining module 303, configured to determine, when a target prefetcher corresponding to the target cache meets a throttling condition, an allowable prefetch number of the cache area according to the cache miss heat and the first prefetch accuracy;
and the control module 304 is configured to control, in a next period, sending of the prefetch request corresponding to the cache area according to the allowed prefetch number.
Optionally, the apparatus further comprises:
The recording module is used for recording cache miss heat, first prefetch accuracy and the number of prefetches allowed in the cache region in a cache region heat table;
The control module comprises:
The inquiring submodule is used for inquiring the cache region heat table according to the prefetch address carried by the prefetch request under the condition that the prefetch request sent by the target prefetcher is monitored;
the reading submodule is used for reading the allowable prefetching quantity and the first prefetching accuracy of the first cache region if the first cache region matched with the prefetching address exists in the cache region heat table;
And the sending submodule is used for sending the prefetch request to a prefetch queue and subtracting n from the value of the allowed prefetch number of the first cache area in the cache area heat meter when the allowed prefetch number is larger than 0 and the first prefetch accuracy is larger than or equal to a first threshold value, wherein n is larger than 0.
Optionally, the control module further comprises:
The interception sub-module is used for intercepting the prefetch request under the condition that the first condition is met;
Wherein the first condition includes at least one of:
The cache region heat table does not have a first cache region matched with the prefetch address;
The allowable prefetching number of the first cache region is equal to 0;
the first prefetch accuracy of the first cache region is less than the first threshold.
Optionally, the segmentation module includes:
the segmentation submodule is used for grouping the cache addresses in the target cache by taking the address high bits of the cache addresses as labels to obtain at least two cache areas; the labels of the cache addresses contained in the same cache area are the same.
Optionally, the first monitoring module includes:
the monitoring submodule is used for monitoring the cache miss times, the first prefetch sending times and the first prefetch hit times corresponding to each cache region in the prefetch period;
A cache miss heat determination submodule, configured to determine a cache miss heat of the cache region according to the cache miss times;
And the prefetch accuracy computing sub-module is used for computing the first prefetch accuracy in the cache area according to the first prefetch sending times and the first prefetch hit times.
Optionally, the apparatus further comprises:
The acquisition module is used for acquiring the request proportion from the target prefetcher in the memory access request sent by the first cache to the memory in the preset period; the first cache is the cache closest to the memory in the processor system;
the second monitoring module is used for monitoring second prefetch sending times and second prefetch hit times of the target prefetcher in the preset period;
The second determining module is used for determining a second prefetch accuracy of the target prefetcher according to the second prefetch sending times and the second prefetch hit times;
The flow calculation module is used for calculating the prefetching flow of the target prefetcher according to the request proportion and the second prefetching accuracy; the prefetching flow is used for indicating the extra memory bus bandwidth flow caused by the error prefetching sent by the target prefetcher;
And the throttling judgment module is used for determining that the prefetcher meets a throttling condition under the condition that the prefetching flow is larger than a second threshold value.
In summary, the embodiment of the invention provides a prefetch control device, which divides the address space of a target cache, periodically monitors the cache miss heat and the first prefetch accuracy in each cache region, determines how many prefetch requests are sent to the cache region in the next period based on the cache miss heat and the first prefetch accuracy of the cache region under the condition that the target prefetcher meets the throttling condition, realizes the independent control of the prefetch quantity of each cache region, throttles a certain cache region, does not influence the normal prefetch flow of other cache regions in the target cache, avoids the blindness of global throttling of the target cache, and improves the prefetch control accuracy. In addition, the embodiment of the invention triggers the throttling control only when the target prefetcher meets the throttling condition, can ensure that the prefetch request generated by the target prefetcher is kept as far as possible when the target prefetcher has no flow problem, reduces the flow overhead caused by prefetching while ensuring the prefetching performance of the target prefetcher, and is beneficial to improving the overall performance of a processor system.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The specific manner in which the various modules perform the operations in relation to the processor of the above-described embodiments have been described in detail in relation to the embodiments of the method and will not be described in detail herein.
Referring to fig. 4, a block diagram of an electronic device according to an embodiment of the present invention is shown. As shown in fig. 4, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions, and the executable instructions enable the processor to execute the prefetch control method of the previous embodiment.
The Processor may be a CPU (Central Processing Unit ), general purpose Processor, DSP (DIGITAL SIGNAL Processor ), ASIC (Application SPECIFIC INTEGRATED Circuit), FPGA (Field Programmable GATE ARRAY ) or other editable device, transistor logic device, hardware component, or any combination thereof. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.
The communication bus may include a path to transfer information between the memory and the communication interface. The communication bus may be a PCI (PERIPHERAL COMPONENT INTERCONNECT, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus, or the like. The communication bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 4, but not only one bus or one type of bus.
The Memory may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory ) or other type of dynamic storage device that can store information and instructions, an EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY ), a CD-ROM (Compact Disc Read Only Memory, compact disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, and the like.
Embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when executed by a processor of an electronic device (server or terminal), enables the processor to perform the prefetch control method shown in fig. 1.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems) and computer program products according to embodiments of the invention. It will be understood that each flowchart and/or block of the flowchart illustrations and/or block diagrams, and combinations of flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The foregoing has described in detail the methods, apparatuses, electronic devices and readable storage medium for controlling prefetching, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the above description of the embodiments is only for aiding in understanding the methods and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (14)
1. A prefetch control method, the method comprising:
Dividing an address space of a target cache into at least two cache areas;
dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period;
under the condition that a target prefetcher corresponding to the target cache meets a throttling condition, determining the allowable prefetching quantity of the cache region according to the cache miss heat and the first prefetching accuracy;
and in the next period, controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity.
2. The method of claim 1, wherein the method further comprises, during the next cycle, before controlling the sending of the prefetch request corresponding to the cache region according to the allowed prefetch count:
Recording cache miss heat, first prefetch accuracy and allowed prefetch number of the cache region in a cache region heat table;
And in the next period, controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity, including:
under the condition that a prefetch request sent by the target prefetcher is monitored, inquiring the cache region heat table according to a prefetch address carried by the prefetch request;
If a first cache area matched with the prefetching address exists in the cache area heat table, reading the allowable prefetching quantity and the first prefetching accuracy of the first cache area;
And sending the prefetch request to a prefetch queue and subtracting n from the value of the allowed prefetch number of the first cache region in the cache region heat table, wherein n is greater than 0, when the allowed prefetch number is greater than 0 and the first prefetch accuracy is greater than or equal to a first threshold.
3. The method according to claim 2, wherein the method further comprises:
Intercepting the prefetch request if a first condition is satisfied;
Wherein the first condition includes at least one of:
The cache region heat table does not have a first cache region matched with the prefetch address;
The allowable prefetching number of the first cache region is equal to 0;
the first prefetch accuracy of the first cache region is less than the first threshold.
4. The method of claim 1, wherein dividing the address space of the target cache into at least two cache regions comprises:
Grouping the cache addresses in the target cache by taking the address high bits of the cache addresses as labels to obtain at least two cache areas; the labels of the cache addresses contained in the same cache area are the same.
5. The method of claim 1, wherein dynamically monitoring the cache miss heat and the first prefetch accuracy for each cache region over a predetermined period comprises:
In a prefetching period, monitoring the cache miss times, the first prefetching sending times and the first prefetching hit times corresponding to each cache region;
Determining cache miss heats of the cache region according to the cache miss times;
And calculating the first prefetch accuracy in the cache area according to the first prefetch sending times and the first prefetch hit times.
6. The method according to claim 1, wherein the method further comprises:
acquiring the request proportion from the target prefetcher in a memory access request sent by a first cache to a memory in the preset period; the first cache is the cache closest to the memory in the processor system;
Monitoring second prefetch sending times and second prefetch hit times of the target prefetcher in the preset period;
determining a second prefetch accuracy of the target prefetcher according to the second prefetch issue times and the second prefetch hit times;
Calculating the prefetching flow of the target prefetcher according to the request proportion and the second prefetching accuracy; the prefetching flow is used for indicating the extra memory bus bandwidth flow caused by the error prefetching sent by the target prefetcher;
and determining that the prefetcher meets a throttling condition under the condition that the prefetching flow is larger than a second threshold value.
7. A prefetch control apparatus, the apparatus comprising:
The dividing module is used for dividing the address space of the target cache into at least two cache areas;
the first monitoring module is used for dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period;
the first determining module is used for determining the allowable prefetching quantity of the cache area according to the cache miss heat and the first prefetching accuracy under the condition that the target prefetcher corresponding to the target cache meets a throttling condition;
And the control module is used for controlling the sending of the prefetch request corresponding to the cache area according to the allowed prefetch quantity in the next period.
8. The apparatus of claim 7, wherein the apparatus further comprises:
The recording module is used for recording cache miss heat, first prefetch accuracy and the number of prefetches allowed in the cache region in a cache region heat table;
The control module comprises:
The inquiring submodule is used for inquiring the cache region heat table according to the prefetch address carried by the prefetch request under the condition that the prefetch request sent by the target prefetcher is monitored;
the reading submodule is used for reading the allowable prefetching quantity and the first prefetching accuracy of the first cache region if the first cache region matched with the prefetching address exists in the cache region heat table;
And the sending submodule is used for sending the prefetch request to a prefetch queue and subtracting n from the value of the allowed prefetch number of the first cache area in the cache area heat meter when the allowed prefetch number is larger than 0 and the first prefetch accuracy is larger than or equal to a first threshold value, wherein n is larger than 0.
9. The apparatus of claim 8, wherein the control module further comprises:
The interception sub-module is used for intercepting the prefetch request under the condition that the first condition is met;
Wherein the first condition includes at least one of:
The cache region heat table does not have a first cache region matched with the prefetch address;
The allowable prefetching number of the first cache region is equal to 0;
the first prefetch accuracy of the first cache region is less than the first threshold.
10. The apparatus of claim 7, wherein the segmentation module comprises:
the segmentation submodule is used for grouping the cache addresses in the target cache by taking the address high bits of the cache addresses as labels to obtain at least two cache areas; the labels of the cache addresses contained in the same cache area are the same.
11. The apparatus of claim 7, wherein the first monitoring module comprises:
the monitoring submodule is used for monitoring the cache miss times, the first prefetch sending times and the first prefetch hit times corresponding to each cache region in the prefetch period;
A cache miss heat determination submodule, configured to determine a cache miss heat of the cache region according to the cache miss times;
And the prefetch accuracy computing sub-module is used for computing the first prefetch accuracy in the cache area according to the first prefetch sending times and the first prefetch hit times.
12. The apparatus of claim 7, wherein the apparatus further comprises:
The acquisition module is used for acquiring the request proportion from the target prefetcher in the memory access request sent by the first cache to the memory in the preset period; the first cache is the cache closest to the memory in the processor system;
the second monitoring module is used for monitoring second prefetch sending times and second prefetch hit times of the target prefetcher in the preset period;
The second determining module is used for determining a second prefetch accuracy of the target prefetcher according to the second prefetch sending times and the second prefetch hit times;
The flow calculation module is used for calculating the prefetching flow of the target prefetcher according to the request proportion and the second prefetching accuracy; the prefetching flow is used for indicating the extra memory bus bandwidth flow caused by the error prefetching sent by the target prefetcher;
And the throttling judgment module is used for determining that the prefetcher meets a throttling condition under the condition that the prefetching flow is larger than a second threshold value.
13. An electronic device, comprising a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is configured to store executable instructions that cause the processor to perform the prefetch control method according to any one of claims 1 to 6.
14. A readable storage medium, characterized in that instructions in the readable storage medium, when executed by a processor of an electronic device, enable the processor to perform the prefetch control method according to any one of claims 1 to 6.
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