CN118245287A - High-reliability FPGA (field programmable gate array) for realizing checking rollback based on memristor - Google Patents

Abstract

The application discloses a high-reliability FPGA (field programmable gate array) for realizing check rollback based on memristors, which relates to the technical field of FPGAs, wherein memristors based on variable resistance values are arranged in nonvolatile time sequence elements in the high-reliability FPGA, the memristors are used as functional elements on one hand and are used for storing information on the other hand, an check rollback controller controls each nonvolatile time sequence element to update and store a working state without faults by using the resistance state of each built-in memristor, and the resistance state of each built-in memristor is restored to the latest working state when faults occur, so that the high-reliability FPGA is driven to be restored to the latest fault-free working state, thereby realizing the functions of nonvolatile state preservation and state restoration, improving the reliability and stability.

Description

High-reliability FPGA (field programmable gate array) for realizing checking rollback based on memristor

Technical Field

The application relates to the technical field of FPGA (field programmable gate array), in particular to a high-reliability FPGA for realizing check rollback based on a memristor.

Background

An FPGA (Field Programmable GATE ARRAY ) is a hardware programmable logic device and is widely used in systems in various fields. With the continuous progress of technology, the reliability requirements of various systems in modern society are increasing, especially in fields such as aerospace, medical equipment, energy, traffic, financial systems and the like, which have high requirements on stability. However, for the currently mainstream FPGA based on SRAM, information is lost when the system fails, which affects the reliability and stability of the system.

Disclosure of Invention

Aiming at the problems and the technical requirements, the application provides a high-reliability FPGA for realizing checking rollback based on a memristor, which has the following technical scheme:

The high-reliability FPGA based on memristors realizes checking rollback, the high-reliability FPGA internally comprises at least one nonvolatile time sequence element formed by manufacturing memristors based on variable resistance values, and the high-reliability FPGA internally further comprises a checking rollback controller; in the operation process of the high-reliability FPGA:

When the current running state of the high-reliability FPGA has no fault, the detection rollback controller controls each nonvolatile time sequence element to update and store the current working state of the nonvolatile time sequence element by utilizing the resistance state of the built-in memristor;

When the current running state of the high-reliability FPGA has faults, the detection rollback controller controls each nonvolatile time sequence element to restore to the nearest working state of the nonvolatile time sequence element by utilizing the resistance state of the built-in memristor, and the high-reliability FPGA is driven to restore to the nearest fault-free running state.

In the further technical scheme, in the running process of the high-reliability FPGA, when the current running state of the high-reliability FPGA is determined to be fault-free, the detection rollback controller controls each nonvolatile time sequence element to update and store the current working state of the nonvolatile time sequence element by using the resistance state of the built-in memristor according to a preset checking frequency.

The detection frequency adopted by the rollback controller is dynamically variable in the running process of the high-reliability FPGA, and the detection frequency is related to at least one of the running state, the running environment and the reliability requirement of the high-reliability FPGA.

The further technical scheme is that in the running process of the high-reliability FPGA:

Temporarily increasing the checking frequency in a preset time period after determining that the running state of the high-reliability FPGA fails, and recovering the checking frequency after determining that the duration time of the running state of the high-reliability FPGA without failure reaches the preset time period;

and/or, when the running environment of the high-reliability FPGA is determined to be bad, increasing the checking frequency;

and/or increasing the inspection frequency when the reliability requirement of the high-reliability FPGA is determined to be high.

The further technical scheme is that in the running process of the high-reliability FPGA:

Suspending the user function executed by the high-reliability FPGA, performing fault test on the current running state of the high-reliability FPGA, resuming the execution of the user function after the fault test is completed, and detecting whether the current running state of the high-reliability FPGA has faults or not according to the fault test result by the rollback controller;

And simultaneously carrying out fault test on the current running state of the high-reliability FPGA in parallel while carrying out user functions on the high-reliability FPGA, and determining whether the current running state of the high-reliability FPGA has faults or not by the detection rollback controller according to the fault test result.

The further technical scheme is that the check rollback controller is connected through a control network and controls the resistance state of the memristors arranged in each nonvolatile time sequence element;

When the same control line is shared between each nonvolatile time sequence element and the check rollback controller in the control line network, the check rollback controller simultaneously reads the resistance state of the memristor built in each nonvolatile time sequence element, and the check rollback controller simultaneously configures the resistance state of the memristor built in each nonvolatile time sequence element;

When at least two nonvolatile time sequence elements exist in the control network and control lines between the checking rollback controllers are independent of each other, the control network forms a hierarchical structure, the checking rollback controllers sequentially read the resistance states of memristors built in the nonvolatile time sequence elements according to a hierarchical sequence, and the checking rollback controllers sequentially configure the resistance states of the memristors built in the nonvolatile time sequence elements according to the hierarchical sequence.

The further technical scheme is that the total checking time and the total rollback time of the rollback checking controller are related to the structure of a control network, and the total checking time and the total rollback time are adjustable;

The method comprises the steps of checking total time consumption, namely detecting time consumption for a rollback controller to control all non-volatile time sequence elements to finish updating and storing a current working state;

The total rollback time is the time taken to detect that the rollback controller has controlled all non-volatile sequential elements to complete the recovery to the last operating state.

The further technical scheme is that the checking rollback controller and the control network are realized by utilizing programmable resources built in the high-reliability FPGA; in the design process of the high-reliability FPGA, the circuit structure of the control network formed by using programmable resources is matched with the circuit design requirement.

The circuit design requirement comprises at least one of wiring area of a control network, total time consumption of checking a rollback controller, total time consumption of checking the rollback controller, maximum instantaneous current of the rollback controller for reading the resistance state of the memristor built in each nonvolatile time sequence element, and maximum instantaneous current of the memristor built in each nonvolatile time sequence element configured by the rollback controller.

The technical scheme is that the nonvolatile time sequence elements in the high-reliability FPGA comprise nonvolatile DFF, nonvolatile BRAM and time sequence elements for providing configuration bits, the time sequence elements for providing the configuration bits comprise nonvolatile distributed random access memories and nonvolatile shift registers, and the nonvolatile BRAM, the nonvolatile distributed random access memories and the nonvolatile shift registers are respectively constructed based on the nonvolatile DFF;

For the nonvolatile DFF, the rollback controller is checked to control a data storage signal SET of the nonvolatile DFF to be in an effective level state, and programming voltage PHV is applied to the end part of the memristor so as to control the nonvolatile DFF to store the current working state of the output end of the nonvolatile DFF by utilizing the resistance state of the built-in memristor; the check rollback controller controls the data recovery signal RES of the nonvolatile DFF to be configured in an active level state and the set signal to be in an inactive level state, and the resistance state of the memristor built in the nonvolatile DFF is recovered to the last operation state of the nonvolatile DFF.

The beneficial technical effects of the application are as follows:

The application discloses a high-reliability FPGA (field programmable gate array) for realizing checking rollback based on memristors, which optimally designs a hardware circuit structure and a software workflow, upgrades a time sequence element into a nonvolatile time sequence element formed by manufacturing the memristors based on variable resistance values, and additionally controls each nonvolatile time sequence element by a checking rollback controller in the FPGA, wherein the memristors built in the nonvolatile time sequence element are used as functional elements on one hand, and are used for storing information on the other hand. The working state of each nonvolatile time sequence element is directly stored in the built-in memristor and is stored into the resistance state of the memristor, so that the functions of nonvolatile state preservation and state recovery can be realized, the conventional CMOS process is compatible, the scale and the speed of the FPGA can be improved, the reliability and the operation stability of the high-reliability FPGA are ensured, and the high-reliability FPGA can be well applied in a large-data-volume processing scene.

Drawings

Fig. 1 is a block diagram of a nonvolatile DFF in a high reliability FPGA of the present application.

FIG. 2 is a flow chart of a method performed by a check rollback controller in one embodiment of the application.

Fig. 3 is a circuit configuration of a control line network between a check rollback controller and two nonvolatile DFFs in one example.

Detailed Description

The following describes the embodiments of the present application further with reference to the drawings.

The application discloses a high-reliability FPGA for realizing check rollback based on a memristor, which is provided with a check rollback mechanism, wherein the check rollback mechanism can record a certain specific working state in the operation process of the high-reliability FPGA, and then when a fault occurs in the operation process of the operation, the change or transaction which is done before can be cancelled or rolled back, and the operation can be continued until the working state which is recorded before is recovered, so that the operation can be quickly recovered when the fault occurs, and the high-reliability operation can be realized.

The conventional FPGA is implemented by using a volatile SRAM (Static Random-Access Memory), and the SRAM type FPGA can record a working state in the SRAM, but when the FPGA fails, information stored in the SRAM is lost, so that the SRAM type FPGA cannot actually implement checking rollback, and when the FPGA fails, the FPGA can only recover to an initial working state when the FPGA is just powered on, and then resumes operation, resulting in long recovery time after the SRAM type FPGA fails, and affecting operation stability and reliability.

In the prior art, some FPGAs are realized by adopting a Flash technology, the Flash type FPGA can record the working state in Flash, information stored in Flash cannot be lost when the FPGA fails, so that the Flash type FPGA can be restored to the last stored working state to continue operation, and the Flash type FPGA does not need to be restored to the original working state just when the FPGA is powered on like the SRAM type FPGA, so that the Flash type FPGA can realize checking rollback in theory. However, the FPGA based on the Flash technology is difficult to be compatible with the existing most advanced CMOS technology, which limits the scale and speed of the Flash FPGA, the speed of accessing and reading information in Flash is too slow, the memory space depends on the size of Flash memory, and the storage space is limited, so that the Flash FPGA is difficult to meet the requirement of large data processing capacity, and is also difficult to be suitable for scenes with large scale in general use of the FPGA at present.

It can be seen from the above description that the checking rollback of the two main FPGAs in the prior art cannot be well realized, which is an important reason for influencing the operation reliability, so that the high-reliability FPGA of the present application improves the reliability by optimizing the checking rollback mechanism.

Compared with the traditional FPGA, the high-reliability FPGA disclosed by the application has the advantages that the improvement of the internal circuit structure mainly comprises the following two parts:

(1) The hardware structure of the time sequence element in the traditional FPGA is improved and optimized.

The time sequence element is an element used for storing information in the FPGA, and the running state of the FPGA is determined by the value of the time sequence element in the FPGA, so that the working state of the FPGA can be recorded by storing the value of the time sequence element in the FPGA. The timing elements within the FPGA include DFF (D flip-flop), BRAM (Block RAM), and timing elements providing configuration bits including distributed random access memory (Distributed Random Access Memory, DRAM) and shift registers.

In order to avoid the volatile disadvantage of the SRAM type FPGA and overcome the disadvantage that the Flash type FPGA is difficult to be compatible with the CMOS process, the method is different from the SRAM type FPGA and the Flash type FPGA: and (3) improving and upgrading the circuit structure of at least one time sequence element in the traditional FPGA, and replacing the circuit structure with a corresponding nonvolatile time sequence element formed by manufacturing the memristor based on the variable resistance. In order to completely save the running state of the high-reliability FPGA, in practical application, all time sequence elements in the high-reliability FPGA adopt nonvolatile time sequence elements formed by manufacturing memristors based on variable resistance values, so that the values of all time sequence elements in the high-reliability FPGA can be saved.

Thus, all of the timing elements within the high reliability FPGA are non-volatile timing elements, and the non-volatile timing elements include non-volatile DFFs, non-volatile BRAMs, and non-volatile timing elements that provide configuration bits, including non-volatile distributed random access memories and non-volatile shift registers.

The BRAM is implemented by a combination of registers and latches, etc., and the nonvolatile sequential elements providing configuration bits are also implemented by registers, latches, and RAM-enabled devices, so it can be considered that the nonvolatile BRAM, nonvolatile distributed random access memory, and nonvolatile shift register are respectively built based on nonvolatile DFFs. Therefore, after the nonvolatile DFF is formed based on the memristor with the variable resistance, the nonvolatile BRAM and the nonvolatile time sequence element structure for providing the configuration bit can be further built according to the standard circuit structure based on the nonvolatile DFF.

As shown in fig. 1, the nonvolatile DFF of the present application includes a DATA input port DATA, a DATA output port Q, a clock port CK, a SET signal port SEB, a shaping signal port FOM, a DATA saving signal port SET, a DATA recovery signal port RES, and a variable resistance reset signal port RET. The specific structure and working principle of the nonvolatile DFF may refer to the related content in the nonvolatile DFF for the FPGA based on the variable resistance resistor applied by the applicant in the prior application, and the embodiment will not be described in detail.

(2) And an inspection rollback controller is added in the high-reliability FPGA and is used for controlling the process of inspection rollback.

Based on the improvement of the hardware circuit structure, compared with the traditional FPGA, the high-reliability FPGA improves the working process, and in the running process of the high-reliability FPGA:

When the current running state of the high-reliability FPGA has no faults, the detection rollback controller controls each nonvolatile time sequence element to update and store the current working state without faults of the nonvolatile time sequence element by utilizing the resistance state of the built-in memristor, so that the current running state without faults of the high-reliability FPGA is stored by utilizing the resistance state of the built-in memristor of each nonvolatile time sequence element.

When the current running state of the high-reliability FPGA has faults, the detection rollback controller controls each nonvolatile time sequence element to recover to the latest working state of the nonvolatile time sequence element by utilizing the resistance state of the built-in memristor, so that the high-reliability FPGA can be driven to recover to the stored latest fault-free running state.

In one embodiment, there are two main ways to detect whether there is a fault in the current operating state during the operation of the high reliability FPGA: (1) And suspending the user function executed by the high-reliability FPGA, performing fault test on the current running state of the high-reliability FPGA, resuming the execution of the user function after the fault test is completed, and detecting whether the current running state of the high-reliability FPGA has faults or not according to the fault test result by the rollback controller. (2) And simultaneously carrying out fault test on the current running state of the high-reliability FPGA in parallel while carrying out user functions on the high-reliability FPGA, and determining whether the current running state of the high-reliability FPGA has faults or not by the detection rollback controller according to the fault test result. Regardless of the method employed, fault testing of the current operating state of the high reliability FPGA may be accomplished by detecting the rollback controller or other components or higher level systems within the high reliability FPGA.

That is, in the high-reliability FPGA of the present application, the memristors built in the nonvolatile timing elements are used as functional elements on one hand, and are used for storing information on the other hand. The working state of each nonvolatile time sequence element is directly stored in a built-in memristor, and is stored into the resistance state of the memristor, wherein the resistance state is controlled by the control voltage of the memristor, namely, the configuration information and the working state of the nonvolatile time sequence element can be mutually converted with the control voltage of the built-in memristor, and the functions of state preservation and state recovery are realized. The resistance state of the memristor arranged in the nonvolatile time sequence element is nonvolatile, so that information loss is avoided, the defect of SRAM type FPGA is overcome, in addition, the method can be compatible with the existing CMOS technology, the scale and the speed of the FPGA can be improved, the defect of Flash type FPGA is overcome, the high-reliability FPGA is prevented from losing information after error or emergency fault occurs, the state before the fault can be quickly recovered, and the high reliability and the high stability of the FPGA system are realized. In addition, the rollback detection controller can be internally provided with a register which is used for dynamically maintaining system state information, wherein the system state information indicates the information of the latest fault-free running state stored currently, so that the system state can be clearly stored and restored in the process of updating the storage and restoring the running state.

When the functions are specifically realized, the detection rollback controller stores and restores the working states of the nonvolatile time sequence elements by controlling the control voltage of the memristors built in the nonvolatile time sequence elements. The control process of detecting the control voltage of the rollback controller to the memristor built in the nonvolatile DFF is as follows:

In the checking stage, the checking rollback controller controls the data storage signal SET of the nonvolatile DFF to be in an effective level state, and applies programming voltage PHV at the end part of the memristor to control the nonvolatile DFF to store the current working state of the output end of the nonvolatile DFF by utilizing the resistance state of the built-in memristor, so as to update the current working state of the nonvolatile DFF.

In the rollback phase, the rollback controller is checked to control the data recovery signal RES of the nonvolatile DFF to be configured in an active level state and the set signal to be in an inactive level state, and the resistance state of the memristor built in the nonvolatile DFF is restored to the last operation state of the nonvolatile DFF.

This embodiment will not be described in detail for the control process of the nonvolatile DFF. In addition, because other nonvolatile time sequence elements are all built based on nonvolatile DFFs, the nonvolatile DFFs for building other nonvolatile time sequence elements are controlled by adopting the same method, so that the memristors of the other nonvolatile time sequence elements can be controlled, and the embodiment is not expanded one by one.

On the basis of realizing the functions by using the nonvolatile time sequence element, the operation state of the high-reliability FPGA is recovered to the stored latest fault-free operation state when faults occur, and when the stored latest fault-free operation state is the operation state before a longer time, the operation state needs to be rolled back to the operation state before the longer time to continue operation after the faults occur, so that the recovery time after the faults occurs is influenced, and the reliability is reduced. Therefore, in one embodiment, in the operation process of the high-reliability FPGA, when it is determined that the current operation state of the high-reliability FPGA is fault-free, the detection rollback controller controls each nonvolatile time sequence element to update and store the current operation state of the nonvolatile time sequence element by using the resistance state of the built-in memristor according to a predetermined checking frequency, that is, the fault-free operation state is stored regularly, so that by reasonably configuring the checking frequency, the difference between the rollback operation state after the FPGA has a fault and the operation state when the FPGA has a fault can not be excessive, and the recovery time after the fault can be controlled within a reasonable range.

Increasing the inspection frequency can shorten the recovery time after failure, but increasing the inspection frequency also brings about other problems: when a method of suspending the user function to perform fault test on the current running state of the high-reliability FPGA is adopted, a higher inspection frequency means that the user function needs to be suspended and fault test is performed more frequently, which affects the time-consuming execution of the user function by the high-reliability FPGA and reduces the execution speed and performance of the chip. When the method of performing fault test on the current running state of the high-reliability FPGA in parallel while executing the user function is adopted, the fault test introduces additional power consumption and calculation power requirements, so that a higher inspection frequency also brings greater power consumption burden and calculation burden. Thus, regardless of the failure test method employed, a relatively high inspection frequency can have a corresponding negative impact. Therefore, in determining the inspection frequency, it is necessary to select an appropriate inspection frequency in consideration of the positive influence of the inspection frequency on shortening the recovery time and the negative influence thereof.

Based on this consideration, one approach is to set a suitable inspection frequency based on pre-debugging and experience so that the overall effect is sufficiently ideal. Alternatively, the checking frequency used by the rollback controller is dynamically variable during operation of the high reliability FPGA, please refer to the flowchart shown in fig. 2, and the checking frequency is related to at least one of the operating state, the operating environment, and the reliability requirement of the high reliability FPGA. In one embodiment, temporarily increasing the inspection frequency within a predetermined period of time after determining that the operational state of the high reliability FPGA is faulty, and recovering the inspection frequency after determining that the operational state of the high reliability FPGA is fault-free for a predetermined period of time; and/or, when the running environment of the high-reliability FPGA is determined to be bad, increasing the checking frequency; and/or increasing the inspection frequency when the reliability requirement of the high-reliability FPGA is determined to be high. That is, when the operating state, operating environment and reliability requirements of the high-reliability FPGA indicate an increase in the probability of occurrence of a fault or indicate an increase in the reliability requirements, the inspection frequency is increased to preferentially ensure the operation reliability, otherwise, a lower inspection frequency is maintained to reduce the negative effects caused by the inspection mechanism.

In addition, as described above, whether the storage or recovery of the operation state is performed based on the voltage control of the memristor by the check rollback controller, and thus the check rollback controller needs to be connected through a control line network and control the resistance states of the memristors built in the respective nonvolatile timing elements. When the control network structures are different, the control methods of the check rollback controller on all the various nonvolatile time sequence elements are also different:

When the same control line is shared between each nonvolatile time sequence element and the check rollback controller in the control line network, the check rollback controller simultaneously reads the resistance state of the memristor built in each nonvolatile time sequence element, and the check rollback controller simultaneously configures the resistance state of the memristor built in each nonvolatile time sequence element. For example, in fig. 3, the same control line is shared between the two nonvolatile DFFs and the check rollback controller, that is, the same ports of the two nonvolatile DFFs are connected and connected to the same port of the check rollback controller, the check rollback controller may simultaneously control the data saving signals SET of the two nonvolatile DFFs to be in an active level state, and simultaneously apply the programming voltage PHV to the ends of the memristors of the two nonvolatile DFFs, thereby controlling the two nonvolatile DFFs to simultaneously store the current working state of the output end of the nonvolatile DFF by using the resistance state of the built-in memristors. The check rollback controller may also control the data recovery signals RES of the two nonvolatile DFFs to be configured in an active level state and the set signals to be in an inactive level state at the same time, so as to recover the resistance states of memristors built in the two nonvolatile DFFs to their respective latest operating states at the same time.

When at least two nonvolatile time sequence elements exist in the control network and control lines between the check rollback controllers are independent of each other, the control network forms a hierarchical structure, the check rollback controllers sequentially read resistance states of memristors built in the nonvolatile time sequence elements according to a hierarchical sequence formed by the hierarchical structure, and the check rollback controllers sequentially configure the resistance states of the memristors built in the nonvolatile time sequence elements according to the same hierarchical sequence. Corresponding to the structure of fig. 3, the check rollback controller may be connected to two nonvolatile DFFs, respectively, and then sequentially control the operation processes of the two nonvolatile DFFs. According to the different quantity and positions of the nonvolatile time sequence elements, the layering structure formed by the control network can be various, the control network can be designed according to actual needs, and after the control network is determined, the layering sequence can be correspondingly determined.

When the structure of the control network is different, the reading configuration process of the check rollback controller on all the nonvolatile time sequence elements is different, and the difference causes the total check time consumption and the total rollback time consumption to be different, and the total check time consumption and the total rollback time consumption of the check rollback controller are related to the structure of the control network. The total time consumption of checking is the time consumption of detecting that the rollback controller controls all the nonvolatile time sequence elements to finish updating and storing the current working state. The total rollback time is the time taken to detect that the rollback controller has controlled all non-volatile sequential elements to complete the recovery to the last operating state.

In one embodiment, the check rollback controller and the control network contained in the high-reliability FPGA are realized by using programmable resources built in the high-reliability FPGA, and due to the characteristics, the functions of the check rollback controller and the structure of the control network can be adjusted and configured through configuration information, and the adjustment and configuration can be realized by the same configuration chain of the FPGA or by a separate configuration chain or be controlled by pin input. Based on the configurable characteristics, the functions of the checking rollback controller and the structure of the control network can be adjusted, so that the checking total time consumption and the rollback total time consumption can be correspondingly adjusted, and the checking total time consumption and the rollback total time consumption can be adjusted to proper values.

In order to store the operating state of each non-volatile sequential element as soon as possible, it is generally desirable to keep the total time spent checking as short as possible, while in order to restore the operating state of each non-volatile sequential element as soon as possible, it is generally desirable to keep the total time spent rolling back as short as possible. When the control line network is designed so that all non-volatile timing elements share the same control line with the check rollback controller, the check rollback controller can be enabled to control each non-volatile timing element simultaneously, so that the total check time and rollback time can be minimized. However, the structure of the control network is not only related to the total time consumed for checking and rolling back, but also affects other performances, such as the wiring area of the control network, the instantaneous current of the control network, etc. When designing the control line network such that all the non-volatile timing elements share the same control line with the check rollback controller, other negative effects may be brought about, such as affecting the wiring area, for example, causing excessive instantaneous current, so that the structure of the control line network cannot be designed with pursuing shorter total check time and rollback time.

As described above, thanks to the fact that the checking rollback controller and the control network are realized based on the utilization of the programmable resources built in the high-reliability FPGA, the programmable resources can be configured according to actual needs to form a proper control network structure so as to achieve better comprehensive performance, and then in the design process of the high-reliability FPGA, the circuit structure of the control network formed by utilizing the programmable resources is matched with the circuit design requirement. The circuit design requirements herein include at least one of a routing area of the control line network, a total time consumption of checking the rollback controller, a maximum instantaneous current of the rollback controller to read a resistance state of the memristor built in each non-volatile timing element, and a maximum instantaneous current of the rollback controller to configure the resistance state of the memristor built in each non-volatile timing element.

The above is only a preferred embodiment of the present application, and the present application is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present application are deemed to be included within the scope of the present application.

Claims (10)

1. The high-reliability FPGA is characterized by comprising at least one nonvolatile time sequence element formed by manufacturing memristors based on variable resistance, and an inspection rollback controller; during operation of the high reliability FPGA:

When the current running state of the high-reliability FPGA has no fault, the detection rollback controller controls each nonvolatile time sequence element to update and store the current working state of the nonvolatile time sequence element by utilizing the resistance state of the built-in memristor;

When the current running state of the high-reliability FPGA has faults, the detection rollback controller controls each nonvolatile time sequence element to restore to the nearest working state of the nonvolatile time sequence element by utilizing the resistance state of the built-in memristor, and drives the high-reliability FPGA to restore to the nearest fault-free running state.

2. The high reliability FPGA of claim 1 wherein,

And in the running process of the high-reliability FPGA, when the current running state of the high-reliability FPGA is determined to be fault-free, the detection rollback controller controls each nonvolatile time sequence element to update and store the current working state of the nonvolatile time sequence element by using the resistance state of the built-in memristor according to a preset checking frequency.

3. The high reliability FPGA of claim 2 wherein,

The checking frequency adopted by the detecting rollback controller is dynamically variable in the running process of the high-reliability FPGA, and the checking frequency is related to at least one of the running state, the running environment and the reliability requirement of the high-reliability FPGA.

4. A high reliability FPGA as claimed in claim 3 wherein during operation of the high reliability FPGA:

temporarily increasing the checking frequency in a preset time period after determining that the running state of the high-reliability FPGA fails, and recovering the checking frequency after determining that the duration time of the running state of the high-reliability FPGA without failure reaches a preset time period;

And/or, when the running environment of the high-reliability FPGA is determined to be bad, increasing the checking frequency;

and/or increasing the checking frequency when the reliability requirement of the high-reliability FPGA is determined to be high.

5. The high reliability FPGA of claim 1, wherein during operation of the high reliability FPGA:

suspending the user function executed by the high-reliability FPGA, performing fault test on the current running state of the high-reliability FPGA, and recovering to execute the user function after the fault test is completed, wherein the detection rollback controller determines whether the current running state of the high-reliability FPGA has a fault according to a fault test result;

and simultaneously carrying out fault test on the current running state of the high-reliability FPGA while the high-reliability FPGA executes the user function, and determining whether the current running state of the high-reliability FPGA has faults or not by the detection rollback controller according to the fault test result.

6. The high reliability FPGA of claim 1 wherein,

The check rollback controller is connected with the control network and controls the resistance state of the memristors built in each nonvolatile time sequence element;

When the same control line is shared between each nonvolatile time sequence element in the control line network and the check rollback controller, the check rollback controller simultaneously reads the resistance state of the memristor built in each nonvolatile time sequence element, and the check rollback controller simultaneously configures the resistance state of the memristor built in each nonvolatile time sequence element;

When at least two nonvolatile time sequence elements exist in the control network and control lines between the checking rollback controllers are independent of each other, the control network forms a hierarchical structure, the checking rollback controllers sequentially read resistance states of memristors built in the nonvolatile time sequence elements according to a hierarchical sequence, and the checking rollback controllers sequentially configure the resistance states of the memristors built in the nonvolatile time sequence elements according to the hierarchical sequence.

7. The high reliability FPGA of claim 6 wherein the inspection total time and rollback total time of the inspection rollback controller are both related to the structure of the control network and are adjustable;

the detection rollback controller controls all nonvolatile time sequence elements to finish updating and storing the current working state;

The total rollback time is the time taken by the detection rollback controller to control all non-volatile sequential elements to complete the recovery to the last operating state.

8. The high reliability FPGA of claim 6 wherein the check rollback controller and the control line network are both implemented using programmable resources built into the high reliability FPGA; in the design process of the high-reliability FPGA, the circuit structure of the control network formed by using programmable resources is matched with the circuit design requirement.

9. The high reliability FPGA of claim 6, wherein the circuit design requirements include at least one of a routing area of a control line network, a total time spent checking by the check rollback controller, a maximum instantaneous current at which the check rollback controller reads a resistance state of a memristor built in each non-volatile timing element, and a maximum instantaneous current at which the check rollback controller configures a resistance state of a memristor built in each non-volatile timing element.

10. The high-reliability FPGA of claim 1, wherein the nonvolatile sequential elements included within the high-reliability FPGA comprise nonvolatile DFFs, nonvolatile BRAMs, and sequential elements providing configuration bits, the sequential elements providing configuration bits comprise nonvolatile distributed random access memories and nonvolatile shift registers, and the nonvolatile BRAMs, nonvolatile distributed random access memories, and nonvolatile shift registers are respectively constructed based on the nonvolatile DFFs;

For the nonvolatile DFF, the check rollback controller controls a data storage signal SET of the nonvolatile DFF to be in an effective level state, and applies a programming voltage PHV at the end part of the memristor so as to control the nonvolatile DFF to store the current working state of the output end of the nonvolatile DFF by utilizing the resistance state of the built-in memristor; the check rollback controller controls a data recovery signal RES of the nonvolatile DFF to be configured in an active level state and a set signal to be in an inactive level state, and a resistance state of a memristor built in the nonvolatile DFF is recovered to a last operation state of the nonvolatile DFF.