CN118235254A - Nitride-based semiconductor device and method of manufacturing the same - Google Patents

Nitride-based semiconductor device and method of manufacturing the same Download PDF

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Publication number
CN118235254A
CN118235254A CN202280075684.4A CN202280075684A CN118235254A CN 118235254 A CN118235254 A CN 118235254A CN 202280075684 A CN202280075684 A CN 202280075684A CN 118235254 A CN118235254 A CN 118235254A
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nitride
based semiconductor
layer
semiconductor layer
etch
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何惠欣
胡凯
张忠宇
黄敬源
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Innoscience Zhuhai Technology Co Ltd
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Innoscience Zhuhai Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, an etching resist layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a larger band gap than the first nitride-based semiconductor layer. A source electrode and a drain electrode are disposed on the second nitride-based semiconductor layer. An etch-resistant layer is disposed on the second nitride-based semiconductor layer. The etching resist layer is in contact with the second nitride-based semiconductor layer and extends from the second nitride-based semiconductor layer to a position higher than the source and drain electrodes. The gate electrode is disposed on the second nitride-based semiconductor layer and has a bottom portion and a middle portion on the bottom portion and wider than the bottom portion.

Description

Nitride-based semiconductor device and method of manufacturing the same
Technical Field
In general, the present invention relates to nitride-based semiconductor devices. More particularly, the present invention relates to nitride-based semiconductor devices having a gate with a stepped profile.
Background
In recent years, research into High Electron Mobility Transistors (HEMTs) has been increasingly popular, particularly for high power switches and high frequency applications. Group III nitride based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2 DEG) region to meet the needs of high power/frequency devices. Examples of devices having a heterostructure include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs) and modulation doped FETs (MODFETs) in addition to HEMTs.
Disclosure of Invention
In one aspect, the present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, an etch resist layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a larger band gap than the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed on the second nitride-based semiconductor layer. An etch-resistant layer is disposed on the second nitride-based semiconductor layer. The etching resist layer is in contact with the second nitride-based semiconductor layer and extends from the second nitride-based semiconductor layer to a position higher than the source and drain electrodes. The gate electrode is disposed on the second nitride-based semiconductor layer and has a bottom portion and a middle portion over and wider than the bottom portion.
In another aspect, the present invention provides a method for fabricating a nitride-based semiconductor device. The method comprises the following steps; forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer to form a heterojunction therebetween; forming a first etch stop layer on the second nitride-based semiconductor layer; forming an opening in the first etch stop layer; forming a second etch stop layer connected to the first etch stop layer on the second nitride-based semiconductor layer; forming a first passivation layer to cover the second etch stop layer; forming an opening in the first passivation layer to expose a portion of the second etch stop layer; removing the exposed portion of the second etch stop layer; and forming a gate aligned with the opening of the first passivation layer.
In yet another aspect, the present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, an etch-resistant layer, a passivation layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a larger band gap than the first nitride-based semiconductor layer. The etching resist layer is disposed on and in contact with the second nitride-based semiconductor layer. The passivation layer is disposed on the second nitride-based semiconductor layer and separated from the second nitride-based semiconductor layer by the etch-resistant layer. The gate electrode is disposed on the second nitride-based semiconductor layer and has a bottom portion and a middle portion over and wider than the bottom portion.
With the above configuration, by the etching stopper layer, the second nitride-based semiconductor layer can be prevented from being damaged in a plurality of etching stages, thereby avoiding the generation of undesired defects in the second nitride-based semiconductor layer.
Drawings
Various aspects of the invention can be readily appreciated from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity. Embodiments of the invention are described in more detail below with reference to the attached drawing figures, wherein:
fig. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present invention.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, and 2J illustrate various stages of a method for fabricating a nitride-based semiconductor device according to some embodiments of the invention;
Fig. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present invention; and
Fig. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present invention.
Detailed Description
The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present invention will be readily understood from the following detailed description in conjunction with the accompanying drawings.
Spatial descriptions such as "upper," "lower," "left," "right," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," etc., are intended to be relative to a certain component or group of components, or a plane of a component or group of components, for the orientation of the components shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that specific implementations of the structures described herein may be spatially arranged in any orientation or manner without departing from the spirit of the present invention.
Further, it should be noted that, subject to device manufacturing conditions, in an actual device, the actual shape of the various structures depicted as being approximately rectangular may be curved, or have rounded corners, or have a slightly non-uniform thickness, etc. Straight lines and right angles are only used to facilitate the presentation of layers and features.
In the following description, a semiconductor device/die/package and a method for manufacturing the same are set forth as preferred examples. It will be apparent that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring. However, the present invention was written in order to enable any person skilled in the art to practice the teachings thereof without undue experimentation.
Fig. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present invention. The nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, etch resist layers 20, 22, 44, 46, electrodes 30 and 32, passivation layers 40, 42, 48, 50, a gate dielectric layer 52, and a gate electrode 54.
The substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, but are not limited to, si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) or other suitable substrate materials. In some embodiments, the substrate 10 may include, for example, but not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 10 may include, but is not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.
In some embodiments, the nitride-based semiconductor device 1A may further include a buffer layer (not shown). A buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer may be configured to reduce lattice and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 12, thereby overcoming defects caused by mismatch/difference. The buffer layer may include a III-V compound. The III-V compounds may include, for example, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials for the buffer layer may further include, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.
In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). A nucleation layer may be formed between the substrate 10 and the buffer layer. The nucleation layer may be configured to provide a transition to accommodate the mismatch/difference between the substrate 10 and the group III nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, but are not limited to, alN or any alloy thereof.
The nitride-based semiconductor layer 12 may be disposed on the buffer layer. The nitride-based semiconductor layer 14 may be disposed on the nitride-based semiconductor layer 12. Exemplary materials for nitride-based semiconductor layer 12 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in xAlyGa(1-x-y) N (x+y.ltoreq.1), or Al xGa(1-x) N (x.ltoreq.1). Exemplary materials for nitride-based semiconductor layer 14 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, in xAlyGa(1-x-y) N (x+y.ltoreq.1), or Al yGa(1-y) N (y.ltoreq.1).
The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the band gap (i.e., the forbidden band width) of the nitride-based semiconductor layer 14 is greater than the band gap of the nitride-based semiconductor layer 12, thereby making their electron affinities different from each other and forming a heterojunction therebetween. For example, when nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of about 3.4eV, nitride-based semiconductor layer 14 may be selected to be an AlGaN layer having a bandgap of about 4.0 eV. In this way, the nitride-based semiconductor layers 12 and 14 can function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A may be used to include at least one GaN-based High Electron Mobility Transistor (HEMT).
Electrodes 30 and 32 are disposed on the nitride-based semiconductor layer 14. The electrode 30 may be in contact with the nitride-based semiconductor layer 14. The electrode 32 may be in contact with the nitride-based semiconductor layer 14. Each electrode 30 and 32 may function as a source or drain. In some embodiments, electrodes 30 and 32 may be referred to as ohmic electrodes.
In some embodiments, electrodes 30 and 32 may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for electrodes 30 and 32 may include, but are not limited to, ti, alSi, tiN, or combinations thereof. The electrodes 30 and 32 may be single or multiple layers of the same or different composition. In some embodiments, the electrodes 30 and 32 may form ohmic contacts with the nitride-based semiconductor layer 14. Ohmic contact may be achieved by applying Ti, al or other suitable materials to the electrodes 30 and 32.
In some embodiments, each electrode 30 and 32 is formed from at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer include, but are not limited to, ti, ta, tiN, al, au, alSi, ni, pt, or combinations thereof. Exemplary materials for the conductive filler may include, but are not limited to AlSi, alCu, or combinations thereof.
Etch-resistant layers 20 and 22 are disposed on nitride-based semiconductor layer 14. The etch-resistant layers 20 and 22 may cover the nitride-based semiconductor layer 14. The etch-resistant layers 20 and 22 may be in contact with the nitride-based semiconductor layer 14. The etch resistant layer 20 may extend to abut the electrode 30. The electrode 30 may pass through the etch-resistant layer 20 to contact the nitride-based semiconductor layer 14. The etch-resistant layer 22 may extend to abut the electrode 32. The electrode 32 may pass through the etch-resistant layer 22 to contact the nitride-based semiconductor layer 14.
Passivation layers 40 and 42 are disposed on etch resistant layers 20 and 22, respectively. Passivation layers 40 and 42 may cover etch resist layers 20 and 22, respectively. Passivation layers 40 and 42 may cover electrodes 30 and 32, respectively.
Etch-resistant layers 44 and 46 are disposed on nitride-based semiconductor layer 14. Etch-resistant layers 44 and 46 may cover nitride-based semiconductor layer 14. Etch-resistant layers 44 and 46 may be in contact with nitride-based semiconductor layer 14. Etch resistant layers 44 and 46 may extend laterally between electrodes 30 and 32. The etch-resistant layer 44 may extend laterally over the electrode 30. The etch-resistant layer 44 may have a portion extending upwardly between the electrodes 30 and 32. The etch-resistant layer 46 may extend laterally over the electrode 32. The etch-resistant layer 46 may have a portion extending upward between the electrodes 30 and 32.
In some embodiments, there may be a visible interface between etch resistant layers 20 and 40. In some embodiments, etch-resistant layers 20 and 40 may be merged with each other such that they may collectively function as a merged etch-resistant layer. The combined etch-resistant layers formed by etch-resistant layers 20 and 40 may extend from nitride based semiconductor layer 14 to a position above electrode 30.
In some embodiments, etch-resistant layers 22 and 42 may have a visible interface therebetween. In some embodiments, etch-resistant layers 22 and 42 may merge with one another, and thus may collectively function as a merged etch-resistant layer. The combined etch resist formed by etch resist layers 22 and 42 may extend from nitride based semiconductor layer 14 to a position above electrode 32.
A passivation layer 48 is disposed on the etch resistant layer 44. Passivation layer 48 covers etch-resistant layer 44. A passivation layer 50 is disposed on etch resist layer 46. Passivation layer 50 covers etch resist layer 46.
The material of the etch resistant layers 20, 22, 44, 46 is different from the material of the passivation layers 40, 42, 48, 50. In some embodiments, exemplary materials for the etch resistant layers 20, 22, 44, 46 may include, but are not limited to, nitride-based dielectric layers. For example, each etch resistant layer 20, 22, 44, 46 is aluminum nitride. In some embodiments, the material of the passivation layers 40, 42, 48, 50 may include, but is not limited to, dielectric materials. For example, passivation layers 40, 42, 48, 50 may include SiN x,SiOx, siON, siC, siBN, siCBN, oxides, nitrides, plasma Enhanced Oxides (PEOX), or combinations thereof. The material difference between the etch-resistant layer 20, 22, 44, 46 and the passivation layer 40, 42, 48, 50 is such that the etch-resistant layer 20, 22, 44, 46 acts as an etch stop layer during the etching phase of the passivation layer 40, 42, 48, 50. With this configuration, the nitride-based semiconductor layer 14 can be prevented from being unintentionally etched, and the geometry of the gate dielectric layer 52 and the gate 54 can be improved.
A gate dielectric layer 52 is disposed on the nitride-based semiconductor layer 14. The gate dielectric layer 52 is connected to the etch resistant layer. The gate dielectric layer 52 is in contact with the nitride-based semiconductor layer 14. Sidewalls of gate dielectric layer 52 may abut and contact etch-resistant layers 44 and 46. Gate dielectric layer 52 may form a stepped profile along the sidewalls of passivation layers 48 and 50. In some embodiments, gate dielectric layer 52 is a silicon nitride layer that may be used as a solidified layer to improve defects in the surface of nitride-based semiconductor layer 14.
A gate electrode 54 is disposed on the nitride-based semiconductor layer 14 and the gate dielectric layer 52. A gate dielectric layer 52 is disposed between the nitride-based semiconductor layer 14 and the gate electrode 54. The gate 54 may fill the gap defined by the gate dielectric layer 52. Gate 54 is located between electrodes 30 and 32. An upwardly extending portion of etch-resistant layer 44 is located between electrode 30 and gate 54. An upwardly extending portion of etch-resistant layer 46 is located between electrode 32 and gate 54.
Gate 54 has a bottom 542, a middle portion 544 on bottom 542, and a top 546 on middle portion 544. The middle portion 544 is wider than the bottom portion 542. The top 546 is wider than the middle portion 544. Sidewalls of the gate 54 are in contact with the gate dielectric layer 52. A stepped interface may be formed between the gate 54 and the sidewalls of the gate dielectric layer 52. Multiple field plate configurations may be achieved by different widths of the gate 54. For example, the ends of the intermediate portion 544 beyond the bottom 542 may serve as field plates. Similarly, the end of the top 546 beyond the middle portion 544 may serve as a field plate.
The gate electrode 54 may be formed as a single layer or as multiple layers of the same or different composition. Exemplary materials for the metal or metal compound may include, but are not limited to, W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.
The structure shown in fig. 1 may be realized by a series of processes in which the nitride-based semiconductor layer 14 is not affected by the etching stage. As described below, fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I and 2J show different stages of a method for manufacturing the semiconductor device 1A. Hereinafter, deposition techniques may include, but are not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other processes.
Referring to fig. 2A, a substrate 10 is provided. A nitride-based semiconductor layer 12 is formed on a substrate 10. A nitride-based semiconductor layer 14 is formed on the nitride-based semiconductor layer 12. An etch stop layer 60 is formed on the nitride-based semiconductor layer 14. A passivation layer 62 is formed on the etch stop layer 60. The nitride-based semiconductor layer 14 and the passivation layer 62 are separated from each other by the etch stop layer 60. During the formation of the passivation layer 62, the electrodes 30 and 32 are formed on the nitride-based semiconductor layer 14. The formation of electrodes 30 and 32 is performed after the formation of etch stop layer 60.
Referring to fig. 2B, a mask layer 64 is formed on the passivation layer 62. The mask layer 64 has an opening to expose the passivation layer 62. Referring to fig. 2C, a portion of passivation layer 62 is removed. In some embodiments, the removal of passivation layer 62 is performed by an etching stage using mask layer 64. After the passivation layer 62 is removed, the etch stop layer 60 is exposed from the passivation layer 62. Since the etch stop layer 60 and the passivation layer 62 have different materials, the etch stop layer 60 may be used to block etching during the etching stage. Referring to fig. 2D, an opening is formed in the etch stop layer 60 in the etching stage. The nitride-based semiconductor layer 14 may be exposed from the opening of the etch stop layer 60.
Referring to fig. 2E, an etch stop layer 66 is formed on the nitride-based semiconductor layer 14. An etch stop layer 66 is also formed on etch stop layer 60 and passivation layer 62. The etch stop layer 66 is connected to the etch stop layer 60 such that the exposed portion of the nitride-based semiconductor layer 14 as shown in fig. 2D is completely covered. Referring to fig. 2F, a passivation layer 68 is formed to cover the etch stop layer 66. Passivation layer 68 is separated from nitride-based semiconductor layer 14 by etch-resistant layers 60 and 66.
Referring to fig. 2G, a mask layer 70 is formed on the passivation layer 68. Mask layer 70 has an opening exposing a portion of passivation layer 68. Referring to fig. 2H, the exposed portions of passivation layer 68 are removed. In some embodiments, the removal of passivation layer 68 is performed by an etching stage using mask layer 70. After removal, an opening is formed in passivation layer 68 to expose a portion of etch stop layer 66.
Referring to fig. 2I, the exposed portion of the etch stop layer 66 is removed such that a portion of the nitride-based semiconductor layer 14 is exposed. Referring to fig. 2J, a gate dielectric layer 52 is formed on the nitride-based semiconductor layer 14. The gate dielectric layer 52 is in contact with the nitride-based semiconductor layer 14. Gate dielectric layer 52 is in contact with etch stop layer 66 and passivation layer 68. Thereafter, a gate may be formed, wherein the gate is aligned with the opening of passivation layer 68. In the above manufacturing process, there are more etching stages. The etch stop layers 60 and 66 may protect the nitride-based semiconductor layer 14 from damage during multiple etching stages to avoid the creation of undesirable defects in the nitride-based semiconductor layer 14.
Fig. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present invention. The nitride-based semiconductor device 1B is similar to the semiconductor device 1A in fig. 1 except that passivation layers 48 and 50, gate dielectric layer 52 and gate 54 are replaced with passivation layers 48B and 50B, gate dielectric layer 52B and gate 54B. The passivation layers 48B and 50B have inner sidewalls inclined with respect to the nitride-based semiconductor layer 14. Accordingly, the gate dielectric layer 52B formed to cover the passivation layers 48B and 50B may have an inclined profile. Gate 54B has a bottom 542B that also has sloped sidewalls. The sloped profile of gate dielectric layer 52B and gate 54B may smooth deposition.
Fig. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present invention. Nitride-based semiconductor device 1C is similar to semiconductor device 1A in fig. 1 except that passivation layers 48 and 50, gate dielectric layer 52 and gate 54 are replaced with passivation layers 48C and 50C, gate dielectric layer 52C and gate 54C. The passivation layers 48C and 50C have inner sidewalls inclined with respect to the nitride-based semiconductor layer 14. Accordingly, the gate dielectric layer 52C formed to cover the passivation layers 48C and 50C may have an inclined profile. Gate 54C has a middle portion 542C, which middle portion 542C also has sloped sidewalls. The sloped profile of gate dielectric layer 52C and gate 54C may smooth deposition.
The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially," "essentially," "about," and "approximately" are used to describe and illustrate minor variations. When used in connection with an event or circumstance, the term can include instances where the event or circumstance occurs precisely and instances where it occurs approximately. For example, when used in conjunction with a numerical value, these terms may encompass a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces lying along a same plane within a micrometer-scale distance, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm lying along the same plane.
As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass a situation in which a previous component is disposed directly on (e.g., in physical contact with) a subsequent component, as well as a situation in which one or more intermediate components are located between the previous component and the subsequent component.
While the invention has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations are not necessarily drawn to scale. There may be a distinction between artistic reproductions and actual devices in the present invention due to manufacturing processes and tolerances. Further, it should be understood that the actual devices and layers may deviate from the rectangular layer depiction of the drawings due to fabrication processes such as conformal deposition, etching, etc., and may include corner surfaces or edges, rounded corners, etc. Other embodiments of the invention not specifically shown are possible. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present invention. All such modifications are intended to be included within the scope of the following claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Thus, unless specifically indicated herein, the order and grouping of operations is not limiting.

Claims (25)

1. A nitride-based semiconductor device comprising:
A first nitride-based semiconductor layer;
A second nitride-based semiconductor layer provided on the first nitride-based semiconductor layer and having a larger band gap than the first nitride-based semiconductor layer;
a source electrode and a drain electrode disposed on the second nitride-based semiconductor layer;
An etching resist layer disposed on the second nitride-based semiconductor layer, wherein the etching resist layer is in contact with the second nitride-based semiconductor layer and extends from the second nitride-based semiconductor layer to a position higher than the source electrode and the drain electrode; and
And a gate electrode disposed on the second nitride-based semiconductor layer and having a bottom portion and an intermediate portion on the bottom portion and wider than the bottom portion.
2. A nitride-based semiconductor device according to any one of the preceding claims, wherein the etch-resistant layer extends laterally between the source and drain.
3. The nitride-based semiconductor device of any one of the preceding claims, wherein the etch-resistant layer extends laterally over the source.
4. The nitride-based semiconductor device of any one of the preceding claims, wherein the etch-resistant layer extends laterally over the drain.
5. A nitride-based semiconductor device according to any one of the preceding claims, wherein the etch-resistant layer extends to abut the source and drain.
6. The nitride-based semiconductor device of any one of the preceding claims, wherein the gate further has a top portion on and wider than the middle portion.
7. A nitride-based semiconductor device according to any one of the preceding claims, further comprising a gate dielectric layer disposed on the second nitride-based semiconductor layer and in contact with the etch-resistant layer.
8. The nitride-based semiconductor device of any one of the preceding claims, wherein the gate dielectric layer is in contact with the second nitride-based semiconductor layer.
9. The nitride-based semiconductor device of any one of the preceding claims, wherein an interface is formed between the gate and the gate dielectric layer.
10. A nitride-based semiconductor device according to any one of the preceding claims, wherein the etch-resistant layer has an upward extension between the source and drain.
11. The nitride-based semiconductor device of any one of the preceding claims, wherein the upwardly extending portion of the etch-resistant layer is located between the source and the gate.
12. The nitride-based semiconductor device of any one of the preceding claims, wherein the upwardly extending portion of the etch-resistant layer is located between the drain and the gate.
13. The nitride-based semiconductor device of any one of the preceding claims, further comprising a passivation layer covering the source and drain electrodes and having a material different from that of the etch-resistant layer.
14. The nitride-based semiconductor device of any one of the preceding claims, wherein the etch-resistant layer covers the second nitride-based semiconductor layer.
15. The nitride-based semiconductor device of any one of the preceding claims, wherein the etch-resistant layer is a nitride-based layer.
16. A method for fabricating a nitride-based semiconductor device, comprising:
forming a first nitride-based semiconductor layer;
Forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer to form a heterojunction therebetween;
forming a first etch stop layer on the second nitride-based semiconductor layer;
forming an opening in the first etch stop layer;
forming a second etch stop layer on the second nitride-based semiconductor layer, wherein the second etch stop layer is connected to the first etch stop layer;
Forming a first passivation layer to cover the second etch stop layer;
Forming an opening in the first passivation layer to expose a portion of the second etch stop layer;
Removing the exposed portion of the second etch stop layer; and
A gate aligned with the opening of the first passivation layer is formed.
17. The method of any of the preceding claims, further comprising forming a second passivation layer after forming the first etch stop layer and before forming the second etch stop layer.
18. The method of any of the preceding claims, further comprising, prior to forming the gate, forming a gate dielectric layer on the second nitride-based semiconductor layer.
19. The method of any of the preceding claims, further comprising forming a source and a drain after forming the first etch stop layer and before forming the second etch stop layer.
20. The method of any of the preceding claims, wherein the second nitride-based semiconductor layer and the first passivation layer are separated from each other by the first and second etch stop layers.
21. A nitride-based semiconductor device comprising:
A first nitride-based semiconductor layer;
A second nitride-based semiconductor layer provided on the first nitride-based semiconductor layer and having a larger band gap than the first nitride-based semiconductor layer;
An etching resist layer provided on the second nitride-based semiconductor layer and in contact with the second nitride-based semiconductor layer;
a passivation layer disposed on the second nitride-based semiconductor layer and separated from the second nitride-based semiconductor layer by the etch-resistant layer; and
And a gate electrode disposed on the second nitride-based semiconductor layer and having a bottom portion and an intermediate portion on the bottom portion and wider than the bottom portion.
22. The nitride-based semiconductor device of any one of the preceding claims, further comprising a gate dielectric layer disposed between the second nitride-based semiconductor layer and the gate.
23. The nitride-based semiconductor device of any one of the preceding claims, wherein the gate dielectric layer is connected to the etch-resistant layer.
24. The nitride-based semiconductor device of any one of the preceding claims, wherein the gate further has a top portion on and wider than the middle portion.
25. The nitride-based semiconductor device of any one of the preceding claims, wherein the etch-resistant layer has an upward extension on the second nitride-based semiconductor layer.
CN202280075684.4A 2022-09-27 2022-09-27 Nitride-based semiconductor device and method of manufacturing the same Pending CN118235254A (en)

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CN103582938A (en) * 2011-06-03 2014-02-12 住友电气工业株式会社 Nitride electronic device and method for manufacturing nitride electronic device
US20200357905A1 (en) * 2019-05-08 2020-11-12 Cambridge Electronics Inc. Iii-nitride transistor device with a thin barrier
WO2022126571A1 (en) * 2020-12-18 2022-06-23 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing thereof
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