CN118228006B - Chip detection method and system based on FPGA technology - Google Patents
Chip detection method and system based on FPGA technology Download PDFInfo
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Abstract
The application relates to the technical field of chip detection electric parameter analysis, in particular to a chip detection method and a chip detection system based on an FPGA technology, wherein the method comprises the following steps: acquiring a voltage signal change sequence and a current signal change sequence of each sub-circuit in the chip during operation; determining a sub-circuit load related characteristic value at each sampling moment; constructing a load gradient stationarity index, and determining a load severe fluctuation coefficient at each sampling moment; the sub-circuit singular indexes at each sampling moment are constructed by combining the load severe fluctuation coefficient and the load gradient stationarity index so as to determine the voltage drop saliency coefficient of each power supply voltage drop analysis sequence; finally, calculating the power supply voltage drop action intensity of each power supply voltage drop analysis sequence; and (3) finishing chip detection through the power supply voltage drop action intensity of each power supply voltage drop analysis sequence of all the sub-circuits. The application improves the fault detection precision of the chip.
Description
Technical Field
The application relates to the technical field of chip detection electric parameter analysis, in particular to a chip detection method and system based on an FPGA technology.
Background
The FPGA chip (Field Programmable GATE ARRAY, FPGA) is a field programmable integrated circuit with an array capable of being edited on site, and has the advantages of repeated editing, high development speed, low investment and the like, so that the FPGA chip is widely applied to the fields of electronic products, communication, video monitoring and the like. However, when the sub-circuits in the FPGA chip work simultaneously, the sub-circuits with larger power have stronger power supply voltage drop effect due to different powers in different sub-circuits, which easily causes the sub-circuits to have abnormal faults due to too low actual power supply voltage.
With the development of data processing technology, signal data of a plurality of sub-circuits are collected when the FPGA chip runs, and the data are processed and analyzed by utilizing a data processing algorithm, so that faults of the sub-circuits in the FPGA chip are identified. Common data processing algorithms, such as clustering algorithms, identify faults in sub-circuits by hierarchical clustering. However, when the clustering algorithm performs clustering analysis, the voltage drop effect of the sub-circuit is not considered, and faults of the sub-circuit cannot be accurately identified through a clustering result, so that the accuracy of detecting the faults of the sub-circuit is poor.
Disclosure of Invention
In order to solve the technical problems, the application aims to provide a chip detection method and a system based on the FPGA technology, and the adopted technical scheme is as follows:
the application provides a chip detection method based on an FPGA technology, which comprises the following steps:
Acquiring a voltage signal change sequence and a current signal change sequence of each sub-circuit in the chip during operation;
Determining a sub-circuit load related characteristic value at each sampling time according to a local correlation between the voltage and the current at each sampling time in the voltage signal change sequence and the current signal change sequence and the distribution condition of the voltage and the current; constructing a load gradient stationarity index through sub-circuit load related characteristic values of each sampling time of each sub-circuit, and determining a load severe fluctuation coefficient of each sampling time;
Combining the load severe fluctuation coefficient and the load gradient stationarity index to construct a sub-circuit singular index at each sampling moment; constructing each power supply voltage drop analysis sequence of each sub-circuit through sub-circuit singular indexes of all sampling moments of each sub-circuit;
Determining the voltage drop highlighting coefficient of each power supply drop analysis sequence through the difference between the data in the power supply drop analysis sequence of each sub-circuit by combining a threshold segmentation algorithm;
combining the voltage drop salient coefficients of the power supply drop analysis sequences and the data in the power supply drop analysis sequences to determine the power supply drop action intensity of the power supply drop analysis sequences;
and (3) finishing chip detection through the power supply voltage drop action intensity of each power supply voltage drop analysis sequence of all the sub-circuits.
Preferably, the determining process of the sub-circuit load related characteristic value at each sampling time is as follows:
Calculating the correlation between the local voltage fluctuation sequence and the local current fluctuation sequence at each sampling moment, respectively obtaining the variation coefficients of the local voltage fluctuation sequence and the local current fluctuation sequence at each sampling moment, calculating the difference of the two variation coefficients, and marking the difference as variation difference;
the sub-circuit load related characteristic value and the variation difference form a negative correlation relationship and a positive correlation relationship.
Preferably, the construction process of the load gradient stability index comprises the following steps:
the load-related characteristic values of the sub-circuits at all sampling moments of each sub-circuit form a load characteristic change sequence of each sub-circuit;
Aiming at each sub-circuit load related characteristic value in the load characteristic change sequence, forming a load characteristic extraction sequence of each sub-circuit load related characteristic value by a plurality of sub-circuit load related characteristic values which are closest to each sub-circuit load related characteristic value, and carrying out trending analysis on each load characteristic extraction sequence to obtain a load stable fluctuation component sequence at a sampling moment corresponding to each sub-circuit load related characteristic value;
Calculating the absolute value of the difference between each element and other elements in the load stable fluctuation component sequence at each sampling moment, and recording the absolute value as a first element difference;
And the load gradient stationarity index of each element in the load stationary fluctuation component sequence at each sampling moment and the first element difference form a negative correlation.
Preferably, the determining process of the load severe fluctuation coefficient at each sampling time is as follows:
Acquiring information entropy of a load characteristic extraction sequence at each sampling moment; calculating absolute values of differences between adjacent elements in the load characteristic extraction sequence at each sampling moment, and marking the absolute values as second element differences; obtaining a subtraction result of a maximum value and a minimum value in a load characteristic extraction sequence at each sampling moment;
Accumulating the products of the second element differences obtained by calculation of all adjacent elements in the load characteristic extraction sequence at each sampling moment and the subtraction result;
And the load sharp fluctuation coefficient at each sampling moment and the accumulated result and the information entropy form a positive correlation relation.
Preferably, the singular indexes of the sub-circuits form positive correlation with the severe load fluctuation coefficients at each sampling time, and form positive correlation with the mean square error of the load gradient stationarity indexes at all sampling times in the load stationary fluctuation component sequences at each sampling time.
Preferably, the construction process of each power supply voltage drop analysis sequence of each sub-circuit is as follows:
The power singular change sequence of each sub-circuit is formed by the sub-circuit singular indexes of all sampling moments of each sub-circuit, the power singular change sequence is equally divided into a plurality of power singular change sub-sequences, and the power singular change sub-sequences are determined to be the power supply voltage drop analysis sequences of each sub-circuit.
Preferably, the determining process of the voltage drop saliency coefficient of each power supply drop analysis sequence is as follows:
Dividing the singular indexes of the sub-circuits in the power supply voltage drop analysis sequence by acquiring a segmentation threshold value, forming a power supply voltage drop characteristic set of the power supply voltage drop analysis sequence by all the singular indexes of the sub-circuits higher than the segmentation threshold value in the power supply voltage drop analysis sequence, and forming a power supply voltage drop characteristic comparison set by all the singular indexes of the sub-circuits lower than the segmentation threshold value;
Calculating the average value of the power supply voltage drop characteristic comparison set of the power supply voltage drop analysis sequence, and recording the average value as a first singular index average value;
Calculating absolute values of differences between singular indexes of all subcircuits in a power supply voltage drop characteristic set of a power supply voltage drop analysis sequence and the first singular index mean value, and marking the absolute values as first absolute values;
calculating absolute values of differences between singular indexes of all sub-circuits in a power supply voltage drop characteristic set of the power supply voltage drop analysis sequence and a segmentation threshold value of the power supply voltage drop analysis sequence, and marking the absolute values as second absolute values;
And determining the sum of the products of the first absolute value and the second absolute value, which are obtained by calculating the singular indexes of all the subcircuits in the power supply voltage drop characteristic set of the power supply voltage drop analysis sequence, as a voltage drop saliency coefficient of the power supply voltage drop analysis sequence.
Preferably, the power supply voltage drop action intensity and the average value of the power supply voltage drop characteristic set of the power supply voltage drop analysis sequence form a positive correlation.
Preferably, the chip detection is completed by the power supply voltage drop action intensity of each power supply voltage drop analysis sequence of all the sub-circuits, and the process is as follows:
dividing the power supply voltage drop action intensity of the power supply voltage drop analysis sequences of all the sub-circuits by adopting a clustering algorithm, and calculating the average value of each cluster;
And counting the subcircuits corresponding to the power supply voltage drop action intensities in the cluster with the maximum average value for the cluster with the maximum average value, and determining the subcircuits corresponding to the maximum number of the power supply voltage drop action intensities in the cluster with the maximum average value as the voltage drop fault circuit.
The application also provides a chip detection system based on the FPGA technology, which comprises a memory, a processor and a computer program stored in the memory and running on the processor, wherein the processor realizes the steps of any one of the methods when executing the computer program.
From the above, the chip detection method based on the FPGA technology provided by the application has at least the following beneficial effects:
The application constructs the load related characteristic value of the sub-circuit based on the analysis of the load related characteristic of the sub-circuit by the voltage signal change sequence and the current signal change sequence, and fully describes the load characteristic of the sub-circuit; analyzing the load gradient stationarity and the load violent fluctuation degree based on a load characteristic change sequence constructed by the load related characteristic values of the sub-circuit, constructing a sub-circuit power singular index by combining the load gradient stationarity index and the load violent fluctuation coefficient, measuring the sub-circuit power singularity more accurately, and improving the accuracy of subsequent clustering analysis; analyzing the power supply voltage drop salient features based on the power singular change sequence constructed by the sub-circuit power singular indexes, and constructing the power supply voltage drop action intensity through the voltage drop salient coefficients, so that the measurement results of the power supply voltage drop action intensities of different sub-circuits are more accurate; and acquiring a power supply voltage drop clustering set based on the power supply voltage drop action intensity, and improving the accuracy of clustering analysis. The application utilizes the CURE hierarchical clustering algorithm to detect the voltage drop fault circuit based on the power supply voltage drop clustering set, considers the voltage drop effect of the sub-circuit, and accurately identifies the faults of the sub-circuit through the clustering result, so that the accuracy of detecting the faults of the sub-circuit is higher.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions and advantages of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of a method for detecting a chip based on FPGA technology according to an embodiment of the present application;
fig. 2 is a schematic diagram of a power supply voltage drop action intensity extraction flow.
Detailed Description
In order to further describe the technical means and effects adopted by the application to achieve the preset aim, the following detailed description refers to specific implementation, structure, characteristics and effects of a chip detection method and system based on FPGA technology according to the present application by referring to the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" means that the embodiments are not necessarily the same. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
The application provides a chip detection method and a chip detection system based on an FPGA technology, which are specifically described below with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of steps of a method for detecting a chip based on FPGA technology according to an embodiment of the present application is shown, where the method includes the following steps:
S1, collecting a sub-circuit voltage signal change sequence and a current signal change sequence when the FPGA chip runs.
The embodiment aims to improve the accuracy of fault detection of a sub-circuit during operation of an FPGA chip, facilitate subsequent optimization in the design of the FPGA chip, and further improve the quality of an FPGA integrated chip.
An Analog-to-Digital Converter (ADC) is arranged in the FPGA chip, and the Analog-to-Digital Converter converts the voltage and the current of the sub-circuit in the FPGA chip into a voltage digital signal and a current digital signal respectively and outputs the voltage and the current digital signal. And an analog-to-digital conversion module is arranged in the FPGA chip, the accuracy, the step number, the cycle number and the like of the AD module can be configured through the upper computer system, the batch sampling of the related data of the circuit to be tested in the chip is realized, and the data are automatically analyzed and converted.
Specifically, an input channel of the analog-to-digital conversion module is connected with each sub-circuit in the FPGA chip, and when the FPGA chip operates, a voltage digital signal and a current digital signal of each sub-circuit are sampled at an output signal end of the analog-to-digital conversion module.
Preferably, in one embodiment of the present application, when the voltage and current data are collected, the data sampling frequency in this embodiment is 10kHz, and the number of voltage digital signals and the number of current digital signals sampled by each sub-circuit are 500. As another embodiment, the implementer may decide the sampling rate and the sampling number according to the actual situation.
Further, the sequences of the voltage digital signals and the current digital signals obtained by sampling each sub-circuit are respectively used as a voltage signal change sequence and a current signal change sequence of each sub-circuit according to the sequence of time, and an adaptive filtering algorithm is adopted to respectively carry out filtering pretreatment on the voltage signal change sequence and the current signal change sequence of each sub-circuit so as to avoid noise data influence, wherein the adaptive filtering algorithm is a known technology, and the specific process is not repeated.
It should be understood that, as an embodiment of the present application, the adaptive filtering algorithm is used to perform filtering processing on the acquired data sequence, and the foregoing merely provides a method for performing filtering denoising on the voltage and current signal variation sequence, and as other embodiments, other denoising algorithms in the prior art may be used to perform denoising preprocessing on the voltage and current signal variation sequence on the premise of achieving the purpose of denoising the voltage and current signal variation sequence.
Thus, a voltage signal change sequence and a current signal change sequence are obtained for each sub-circuit.
S2, acquiring a sub-circuit load related characteristic value based on the voltage signal change sequence and the current signal change sequence.
Under normal conditions, when the sub-circuits in the FPGA chip work simultaneously, as the power in different sub-circuits is different, the sub-circuit with larger power has stronger power supply voltage drop effect along with the operation of the FPGA chip, and at the moment, the voltage signal and the current signal can change greatly. In order to analyze for power supply voltage drop effects, analysis based on voltage signals as well as current signals is required.
Specifically, in order to analyze the voltage drop effect of the power supply when the load in the FPGA chip changes, each sub-circuit is respectively centered on each element in the voltage signal change sequence and the current signal change sequence, and is provided withThe window with the size is used as a sequence window of each element, a sequence formed by the elements in the sequence window of each element in the voltage signal change sequence is used as a local voltage fluctuation sequence of each element corresponding to the sampling moment, and a sequence formed by the elements in the sequence window of each element in the current signal change sequence is used as a local current fluctuation sequence of each element corresponding to the sampling moment.
Normally, the load of the subcircuit in the FPGA chip is stable, and when a strong power supply voltage drop acts in the circuit, the load can change greatly, and at the moment, the correlation between the voltage and the current in the circuit changes greatly. Therefore, to analyze the power supply voltage drop effect of the circuit, it is necessary to extract the load characteristics of the circuit.
Based on the analysis, calculating the load related characteristic value of the sub-circuit for each sub-circuit, wherein the specific process is as follows:
Calculating the correlation between the local voltage fluctuation sequence and the local current fluctuation sequence at each sampling moment, respectively obtaining the variation coefficients of the local voltage fluctuation sequence and the local current fluctuation sequence at each sampling moment, calculating the difference of the two variation coefficients, and marking the difference as variation difference; the sub-circuit load related characteristic value and the variation difference form a negative correlation relationship and a positive correlation relationship.
It is to be understood that the positive correlation and the negative correlation of the present application refer to the relationship between the independent variable and the dependent variable, and the positive correlation refers to the increase (decrease) of the independent variable with the increase (decrease) of the dependent variable, and may be an addition relationship, a multiplication relationship, or the like; the negative correlation is that the independent variable decreases (increases) with increasing (decreasing) of the dependent variable, and may be an inverse relationship, a subtraction relationship, or the like.
Preferably, the load related characteristic value of the sub-circuit may be a ratio of the correlation and the variation difference, where the correlation may be a pearson correlation coefficient, and as other embodiments, on the basis of achieving the purpose of measuring the correlation of two sequences, an implementer may obtain the correlation of two sequences by using other methods in the prior art, and the application is not limited in particular.
It should be noted that, the stronger the correlation between the local current and the local voltage change characteristic, the more stable the correlation between the voltage and the current in the circuit, the more stable the load, and the smaller the difference between the two coefficients of variation is utilized, the more fully the load characteristic of the sub-circuit is described, and the larger the correlation between the voltage and the current, namely the stronger the load correlation characteristic of the sub-circuit.
And S3, acquiring a load characteristic extraction sequence and a load stable fluctuation component sequence based on the load related characteristic value of the sub-circuit, and acquiring a sub-circuit power singular index according to the load characteristic extraction sequence and the load stable fluctuation component sequence.
Further, to analyze the power supply voltage drop effect through the load-related characteristics of the sub-circuit, it is necessary to first analyze the changes in the load-related characteristics of the sub-circuit. In general, the load related characteristics of the sub-circuit have larger variation, reflecting the singular variation of the power of the sub-circuit, and the more likely the power drop effect in the FPGA chip is caused.
Specifically, in one embodiment of the present application, for each sub-circuit, a sequence of sub-circuit load related characteristic values at all sampling moments according to the chronological order is used as a load characteristic change sequence of each sub-circuit. For each sub-circuit load related characteristic value of the load characteristic change sequence of each sub-circuit, the 40 sub-circuit load related characteristic values with the nearest Euclidean distance between the sub-circuit load related characteristic values are used as a load characteristic extraction sequence of each sub-circuit load related characteristic value according to the sequence formed by the sequence of time sequence.
It should be understood that, the load related characteristic values of the sub-circuits at all sampling moments are formed into the load characteristic change sequence of each sub-circuit according to the time sequence, which is just one embodiment of the present application, and as other embodiments, the implementers do not need to sort completely according to the time sequence, and the implementers decide at their own discretion according to the actual application situation, and the present application is not particularly limited.
Meanwhile, the embodiment is provided only for 40 sub-circuit load related characteristic values with the nearest Euclidean distance, and under the premise of realizing the purpose of selecting a plurality of sub-circuit load related characteristic values which are closer to each sub-circuit load related characteristic value, an implementer can select other distance measurement modes, and can set a preset number of sub-circuit load related characteristic values by himself, and the implementation is determined according to practical application.
In order to analyze the stable variation characteristics of the load characteristic extraction sequence, the load characteristic extraction sequence of each sub-circuit load related characteristic value is used as the input of a DFA trending fluctuation analysis algorithm (DETRENDED FLUCTUATION ANALYSIS), and the output of the DFA trending fluctuation analysis algorithm is used as the load stable fluctuation component sequence of the sampling moment corresponding to each sub-circuit load related characteristic value, wherein the DFA trending fluctuation analysis algorithm is a known technology, and the specific process is not repeated.
Based on the analysis, calculating the absolute value of the difference between each element and other elements in the load stable fluctuation component sequence at each sampling moment, and recording the absolute value as a first element difference; and the load gradient stationarity index of each element in the load stationary fluctuation component sequence at each sampling moment and the first element difference form a negative correlation.
For one embodiment of the present application, the load ramp stationarity index of the j-th element in the load stationary fluctuation component sequence for each sampling instant may be: and obtaining the opposite number of the first element difference, taking the opposite number as an index of an exponential function taking a natural constant as a base number, and taking the average value of calculation results of the exponential function obtained between the jth element and other elements in the load stable fluctuation component sequence as the load gradient stationarity index of the jth element in the load stable fluctuation component sequence.
Further, the difference and fluctuation conditions among elements in the load characteristic extraction sequence at each sampling moment are combined, and a load severe fluctuation coefficient at each sampling moment is constructed, specifically:
calculating information entropy of a load feature extraction sequence at each sampling moment, obtaining absolute values of differences between adjacent elements in the load feature extraction sequence at each sampling moment, and calculating a subtraction result of a maximum value and a minimum value in the load feature extraction sequence at each sampling moment; accumulating the products of the absolute values obtained by calculation of all adjacent elements in the load characteristic extraction sequence at each sampling moment and the subtraction result;
And the load sharp fluctuation coefficient at each sampling moment and the accumulated result and the information entropy form a positive correlation relation.
It should be understood that the positive correlation refers to the relationship between the independent variable and the dependent variable, and when the independent variable increases or decreases, the dependent variable also increases or decreases, that is, the change directions of the two variables are the same, the positive correlation may be a multiplication relationship, an addition relationship, a direct-ratio relationship, or the like, and the application is not limited in particular, and in one example of the application, the load drastic fluctuation coefficient is the product of the accumulated result and the information entropy.
Further, calculating the singular indexes of the sub-circuits at each sampling time according to the severe load fluctuation coefficient and the fluctuation condition of the load gradient stationarity indexes at all sampling times in the load steady fluctuation component sequence. The singular indexes of the sub-circuits form a positive correlation with the load severe fluctuation coefficient of each sampling moment and the mean square error of the load gradient stationarity indexes of all sampling moments in the load stationary fluctuation component sequences of each sampling moment.
It should be understood that, for the positive correlation of the present application, only for explaining a correlation between an independent variable and a dependent variable, the positive correlation is that the independent variable increases with the increase of the dependent variable, decreases with the decrease of the dependent variable, may be an addition relationship, a multiplication relationship, etc., and is specifically determined according to practical applications, the present application is not particularly limited.
Preferably, as an embodiment of the present application, the sub-circuit singular index is a product of a load sharp fluctuation coefficient and the mean square error.
The load gradient stationarity index is measured through element differences in the load stable fluctuation component sequences, the smaller the load gradient stationarity index is, the larger the singular change of power in the sub-circuit is reflected, meanwhile, the load severe fluctuation coefficient is extracted through the load characteristic extraction sequences and is involved in calculation of the sub-circuit power singular index, so that the measurement of the sub-circuit power singularity is more accurate, and the accuracy of the subsequent clustering analysis is improved.
S4, acquiring the action intensity of the voltage drop of the power supply according to the singular index of the power of the sub-circuit.
Further, in order to analyze the voltage drop effect of the power supply of the sub-circuit, a power singular change sequence is constructed based on the obtained power singular index of the sub-circuit.
Specifically, the singular indexes of the power of the sub-circuits at all sampling moments of each sub-circuit are formed into a singular power change sequence of each sub-circuit.
Further, in order to extract the power supply voltage drop effect of each sub-circuit, it is necessary to extract the power supply voltage drop analysis sequence through the power singular change sequence.
Specifically, for each sub-circuit, the power singular variation sequence is used as the input of a sequence division algorithm, the power singular variation sequence is uniformly divided into a plurality of power singular variation sub-sequences by the sequence division algorithm, the output of the sequence division algorithm is used as all the power singular variation sub-sequences of each sub-circuit, and each power singular variation sub-sequence of each sub-circuit is used as each power supply voltage drop analysis sequence of each sub-circuit.
Preferably, in one embodiment of the present application, each power singular change sequence is uniformly divided into 50 power singular change subsequences, which can be set by an implementer.
In order to analyze the power supply voltage drop characteristics of each sub-circuit, a power supply voltage drop analysis sequence needs to be subjected to characteristic extraction. In general, the stronger the power singularity characteristic in the sub-circuit, the stronger the power supply voltage drop acting force in the circuit at this time, and in order to analyze the power supply voltage drop characteristic more accurately, the power supply voltage drop characteristic set and the power supply voltage drop characteristic comparison set need to be extracted first.
Therefore, the application divides the singular indexes of all the sub-circuits in the power supply voltage drop analysis sequence by combining the division threshold values. As an embodiment of the present application, specifically, all the singular indexes of the sub-circuits in the power supply voltage drop analysis sequence are used as the input of the maximum inter-class variance algorithm, the singular indexes of the sub-circuits higher than the segmentation threshold are used as the power supply voltage drop feature comparison elements, the singular indexes of the sub-circuits lower than the segmentation threshold are used as the power supply voltage drop feature comparison elements, the output of the maximum inter-class variance algorithm is used as all the power supply voltage drop feature elements and all the power supply voltage drop feature comparison elements, the set formed by all the power supply voltage drop feature elements is used as the power supply voltage drop feature set, and the set formed by all the power supply voltage drop feature comparison elements is used as the power supply voltage drop feature comparison set, wherein the maximum inter-class variance algorithm is a known technology, and the detailed process is not repeated.
It should be understood that the embodiment of the present application only provides a way to divide the singular indexes of each sub-circuit in the power supply voltage drop analysis sequence, and in other embodiments, the data in the power supply voltage drop analysis sequence may be divided by using other division algorithms in the prior art without special limitation on the present application under the premise of ensuring the purpose of dividing the power supply voltage drop analysis sequence.
Based on the analysis, the application calculates the voltage drop saliency coefficient of the power supply drop analysis sequence. For each sub-circuit, calculating the average value of the power supply voltage drop characteristic comparison set of the power supply voltage drop analysis sequence, and recording the average value as a first singular index average value; calculating absolute values of differences between singular indexes of all subcircuits in a power supply voltage drop characteristic set of a power supply voltage drop analysis sequence and the first singular index mean value, and marking the absolute values as first absolute values; calculating absolute values of differences between singular indexes of all sub-circuits in a power supply voltage drop characteristic set of the power supply voltage drop analysis sequence and a segmentation threshold value of the power supply voltage drop analysis sequence, and marking the absolute values as second absolute values;
and accumulating the products of the first absolute value and the second absolute value, which are obtained by calculating the singular indexes of all the subcircuits in the power supply voltage drop characteristic set of the power supply voltage drop analysis sequence, and taking the accumulated results as voltage drop salient coefficients of the power supply voltage drop analysis sequence.
Further, the power supply voltage drop action intensity of the power supply voltage drop analysis sequence is calculated according to the voltage drop salient coefficient of the power supply voltage drop analysis sequence and the power supply voltage drop characteristic set of the power supply voltage drop analysis sequence, wherein the power supply voltage drop action intensity of the power supply voltage drop analysis sequence and the voltage drop salient coefficient form a positive correlation, and the power supply voltage drop action intensity and the average value of the power supply voltage drop characteristic set of the power supply voltage drop analysis sequence form a positive correlation.
It should be noted that, the positive correlation relationship in the present application is that the independent variable increases with the increase of the dependent variable, and the independent variable decreases with the decrease of the dependent variable, and the specific positive correlation relationship may be a multiplication relationship, an addition relationship, an exponential function, etc., and is determined according to the actual situation in the application process, and the present application is not limited in particular.
Preferably, as an embodiment of the present application, the power supply voltage drop action intensity of the power supply voltage drop analysis sequence is the product of the average value of the power supply voltage drop characteristic set of the power supply voltage drop analysis sequence and the voltage drop saliency coefficient.
It can be understood that by means of the difference between the element in the power supply voltage drop feature set and the average value of the power supply voltage drop feature contrast set and the difference between the element in the power supply voltage drop feature set and the segmentation threshold value, the measurement of the power supply voltage drop salient feature is more accurate, so that the power supply voltage drop effect is measured by means of the power supply voltage drop salient feature and the average value of the power singular feature represented in the power supply voltage drop feature set, the measurement results of the power supply voltage drop effect intensities of different subcircuits are more accurate, and the accuracy of the subsequent clustering analysis is improved.
Thus, the power supply voltage drop action intensity of all power supply voltage drop analysis sequences of each sub-circuit is obtained.
In some embodiments of the present application, a schematic diagram of the power supply voltage drop action intensity extraction process is shown in fig. 2.
S5, identifying a voltage drop fault circuit by using the voltage drop action intensity of the power supply, and finishing accurate detection of the circuit faults in the chip.
In order to identify the power supply voltage drop faults of the sub-circuits in the FPGA chip, the fault detection is carried out on the internal circuits of the chip by combining a clustering algorithm based on the power supply voltage drop action intensity of the power supply voltage drop analysis sequences of all the sub-circuits.
In some embodiments of the application, a CURE hierarchical clustering algorithm (Clustering Using Representative) is used to cluster the power supply voltage drop intensity of the power supply voltage drop analysis sequences of all sub-circuits. As other embodiments, the implementer may also employ other clustering methods of the prior art.
The method comprises the steps of taking a set formed by the power supply voltage drop action intensities of power supply voltage drop analysis sequences of all sub-circuits as a power supply voltage drop clustering set, taking the power supply voltage drop clustering set as the input of a CURE hierarchical clustering algorithm (Clustering Using Representative), wherein the values of the cluster number, the representative point number and the shrinkage factor embodiment in the necessary parameters are respectively 15, 20 and 0.5, and taking the output of the CURE hierarchical clustering algorithm as the clustering analysis result of the power supply voltage drop clustering set, wherein the CURE hierarchical clustering algorithm is a known technology, and the specific process is not repeated.
Further, calculating the average value of the voltage drop action intensity of all power supplies in each cluster in the cluster analysis result, taking the cluster corresponding to the largest average value as a target cluster, counting the number of the voltage drop action intensity of the power supplies belonging to each sub-circuit in the target cluster by a statistical method, and taking the sub-circuit corresponding to the largest number of the voltage drop action intensity of the power supplies as a voltage drop fault circuit, so that the voltage drop fault circuit is indicated to be subjected to the voltage drop of the power supplies to cause abnormal faults.
Based on the same inventive concept as the above method, the embodiment of the application further provides a chip detection system based on FPGA technology, which includes a memory, a processor, and a computer program stored in the memory and running on the processor, where the processor implements the steps of any one of the above methods for chip detection based on FPGA technology when executing the computer program.
It should be noted that: the sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. And the foregoing description has been directed to specific embodiments of this specification. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather, any modifications, equivalents, improvements, etc. that fall within the principles of the present application are intended to be included within the scope of the present application.
Claims (9)
1. The chip detection method based on the FPGA technology is characterized by comprising the following steps of:
Acquiring a voltage signal change sequence and a current signal change sequence of each sub-circuit in the chip during operation;
Determining a sub-circuit load related characteristic value at each sampling time according to a local correlation between the voltage and the current at each sampling time in the voltage signal change sequence and the current signal change sequence and the distribution condition of the voltage and the current; constructing a load gradient stationarity index through sub-circuit load related characteristic values of each sampling time of each sub-circuit, and determining a load severe fluctuation coefficient of each sampling time;
Combining the load severe fluctuation coefficient and the load gradient stationarity index to construct a sub-circuit singular index at each sampling moment; constructing each power supply voltage drop analysis sequence of each sub-circuit through sub-circuit singular indexes of all sampling moments of each sub-circuit;
Determining the voltage drop highlighting coefficient of each power supply drop analysis sequence through the difference between the data in the power supply drop analysis sequence of each sub-circuit by combining a threshold segmentation algorithm;
combining the voltage drop salient coefficients of the power supply drop analysis sequences and the data in the power supply drop analysis sequences to determine the power supply drop action intensity of the power supply drop analysis sequences;
The chip detection is completed through the power supply voltage drop action intensity of each power supply voltage drop analysis sequence of all the sub-circuits;
the chip detection is completed through the power supply voltage drop action intensity of each power supply voltage drop analysis sequence of all the sub-circuits, and the process is as follows:
dividing the power supply voltage drop action intensity of the power supply voltage drop analysis sequences of all the sub-circuits by adopting a clustering algorithm, and calculating the average value of each cluster;
And counting the subcircuits corresponding to the power supply voltage drop action intensities in the cluster with the maximum average value for the cluster with the maximum average value, and determining the subcircuits corresponding to the maximum number of the power supply voltage drop action intensities in the cluster with the maximum average value as the voltage drop fault circuit.
2. The method for detecting a chip based on FPGA technology as claimed in claim 1, wherein the determining process of the sub-circuit load related characteristic value at each sampling time is:
Calculating the correlation between the local voltage fluctuation sequence and the local current fluctuation sequence at each sampling moment, respectively obtaining the variation coefficients of the local voltage fluctuation sequence and the local current fluctuation sequence at each sampling moment, calculating the difference of the two variation coefficients, and marking the difference as variation difference;
the sub-circuit load related characteristic value and the variation difference form a negative correlation relationship and a positive correlation relationship.
3. The method for detecting a chip based on the FPGA technology as claimed in claim 2, wherein the construction process of the load gradient stationarity index is as follows:
the load-related characteristic values of the sub-circuits at all sampling moments of each sub-circuit form a load characteristic change sequence of each sub-circuit;
Aiming at each sub-circuit load related characteristic value in the load characteristic change sequence, forming a load characteristic extraction sequence of each sub-circuit load related characteristic value by a plurality of sub-circuit load related characteristic values which are closest to each sub-circuit load related characteristic value, and carrying out trending analysis on each load characteristic extraction sequence to obtain a load stable fluctuation component sequence at a sampling moment corresponding to each sub-circuit load related characteristic value;
Calculating the absolute value of the difference between each element and other elements in the load stable fluctuation component sequence at each sampling moment, and recording the absolute value as a first element difference;
And the load gradient stationarity index of each element in the load stationary fluctuation component sequence at each sampling moment and the first element difference form a negative correlation.
4. The method for detecting a chip based on the FPGA technology as claimed in claim 3, wherein the determining process of the load sharp fluctuation coefficient at each sampling time is:
Acquiring information entropy of a load characteristic extraction sequence at each sampling moment; calculating absolute values of differences between adjacent elements in the load characteristic extraction sequence at each sampling moment, and marking the absolute values as second element differences; obtaining a subtraction result of a maximum value and a minimum value in a load characteristic extraction sequence at each sampling moment;
Accumulating the products of the second element differences obtained by calculation of all adjacent elements in the load characteristic extraction sequence at each sampling moment and the subtraction result;
and the load sharp fluctuation coefficient at each sampling moment and the accumulated result and the information entropy form a positive correlation relation.
5. The method for detecting chips based on FPGA technology as defined in claim 4, wherein said sub-circuit singular indexes are in positive correlation with the load sharp fluctuation coefficients at each sampling time, and in positive correlation with the mean square error of the load gradient stationarity indexes at all sampling times in the load steady fluctuation component sequences at each sampling time.
6. The method for detecting a chip based on FPGA technology as claimed in claim 1, wherein the power supply voltage drop analysis sequence of each sub-circuit is constructed by:
The power singular change sequence of each sub-circuit is formed by the sub-circuit singular indexes of all sampling moments of each sub-circuit, the power singular change sequence is equally divided into a plurality of power singular change sub-sequences, and the power singular change sub-sequences are determined to be the power supply voltage drop analysis sequences of each sub-circuit.
7. The method for detecting a chip based on FPGA technology as claimed in claim 6, wherein the determining process of the voltage drop saliency coefficient of each power drop analysis sequence is:
Dividing the singular indexes of the sub-circuits in the power supply voltage drop analysis sequence by acquiring a segmentation threshold value, forming a power supply voltage drop characteristic set of the power supply voltage drop analysis sequence by all the singular indexes of the sub-circuits higher than the segmentation threshold value in the power supply voltage drop analysis sequence, and forming a power supply voltage drop characteristic comparison set by all the singular indexes of the sub-circuits lower than the segmentation threshold value;
Calculating the average value of the power supply voltage drop characteristic comparison set of the power supply voltage drop analysis sequence, and recording the average value as a first singular index average value;
Calculating absolute values of differences between singular indexes of all subcircuits in a power supply voltage drop characteristic set of a power supply voltage drop analysis sequence and the first singular index mean value, and marking the absolute values as first absolute values;
calculating absolute values of differences between singular indexes of all sub-circuits in a power supply voltage drop characteristic set of the power supply voltage drop analysis sequence and a segmentation threshold value of the power supply voltage drop analysis sequence, and marking the absolute values as second absolute values;
And determining the sum of the products of the first absolute value and the second absolute value, which are obtained by calculating the singular indexes of all the subcircuits in the power supply voltage drop characteristic set of the power supply voltage drop analysis sequence, as a voltage drop saliency coefficient of the power supply voltage drop analysis sequence.
8. The method for detecting a chip based on the FPGA technology as claimed in claim 7, wherein the power supply voltage drop action intensity is in positive correlation with the voltage drop saliency coefficient of the power supply voltage drop analysis sequence and the average value of the power supply voltage drop feature set of the power supply voltage drop analysis sequence.
9. A chip detection system based on FPGA technology, comprising a memory, a processor and a computer program stored in said memory and running on said processor, characterized in that said processor implements the steps of the method according to any of claims 1-8 when said computer program is executed.
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