CN118227178B - FPGA firmware updating method and device - Google Patents

Abstract

The invention belongs to the field of electrical data processing, and discloses a method and a device for updating FPGA firmware, wherein the method comprises the following steps: after the FPGA completes initialization, an embedded processor receives a firmware update instruction sent by an upper computer through a communication interface; responding to a firmware update instruction, and driving a QSPI controller to erase the Flash by the processor; the processor receives new FPGA firmware from the upper computer through the communication interface; the processor drives the QSPI controller to write new FPGA firmware into Flash; resetting the FPGA to complete the FPGA firmware update. The invention reduces the hardware resources required while realizing the upgrading of the FPGA firmware.

Description

FPGA firmware updating method and device

Technical Field

The invention belongs to the Field of electric digital data processing, and particularly relates to an FPGA (Field-Programmable gate array) firmware updating method.

Background

The FPGA has extremely high configurability, and the functions required to be realized by the FPGA chip can be customized according to the requirements in the design stage. In the process of developing a system by using an FPGA, there is often a need for functional change or improvement, so that FPGA configuration information needs to be changed. Changing the FPGA configuration information generally requires re-programming the external Flash storing the FPGA configuration information using a dedicated download, and if the product is delivered to the customer, it takes more manpower and capital costs to re-update the FPGA firmware, which is not friendly to the user.

As shown in fig. 1, the existing FPGA firmware updating scheme uses an independent CPU (Central Processing Unit ) to communicate with the FPGA through a Bus interface, and an instruction analysis module, a data encoding module and an SPI (SERIAL PERIPHERAL INTERFACE Bus, serial peripheral interface) control module are required to be implemented in the FPGA, where the instruction analysis module is used for analyzing configuration instructions and data sent by the CPU into a format acceptable by the SPI control module. The data encoding module is used for transmitting the state of the SPI control module to the CPU, wherein the state comprises the last instruction completion condition, flash erasing end and the like. The SPI control module is used for implementing specific programming action of the external Flash.

However, the existing FPGA firmware update scheme has the following problems:

(1) An off-chip processor such as a CPU is required to communicate with the FPGA, and the PCB (printed circuit board) layout area of the system is increased.

(2) The instruction analysis module, the data encoding module and the SPI control module occupy more IO resources and logic resources of the FPGA, and correspondingly reduce the resources available for user design in the FPGA.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a method and a device for updating FPGA firmware.

The technical problems to be solved by the invention are realized by the following technical scheme:

An FPGA firmware updating method is characterized in that a processor is embedded in an FPGA, and a QSPI controller and a communication interface are mounted on the processor; the FPGA is externally connected with a Flash, and FPGA firmware is stored in the Flash and comprises an FPGA configuration file and a processor program; the FPGA configuration file at least comprises first configuration information; the first configuration information is used for configuring wiring logic required by the QSPI controller and the communication interface; the processor program at least comprises a program for driving the QSPI controller to read and write the Flash by the processor;

the method comprises the following steps:

after the FPGA finishes initialization, the processor receives a firmware update instruction sent by the upper computer through the communication interface;

responding to the firmware update instruction, and driving the QSPI controller to erase the Flash by the processor;

the processor receives new FPGA firmware from the upper computer through the communication interface;

The processor drives the QSPI controller to write new FPGA firmware into the Flash;

resetting the FPGA to complete the FPGA firmware update.

Optionally, the firmware update instruction is an instruction for updating the FPGA configuration file and/or the processor program;

and the firmware updating instruction carries the FPGA configuration file and/or the storage address of the processor program in the Flash.

Optionally, the communication interface includes: UART interfaces.

Optionally, the processor includes: and (3) an MCU.

Optionally, the method further comprises:

When the processor drives the QSPI controller to erase the Flash, the processor continuously accesses a state register representing an erased state in the Flash; judging whether the erasure is completed or not according to the state of the state register; when the erasure is completed, feeding back the erasure completion to the upper computer through the communication interface; and when erasure is not completed, feeding back and waiting to the upper computer through the communication interface.

Optionally, when the processor receives new FPGA firmware from the upper computer through the communication interface, if the data sent by the upper computer includes a plurality of end characters, the processor determines that the new FPGA firmware has been received.

Optionally, the processor drives the QSPI controller to write new FPGA firmware to the Flash, including:

and the processor drives the QSPI controller to burn the new FPGA firmware into the Flash in a page writing mode.

Optionally, the method further comprises:

When the processor drives the QSPI controller to burn new FPGA firmware into the Flash in a page writing mode, the processor judges whether each page writing is finished or not by reading a control register of the Flash; when the page writing is completed each time, feeding back the page writing completion to the upper computer through the communication interface; and when the writing page is in progress, feeding back waiting to the upper computer through the communication interface.

The invention also provides an FPGA firmware updating device which is applied to the processor embedded in the FPGA;

The processor is provided with a QSPI controller and a communication interface; the FPGA is externally connected with a Flash, and FPGA firmware is stored in the Flash and comprises an FPGA configuration file and a processor program; the FPGA configuration file at least comprises first configuration information; the first configuration information is used for configuring wiring logic required by the QSPI controller and the communication interface; the processor program at least comprises a program for driving the QSPI controller to read and write the Flash by the processor;

the device comprises:

the first receiving module is used for receiving a firmware updating instruction through the communication interface after the FPGA completes initialization;

The first driving module is used for responding to the firmware updating instruction and driving the QSPI controller to erase the Flash;

the second receiving module is used for receiving new FPGA firmware through the communication interface;

the second driving module is used for driving the QSPI controller to write new FPGA firmware into the Flash;

And the resetting module is used for resetting the FPGA to finish updating the FPGA firmware.

Optionally, the firmware update instruction is an instruction for updating the FPGA configuration file and/or the processor program;

and the firmware updating instruction carries the FPGA configuration file and/or the storage address of the processor program in the Flash.

In the FPGA firmware updating method provided by the invention, a processor embedded in the FPGA receives a firmware updating instruction from an upper computer; responding to a firmware update instruction, and driving a QSPI controller to erase the external Flash by the processor; then, the processor receives new FPGA firmware from the upper computer and drives the QSPI controller to write the new FPGA firmware into Flash. And then resetting the FPGA to finish updating the FPGA firmware.

Compared with the prior art, the invention does not need to communicate with the FPGA through the off-chip processor, and reduces the PCB layout area of the system. In addition, the communication interface used for the communication between the FPGA and the upper computer is a peripheral device mounted on a processor embedded in the FPGA, and does not occupy IO resources of the FPGA; the wiring logic required by the QSPI controller and the communication interface only occupies little logic resource of the FPGA, so the invention effectively solves the problems existing in the prior art.

Drawings

FIG. 1 is a hardware structure on which the existing FPGA firmware update method is based;

fig. 2 is a hardware architecture on which the FPGA firmware updating method is based according to the embodiment of the present invention;

FIG. 3 is a flowchart of a method for updating FPGA firmware according to an embodiment of the present invention;

fig. 4 is a flowchart of another method for updating FPGA firmware according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

In order to solve the problems of the existing FPGA firmware updating method, the embodiment of the present invention provides an FPGA firmware updating method, which is applicable to an FPGA embedded with a processor, where the processor may include an MCU (Microcontroller Unit, micro control unit), but is not limited thereto.

Fig. 2 shows a hardware architecture on which the FPGA firmware updating method provided by the embodiment of the present invention is based. As shown in fig. 2, the processor embedded in the FPGA mounts a QSPI (Queued SPI, queue serial peripheral interface) controller and a communication interface, which is denoted by Com in fig. 2; the type of the communication interface is not limited, such as UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) interface, bluetooth interface, or LoRa interface. The FPGA is externally connected with a Flash, and FPGA firmware is stored in the Flash and comprises an FPGA configuration file and a processor program; the FPGA configuration file at least comprises first configuration information; the first configuration information is used for configuring wiring logic required by a QSPI controller and a communication interface (Com); the processor program at least comprises a program for driving the QSPI controller to read and write the Flash.

It should be noted that, the embodiment of the present invention occupies little FPGA resource. Taking a communication interface (Com) as a UART interface, for example, the FPGA resources occupied by the embodiment of the present invention include: the method comprises the steps of correspondingly connecting a serial port module receiving end connected with an upper computer with FPGA wiring resources of a UART interface receiving end of an FPGA, correspondingly connecting the serial port module receiving end connected with the upper computer with FPGA wiring resources of the UART interface receiving end of the FPGA, and connecting a port of a QSPI controller mounted on a processor with the FPGA wiring resources of the Flash. The above is all FPGA resources required to be occupied by the embodiment of the invention; the QSPI bus used for connecting the port of the QSPI controller mounted on the processor with the Flash is an inherent functional module in the FPGA, and does not occupy the logic resource of the FPGA.

In the embodiment of the invention, the upper computer and the processor can communicate in a wired communication mode or in a wireless communication mode. For example, the upper computer can be connected with a UART interface mounted on the processor through a wireless serial port module, so that the upper computer and the processor can communicate through a wireless serial port.

Referring to fig. 3 in conjunction with fig. 2, the method for updating FPGA firmware provided by the embodiment of the present invention includes the following steps:

s1: after the FPGA finishes initialization, the processor receives a firmware update instruction sent by the upper computer through the communication interface.

Specifically, the FPGA is provided with an FPGA configuration module, the FPGA configuration module takes an FPGA configuration file out of Flash through a QSPI bus of the FPGA in the process of powering up and initializing the FPGA, and configures the FPGA configuration file to each logic unit of the FPGA, and wiring logic to be configured of the first configuration information is contained in the logic units. The configuration information for configuring other logic resources and IO resources of the FPGA is collectively called second configuration information except for the wiring logic to be configured by the first configuration information.

Then, the FPGA configuration module reads the processor program from the Flash and writes the processor program into the processor. For example, if the processor is an MCU, the FPGA configuration module writes the MCU program into a code RAM of the MCU, which is a RAM (random access memory) for storing the MCU program. After the FPGA configuration module finishes the operation, the occupation of the FPGA configuration module on a QSPI bus is released, the reset control of all resources in the FPGA is released, and then the Flash is controlled by a processor embedded in the FPGA. Then, the processor receives a firmware update instruction sent by the upper computer through a communication interface (Com), wherein the instruction carries a storage address of the FPGA firmware in Flash.

In practical applications, the processor may determine whether a firmware update instruction is received by identifying a specific character in data sent from the host computer. For example, when the data sent by the upper computer contains CFGSTART identification characters, the processor can determine that the firmware update instruction is received, so that the next operation is performed.

S2: and responding to the firmware update instruction, and driving the QSPI controller to erase the Flash by the processor.

Because the firmware update instruction carries the storage address of the FPGA firmware in the Flash, the processor can drive the QSPI controller to erase the Flash according to the address.

Optionally, in one implementation, when the processor drives the QSPI controller to perform an erase operation on the Flash, the processor may continuously access a status register in the Flash that characterizes an erase state; judging whether the erasure is completed or not according to the state of the state register; when the erasure is completed, feeding back the erasure completion to the upper computer through a communication interface (Com); when erasure is not completed, wait is fed back to the upper computer through a communication interface (Com).

It can be understood that in practice, if the FPGA firmware occupies a larger memory space in Flash, it takes a certain time to erase the FPGA firmware, so in order to avoid starting to update the FPGA firmware without erasing, the processor may continuously access the status register of Flash, so as to feed back the erasing completion to the host computer when the erasing is completed, so that the host computer sends a new FPGA firmware after determining that the erasing is completed. The erasure completion fed back by the processor may be a specific identifier, such as CFG, although not limited thereto.

S3: the processor receives new FPGA firmware from the upper computer through the communication interface.

It will be appreciated that in practice, the new FPGA firmware will be distributed to the processor by the host computer multiple times, limited by the number of bits of the communication interface, so that the processor actually needs to receive multiple times of data, thereby receiving the new FPGA firmware entirely.

Optionally, in one implementation, when the processor receives the new FPGA firmware from the upper computer through the communication interface (Com), if the data sent from the upper computer contains a plurality of end characters, the processor determines that the new FPGA firmware has been received. Here, the END character such as END is not limited thereto.

Here, the processor does not determine that the new FPGA firmware has been received until it receives data containing multiple end characters, because the data transmitted once may also contain a single end character. Therefore, in order to distinguish the end flag of the single transmitted partial data from the end flag of the complete FPGA firmware, the embodiment of the present invention employs a plurality of end characters to represent the end flag of the complete FPGA firmware.

S4: the processor drives the QSPI controller to write new FPGA firmware into Flash.

Specifically, the processor drives the QSPI controller to write the new FPGA firmware into Flash through the QSPI interface.

Optionally, in one implementation, the processor driving the QSPI controller to write new FPGA firmware to Flash may include: the processor drives the QSPI controller to burn the new FPGA firmware into Flash in a page writing mode.

Flash contains many blocks and FPGA firmware occupies one or more blocks. Block is typically made up of many pages, the written Page being a Page Program, which is one way to write to a single Page of Flash. In practice, the Page Program also needs to take a certain time, so in one implementation manner, when the processor drives the QSPI controller to write the new FPGA firmware into Flash in a Page writing manner, the processor can also judge whether each Page writing is completed or not by reading the control register of Flash, that is, whether the current Page writing is completed or not; when the page writing is completed, the processor can also feed back the page writing completion to the upper computer through a communication interface (Com) so that the upper computer can continuously send the residual data of the new FPGA firmware; while the write page is in progress, the processor may also feed back a wait to the host computer via the communication interface (Com).

S5: resetting the FPGA to complete the FPGA firmware update.

After resetting the FPGA, the FPGA is powered on again to enter an initialization state, and the initialization process is the same as that shown in step S1, so that after the initialization is completed, the FPGA firmware in the FPGA is updated to be new FPGA firmware.

In the embodiment of the invention, the firmware update instruction sent by the upper computer can be an instruction for updating the FPGA configuration file and/or the processor program; correspondingly, the firmware update instruction carries the storage address of the FPGA configuration file and/or the processor program in Flash.

It can be understood that if the firmware update instruction sent by the upper computer carries the storage address of the FPGA configuration file in Flash, the processor correspondingly erases the FPGA configuration file stored in the FPGA file area in Flash, and the new FPGA configuration file received by the processor is written into the FPGA file area. If the firmware update instruction sent by the upper computer carries the storage address of the processor program in Flash, the processor correspondingly erases the processor program stored in the processor file area in Flash, and the new processor program received by the processor is written into the processor file area. If the firmware update instruction sent by the upper computer carries the storage address of the FPGA configuration file and the storage address of the processor program in Flash, the processor can correspondingly erase and write in the Flash according to the respective addresses.

Therefore, the embodiment of the invention can update the FPGA configuration file or the processor program independently, and can update the FPGA configuration file and the processor program simultaneously.

In a specific example, a method flow of an embodiment of the present invention is shown in fig. 4, and includes:

a. Receiving data by Com: the processor receives data sent by the upper computer through a communication interface (Com).

B. judging whether the data contains a firmware update instruction or not: the processor judges whether the received data contains a firmware update instruction or not by identifying a specific character in the data sent by the upper computer; if so, continuing to execute the step c, otherwise, returning to the step a to continue receiving the data.

C. erasing Flash: the processor drives the QSPI controller to erase the Flash.

D. Judging whether the erasure is completed: the processor judges whether the Flash is erased or not by accessing a status register of the Flash; if the erasure is completed, the step e is continued, otherwise the step d-1 is executed.

D-1, wait by Com feedback: the processor feeds back to the host computer via the communication interface (Com).

E. Receive data through Com (new FPGA firmware): the processor receives data containing new FPGA firmware sent by the upper computer through a communication interface (Com).

F. Judging whether the data contains a plurality of end characters: the processor judges whether the new FPGA firmware is received and completed according to whether the received data contains a plurality of end characters or not; if the received data contains a plurality of end characters, the received data is completely received, the step g is continuously executed, and otherwise, the step f-1 is executed.

G. Resetting the FPGA: the processor resets the FPGA, the FPGA is initialized after being powered on again, and new FPGA firmware is configured into the FPGA after the initialization is completed.

F-1, page Program, and feedback wait: the processor drives the QSPI controller to burn the new FPGA firmware into Flash in a Page Program mode, and feeds back the new FPGA firmware to the upper computer for waiting.

F2, judging whether the Page Program is finished: when the processor writes new FPGA firmware into Flash in a Page Program mode, judging whether each Page writing is finished or not by reading a control register of the Flash; when the writing page is in progress, feeding back waiting to the upper computer through a communication interface (Com), namely returning to the step f-1; and (c) feeding back the completion of page writing to the upper computer through a communication interface (Com) when the page writing is completed every time, so that the upper computer continues to receive the residual data of the new FPGA firmware, namely, returning to the step e until the new FPGA firmware is completely written into Flash.

In practical application, in the method for updating the FPGA firmware provided by the embodiment of the present invention, each method step executed by the processor may be implemented by using C language programming.

Compared with the existing FPGA firmware updating method, the embodiment of the invention does not need to communicate with the FPGA through an off-chip processor. In addition, in the embodiment of the invention, the communication interface used for the communication between the FPGA and the upper computer is a peripheral device mounted on a processor embedded in the FPGA, and does not occupy IO resources of the FPGA; the wiring logic required by the QSPI controller and the communication interface occupies only a small amount of logic resources of the FPGA. Therefore, the embodiment of the invention greatly reduces the use of IO resources and logic resources of the FPGA, simplifies the updating process, reduces the number of components on the PCB, reduces the hardware resources required while realizing the updating of the FPGA firmware, and effectively solves a plurality of problems existing in the traditional FPGA firmware updating method.

Corresponding to the FPGA firmware updating method, the embodiment of the invention also provides an FPGA firmware updating device which is applied to the embedded processor of the FPGA; the processor mounts a QSPI controller and a communication interface; the FPGA is externally connected with a Flash, and FPGA firmware is stored in the Flash and comprises an FPGA configuration file and a processor program; the FPGA configuration file at least comprises first configuration information; the first configuration information is used for configuring wiring logic required by the QSPI controller and the communication interface; the processor program at least comprises a program for driving the QSPI controller to read and write Flash by the processor;

the device comprises:

the first receiving module is used for receiving a firmware updating instruction through a communication interface after the FPGA completes initialization;

The first driving module is used for responding to the firmware updating instruction and driving the QSPI controller to erase the Flash;

the second receiving module is used for receiving new FPGA firmware through the communication interface;

the second driving module is used for driving the QSPI controller to write new FPGA firmware into Flash;

And the resetting module is used for resetting the FPGA to finish updating the FPGA firmware.

Optionally, the firmware update instruction is an instruction to update the FPGA configuration file and/or the processor program;

the firmware update instruction carries an FPGA configuration file and/or a storage address of a processor program in Flash.

Optionally, the communication interface includes: UART interfaces.

Optionally, the processor includes: and (3) an MCU.

Optionally, the apparatus further includes: a first judgment module;

The first judging module is used for continuously accessing a state register representing an erasing state in the Flash when the QSPI controller is driven to erase the Flash; judging whether the erasure is completed or not according to the state of the state register; when the erasure is completed, feeding back the erasure completion to the upper computer through the communication interface; and when erasure is not completed, feeding back waiting to the upper computer through the communication interface.

Optionally, when receiving the new FPGA firmware from the upper computer through the communication interface, if the data sent by the upper computer contains a plurality of end characters, determining that the new FPGA firmware has been received.

Optionally, the second driving module drives the QSPI controller to write new FPGA firmware into Flash, including: and driving the QSPI controller to burn the new FPGA firmware into Flash in a page writing mode.

Optionally, the apparatus further includes: a second judging module;

The second judging module is used for judging whether each page writing is finished or not by reading a control register of the Flash when the QSPI controller is driven to burn a new FPGA firmware into the Flash in a page writing mode; when the page writing is completed, feeding back the page writing completion to the upper computer through the communication interface each time; when the writing page is in progress, waiting is fed back to the upper computer through the communication interface.

It should be noted that, for the device embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and the relevant points are referred to in the description of the method embodiment.

It should be noted that the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. The implementations described in the following exemplary examples do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.

Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings and the disclosure. In the description of the present application, the word "comprising" does not exclude other elements or steps, the "a" or "an" does not exclude a plurality, and the "a" or "an" means two or more, unless specifically defined otherwise. Moreover, some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (8)

1. The FPGA firmware updating method is characterized in that a processor is embedded in the FPGA, and a QSPI controller and a communication interface are mounted on the processor; the FPGA is externally connected with a Flash, and FPGA firmware is stored in the Flash and comprises an FPGA configuration file and a processor program; the FPGA configuration file at least comprises first configuration information; the first configuration information is used for configuring wiring logic required by the QSPI controller and the communication interface; the processor program at least comprises a program for driving the QSPI controller to read and write the Flash by the processor;

the method comprises the following steps:

And (3) powering up and initializing the FPGA: an FPGA configuration module in the FPGA takes the FPGA configuration file out of the Flash through a QSPI bus of the FPGA and configures the FPGA configuration file to each logic unit of the FPGA; the wiring logic to be configured of the first configuration information is included in the respective logic units; the FPGA configuration module reads the processor program from the Flash and writes the processor program into the processor; the FPGA configuration module releases occupation of the QSPI bus after the operation is finished, and releases reset control of all resources in the FPGA so that the Flash is controlled by the processor embedded in the FPGA;

After the FPGA finishes initialization, the processor receives a firmware update instruction sent by an upper computer through the communication interface; the firmware updating instruction is an instruction for updating the FPGA configuration file and/or the processor program; the firmware updating instruction carries the FPGA configuration file and/or the storage address of the processor program in the Flash;

Responding to the firmware update instruction, and driving the QSPI controller to erase the Flash by the processor;

the processor receives new FPGA firmware from the upper computer through the communication interface;

The processor drives the QSPI controller to write new FPGA firmware into the Flash;

Resetting the FPGA to complete the FPGA firmware update.

2. The FPGA firmware updating method of claim 1, wherein said communication interface comprises: UART interfaces.

3. The FPGA firmware updating method of claim 1, wherein said processor comprises: and (3) an MCU.

4. The FPGA firmware updating method of claim 1, further comprising:

When the processor drives the QSPI controller to erase the Flash, the processor continuously accesses a state register representing an erased state in the Flash; judging whether the erasure is completed or not according to the state of the state register; when the erasure is completed, feeding back the erasure completion to the upper computer through the communication interface; and when erasure is not completed, feeding back and waiting to the upper computer through the communication interface.

5. The method according to claim 1, wherein when the processor receives new FPGA firmware from the upper computer through the communication interface, if the data sent from the upper computer contains a plurality of end characters, the processor determines that the new FPGA firmware has been received.

6. The FPGA firmware updating method of claim 1, wherein said processor driving said QSPI controller to write new FPGA firmware to said Flash comprises:

and the processor drives the QSPI controller to burn the new FPGA firmware into the Flash in a page writing mode.

7. The FPGA firmware updating method of claim 6 and further comprising:

When the processor drives the QSPI controller to burn new FPGA firmware into the Flash in a page writing mode, the processor judges whether each page writing is finished or not by reading a control register of the Flash; when the page writing is completed each time, feeding back the page writing completion to the upper computer through the communication interface; and when the writing page is in progress, feeding back waiting to the upper computer through the communication interface.

8. The FPGA firmware updating device is characterized by being applied to an embedded processor of an FPGA;

The processor is provided with a QSPI controller and a communication interface; the FPGA is externally connected with a Flash, and FPGA firmware is stored in the Flash and comprises an FPGA configuration file and a processor program; the FPGA configuration file at least comprises first configuration information; the first configuration information is used for configuring wiring logic required by the QSPI controller and the communication interface; the processor program at least comprises a program for driving the QSPI controller to read and write the Flash by the processor;

the device comprises:

The first receiving module is used for receiving a firmware updating instruction through the communication interface after the FPGA completes initialization; the firmware updating instruction is an instruction for updating the FPGA configuration file and/or the processor program; the firmware updating instruction carries the FPGA configuration file and/or the storage address of the processor program in the Flash; the power-on initialization process of the FPGA comprises the following steps: an FPGA configuration module in the FPGA takes the FPGA configuration file out of the Flash through a QSPI bus of the FPGA and configures the FPGA configuration file to each logic unit of the FPGA; the wiring logic to be configured of the first configuration information is included in the respective logic units; the FPGA configuration module reads the processor program from the Flash and writes the processor program into the processor; the FPGA configuration module releases occupation of the QSPI bus after the operation is finished, and releases reset control of all resources in the FPGA so that the Flash is controlled by the processor embedded in the FPGA;

The first driving module is used for responding to the firmware updating instruction and driving the QSPI controller to erase the Flash;

the second receiving module is used for receiving new FPGA firmware through the communication interface;

the second driving module is used for driving the QSPI controller to write new FPGA firmware into the Flash;

And the resetting module is used for resetting the FPGA to finish updating the FPGA firmware.