CN118216229A - Display panel, under-screen camera device and display device - Google Patents

Abstract

Embodiments of the present application provide a display panel including a camera area under which an image sensor is to be placed, and an under-screen camera apparatus and a display apparatus including the display panel. The display panel includes a plurality of pixels in a camera area, each pixel including an opaque area, an opening area, and a buffer area surrounding the opening area and extending between the opaque area and the opening area. The transmittance of the buffer region is higher than the transmittance of the opaque region and lower than the transmittance of the opening region.

Description

Display panel, under-screen camera device and display device

Technical Field

The present application relates generally to a display device, and more particularly to a device including a camera under a display panel.

Background

Recently, an under-screen camera (UDC) technology has been proposed, in which a camera is placed under a display panel. The UDC technology does not need to place a camera in a frame (bezel), a notch and the like of a smart phone and other devices, so that full-screen devices are realized.

An under-screen camera captures light in the scene through the display panel to generate an image. In order to realize high image quality (camera picture quality, camera PQ) using such a camera, it is necessary to increase the transmittance of the cover display panel so that each pixel of the camera can receive a sufficient amount of light. One known technique is to reduce the display resolution in the region of the camera under which the camera is placed to be lower than the display resolution in another region of the display panel. This can improve the aperture ratio of the display pixels in the camera area. However, even in the camera region, it is not preferable to significantly lower the display image quality (display picture quality, DISPLAY PQ), and therefore, it is limited to increase the aperture ratio and thus the transmittance.

Furthermore, it has been found that acceptable imaging PQ cannot be obtained by only achieving high transmittance in the camera area of the display panel. Each display pixel has a slit-like or aperture-like structure that will diffract light passing therethrough, thereby producing a diffraction image. The diffraction image may spread to multiple camera pixels and cause undesirable effects such as speckle, fog, blurring, and ghosting. Such diffraction images are very complex and are difficult to compensate by data processing in the camera circuitry. Therefore, in order to improve the imaging PQ of the under-screen camera, a technical solution for eliminating or alleviating the diffraction problem is required.

Disclosure of Invention

It is an object of an embodiment of the present application to provide a display panel having a display pixel structure capable of suppressing a diffraction image. The embodiment of the application also provides an under-screen camera device comprising the camera under the display panel and a display device.

According to a first aspect, there is provided a display panel comprising a camera area under which an image sensor is to be placed. The display panel includes a plurality of pixels in the camera area, each pixel including an opaque area, an opening area, and a buffer area surrounding the opening area and extending between the opaque area and the opening area. The transmittance of the buffer region is higher than the transmittance of the opaque region and lower than the transmittance of the opening region.

In one possible implementation of the first aspect, the buffer region may comprise one or more intermediate transmissive layers, wherein the intermediate transmissive layers may be attached to the multilayer structure, and the multilayer structure may be common to the opening region.

In another possible implementation of the first aspect, the opaque region may be embedded with a pixel circuit comprising a polysilicon thin film transistor (thin film transistor, TFT), and the one or more intermediate transmissive layers may comprise a polysilicon layer having the same thickness as the polysilicon layer of the polysilicon TFT.

In another possible implementation of the first aspect, the opaque region may include a black pixel definition layer (pixel DEFINING LAYER, PDL), and the one or more intermediate transmissive layers may include a tapered black PDL that gradually decreases in thickness toward the open region.

In another possible implementation of the first aspect, the opaque region may be embedded with a pixel circuit including a polysilicon TFT and include a black PDL; the one or more intermediate transmissive layers may include a polysilicon layer having the same thickness as the polysilicon layer of the polysilicon TFT, and a tapered black PDL gradually decreasing in thickness toward the opening region, the tapered black PDL partially overlapping the polysilicon layer in the buffer region.

In another possible implementation of the first aspect, the transmittance of the buffer region may be in a range between 30% and 70%.

In another possible implementation of the first aspect, the width of the buffer region may be in a range between 1/20 and 1/5 of the width of the opening region.

In another possible implementation of the first aspect, the opening region may define an opening having rounded corners.

In another possible implementation of the first aspect, the opening region may define a circular opening.

In another possible implementation of the first aspect, the buffer region may further comprise an opaque metal layer along its boundary with the opaque region, and the metal layer may partially overlap with the one or more intermediate transmissive layers. The metal layer may be embedded in one or more interlayer dielectric layers that are continuous across the opaque region, the impact region, and the open region. The open area may define a circular opening and the metal layer may define a circular inner periphery.

In another possible implementation of the first aspect, the display panel may further comprise a non-camera area, wherein the resolution of the camera area may be lower than the non-camera area, and/or each pixel circuit in the camera area may comprise fewer transistors than each pixel circuit in the non-camera area.

In another possible implementation manner of the first aspect, the display panel may be an Organic LIGHT EMITTING Diode (OLED) panel or a micro LIGHT EMITTING diode (μled) panel.

According to a second aspect, there is provided an under-screen camera device comprising a display panel according to the first aspect or any one of its possible implementations and an image sensor placed under a camera area of the display panel.

According to a third aspect, there is provided a display device comprising an off-screen camera device according to the second aspect.

Drawings

Fig. 1A and 1B are a schematic top view and a schematic side view, respectively, of an under-screen camera (UDC) device provided by an embodiment of the present application.

Fig. 2 is a schematic top view showing display pixels in a camera area of a display panel provided by an embodiment of the present application.

Fig. 3 shows the results of an optical simulation using a fresnel diffraction model.

Fig. 4 shows the results of an optical simulation using a fraunhofer diffraction model.

Fig. 5 is a schematic cross-sectional view showing a part of a display pixel of a display panel according to an embodiment of the present application.

Fig. 6 is a schematic cross-sectional view showing a portion of a display pixel of a display panel according to another embodiment of the present application.

Fig. 7 is a schematic cross-sectional view showing a portion of a display pixel of a display panel according to another embodiment of the present application.

Fig. 8 illustrates various buffer area patterns of a display panel provided by an embodiment of the present application.

Fig. 9 is a schematic cross-sectional view showing a portion of a display pixel of a display panel according to another embodiment of the present application, in which the buffer area pattern shown in fig. 8 (d) may be employed.

Fig. 10 is a schematic diagram of a display device according to an embodiment of the present application.

In the drawings, the same or similar elements are denoted by the same or similar reference numerals.

Detailed Description

For a better understanding of the objects, features and advantages of the embodiments of the present application, reference will be made to the following detailed description of the preferred embodiments of the application, taken in conjunction with the accompanying drawings.

In the present application, the terms "first," "second," "third," and the like are intended to distinguish between similar objects, e.g., layers, regions or structures, but do not necessarily indicate a particular order or sequence. It is to be understood that these terms are interchangeable under appropriate circumstances. The terms "comprises," "comprising," "includes," "including," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, or system that comprises a list of steps or elements is not necessarily limited to those steps or elements, but may include other steps or elements not expressly listed or inherent to such process, method, apparatus, or system. Furthermore, the articles "a" and "an" in this disclosure are intended to include one or more items, and may be used interchangeably with "one or more".

Fig. 1A and 1B are a schematic top view and a schematic side view, respectively, of an under-screen camera (UDC) device 10 provided by an embodiment of the present application.

The UDC device 10 comprises a display panel 20 and an image sensor 30 placed under the area of the display panel 20. Here, the area of the display panel 20 under which the image sensor 30 is placed is referred to as a camera area 20A, and the area of the display panel 20 under which the image sensor 30 is not located is referred to as a non-camera area 20B. An intermediate layer 40, such as an air gap or an optical coupling layer, may be disposed between the display panel 20 and the image sensor 30. The separation distance R between the display panel 20 and the image sensor 30 may be in a range between 0.5mm and 5.0mm, for example, through the intermediate layer 40.

The display panel 20 may be, but is not limited to, an Organic Light Emitting Diode (OLED) panel or a micro light emitting diode (μled) panel. The image sensor 30 may take the form of a camera module or the like, also referred to herein as a camera 30. As an example, the camera 30 may have a size of about 5mm by about 5mm, and may span a plurality of display pixels, for example, several tens pixels by several tens pixels or about 100 pixels by 100 pixels, depending on the resolution of the display panel 20.

In the display panel 20, the camera area 20A may have a structure different from that of the non-camera area 20B, so that each pixel (not shown) of the camera 30 may receive a sufficient amount of light for the underlying camera 30 to achieve acceptable image pickup PQ.

For example, the resolution of the camera region 20A is lower than that of the non-camera region 20B. As an example, the non-camera region 20B may have a resolution of 400 Pixels Per Inch (PPI), while the camera region 20A may have a resolution of 200 PPI. This reduces the ratio of the area of each pixel circuit to the area of each display pixel in the camera area 20A, so that the aperture ratio in the camera area 20A can be increased.

Alternatively or additionally, the pixel circuits in the camera area 20A may have a simpler configuration than the pixel circuits in the non-camera area 20B. As an example, the pixel circuits in the non-camera area 20B may have a 7T1C (seven transistors and one capacitor) configuration, and the pixel circuits in the camera area 20A may have a 3T1C or 2T1C configuration. This can improve the aperture ratio in the camera region 20A. Furthermore, the camera area 20A may have a passive matrix configuration instead of such an active matrix configuration.

Accordingly, the display pixels in the camera area 20A form a plurality of openings each having a certain aperture ratio, and the camera area 20A can cause diffraction phenomenon of incident light passing through the openings toward the camera 30.

Now, a display pixel structure in the camera area 20A of the display panel 20 according to an embodiment of the present application will be described in detail.

Fig. 2 is a schematic top view showing display pixels 200 in the camera area 20A of the display panel 20 provided by the embodiment of the present application. Each display pixel 200 includes: an opaque region 210 including pixel circuits, and an opening region 220 for transmitting incident light toward an underlying camera (image sensor 30 in fig. 1A and 1B). The pixel circuit in the opaque region 210 may refer to a circuit (e.g., a 3T1C or 2T1C circuit) for driving a light emitting element (e.g., OLED or μled) of a pixel, and wirings such as a gate line and a source line. The opaque region 210 surrounds the open region 220 and defines a boundary between adjacent display pixels 200.

According to an embodiment of the application, the display pixel 200 further comprises a buffer region 230 arranged along the opaque region 210. The buffer region 230 may surround the opening region 220 and extend between the opaque region 210 and the opening region 220. The transmittance of the buffer region 230 (hereinafter also referred to as "intermediate transmittance") is higher than that of the opaque region 210 and lower than that of the opening region 220.

Because the circuit elements and the metal wirings (e.g., each metal wiring has a thickness of about 300 nm) are densely arranged in the opaque region 210, the opaque region 210 may have a transmittance almost equal to zero. The opening region is a region for transmitting incident light, however, the opening region may actually have a transmittance far lower than 100% due to the presence of, for example, a polarizing plate or a polarizing film. Accordingly, the relative transmittance is considered herein, wherein the transmittance of the opaque region and the open region is 0% and 100%, respectively. In terms of relative transmittance, the transmittance of the buffer region 230 may preferably be in a range between 30% and 70%, more preferably in a range between 40% and 60%, for example, about 50%. Alternatively or additionally, the buffer region 230 may have a graded transmittance that gradually increases from the opaque region 210 side to the open region 220 side.

Providing the buffer region 230 with such intermediate transmittance may smooth out the variation in transmittance within the display pixel 200, which would otherwise be large and abrupt. Accordingly, as described below with reference to fig. 3 and 4, the buffer region 230 may serve as a buffer element preventing diffraction of incident light passing through the opening region 220.

The width Wb of the buffer area 230 may be in a range between 1/20 and 1/5 of the width Wa of the opening area 220. As can be seen from fig. 2, wa+2wb defines a distance D between adjacent opaque regions 210. When the buffer region 230 is not provided, the distance D corresponds to the width of the opening. If Wb is less than Wa/20, sufficient diffraction buffering cannot be achieved. If Wb is greater than Wa/5, the width Wa of the opening area 220 may be significantly reduced, and thus the aperture ratio of the display pixel 200 may be significantly reduced. As a preferred example, the width Wb may be about 1/10 of D.

Regarding the technical effect of the buffer region 230, optical simulation is performed using a Fresnel (Fresnel) diffraction model and a Fraunhofer (Fraunhofer) diffraction model, which are well known in the art. Fig. 3 shows simulation results using a fresnel diffraction model, which is represented by the following equation:

And compares the light intensity curve 320 in the case where the buffer region 230 is provided with the light intensity curve 310 in the case where the buffer region 230 is not provided. Fig. 4 shows simulation results using a fraunhofer diffraction model, which is represented by the following equation:

And compares the light intensity curve 420 in the case where the buffer area 230 is provided with the light intensity curve 410 in the case where the buffer area 230 is not provided.

The transmittance of the opaque region 210, the buffer region 230, and the opening region 220 was set to 0%, 50%, and 100%, respectively, for the fresnel diffraction model (fig. 3) and the fraunhofer diffraction model (fig. 4). Further, in the case where the display pixel 200 has a square shape, a distance (D in fig. 2) between adjacent and opposite opaque regions 210 (i.e., a width of an opening in the case where the buffer region 230 is not provided) is set to 100 μm, a width of the opaque region 210 is set to 50 μm, and a width of the buffer region 230 (Wb in fig. 2) is set to 10 μm. Accordingly, the pitch of the display pixels 200 is set equal to 150 μm, and the width (wa=d-2 Wb) of the opening region 220 in the case where the buffer region 230 is provided is set to 80 μm. At the bottom of fig. 3, these dimensions and transmittance are indicated as being associated with curve 310, curve 320, and the position represented by the horizontal axis.

Fig. 3 shows the light intensity on the camera surface when the distance R between the display panel 20 and the camera 3 (see equation (1) above and fig. 1B) is set to 3mm, as a function of having a period of 150 μm corresponding to the pixel pitch. It should be noted that the light intensity on the vertical axis has been normalized to a uniform incident light intensity. As shown by the arrows in fig. 3, curve 310 (without buffer region 230) has significantly high intensity peaks associated with the diffraction image, while curve 320 (with buffer region 230) significantly suppresses these peaks. This may avoid or reduce unwanted effects in the generated image, such as light spots, fog, blurring and ghosting.

Fig. 4 shows the light intensity normalized to a position (x '=y' =0) directly below the center of the opening area 220. As indicated by the arrow in fig. 4, curve 420 (with buffer region 230) indicates that the first order diffraction that appears in curve 410 (without buffer region 230) is observed to be significantly suppressed. This may also avoid or reduce unwanted effects in the generated image.

How the buffer area 230 is implemented is described below. The display panel generally has a multi-layered structure. The buffer region 230 may include one or more intermediate transmissive layers in addition to a multilayer structure that is generally common to the opening region 220. An OLED display pixel is taken as an example of a display pixel below, but the display pixel may be another type of display pixel, for example a μled display pixel.

Fig. 5 is a schematic cross-sectional view showing a part of a display pixel 500 of a display panel provided by the embodiment. As described above, the display pixel 500 includes the opaque region 210, the opening region 220, and the buffer region 230. The opaque region 210, the open region 220, and the buffer region 230 may each have a multi-layered structure formed on a substrate 510 made of, for example, glass, polyimide, or other transparent material.

The opaque region 210 is embedded with a pixel circuit including a Thin Film Transistor (TFT) and a wiring. In the example shown, the multi-layer structure of opaque region 210 includes TFT polysilicon layer 512 and interlayer dielectric layer 514, interlayer dielectric layer 516, interlayer dielectric layer 518 formed on substrate 510. The multilayer structure further includes first and second metal layers 522 and 524 embedded in the interlayer dielectric layers 514 through 518, and a third metal layer 526 formed on the interlayer dielectric layer 518. The multi-layer structure of the opaque region 210 may further include a planarization layer 528, a pixel electrode 530 as an anode electrode of the OLED, a Pixel DEFINING LAYER (PDL) 532, an Electroluminescent (EL) layer 534 of the OLED, a cathode layer 536, and a capping layer 538. The TFT polysilicon layer 512 and the first to third metal layers 522 to 526 form one or more TFTs and at least one capacitor constituting a pixel circuit.

The multi-layer structure of each of the opening region 220 and the buffer region 230 may include interlayer dielectric layers 514 through 518, planarization layer 528, PDL 532, cathode layer 536, and capping layer 538, which are continuous with the corresponding layers in the opaque region 210. These layers may be considered substantially transparent compared to opaque region 210 (particularly metal layer 522 through metal layer 526, which may have a thickness of about 300nm, for example). With respect to these substantially transparent layers, the multi-layer structure of the buffer region 230 may be common to the open region 220.

According to the present embodiment, the buffer region 230 further includes a polysilicon layer 550. In other words, the buffer region 230 in the present embodiment includes the polysilicon layer 550, wherein the polysilicon layer 550 is attached to the multi-layer structure common to the opening region 220. The polysilicon layer 550 is not a component of the pixel circuit and is therefore also referred to herein as a "redundant" polysilicon layer 550. The redundant polysilicon layer 550 may be formed on the substrate 510 in the same process and at the same time as the TFT polysilicon layer 512, and thus may have the same semiconductor composition and the same thickness as the TFT polysilicon layer 512. In addition, the redundant polysilicon layer 550 may be doped with the same dopant as the TFT channel region in the TFT polysilicon layer 512.

A typical thickness of the TFT polysilicon layer 512 may be about 50nm, and polysilicon having such a thickness may transmit 30% to 70% of light incident thereon, for example, about 50%. Accordingly, the redundant polysilicon layer 550 in the buffer region 230 may also transmit about 50% of light incident thereon. Accordingly, the buffer region 230 including the redundant polysilicon layer 550 may reach about 50% in terms of the above-described relative transmittance (wherein the transmittance of the opaque region 210 and the open region 220 is 0% and 100%, respectively). The arrows in fig. 5 schematically indicate such transmittance in three regions 210 to 230. Accordingly, the buffer region 230 including the redundant polysilicon layer 550 may perform the diffraction buffer function as described above with reference to fig. 2 to 4, and the display pixel 500 may improve the image pickup PQ of a camera (e.g., the camera 30 in fig. 1A and 1B) to be placed under the display panel.

It should be noted that the thickness of the redundant polysilicon layer 550 may be adjusted according to the desired transmittance during the polysilicon deposition step, so long as the predetermined requirements of the TFT polysilicon layer 512 are met. Further, although it is assumed herein that the semiconductor layer of the TFT is made of polysilicon, that is, the semiconductor layer of the TFT is the TFT polysilicon layer 512, the principle of the present embodiment is not limited thereto. The semiconductor layer of the TFT may serve as an intermediate transmission layer in the buffer region 230 as long as it can transmit a portion of light incident thereon.

Fig. 6 is a schematic cross-sectional view illustrating a portion of a display pixel 600 of a display panel according to another embodiment of the present application. Display pixel 600 primarily includes layers that are the same as or similar to those in display pixel 500 shown in fig. 5. These same or similar layers are denoted by the same or similar reference numerals and will not be described again here.

The opaque region 210 of the display pixel 600 includes a black Pixel Defining Layer (PDL) 632 instead of the transparent PDL 532 in fig. 5 (e.g., made of polyimide). The black PDL 632 may include, for example, polyimide containing a black pigment. In the opaque region 210, the black PDL 632 may have a constant thickness of, for example, about 1 μm to 3 μm.

The thickness of the black PDL 632 decreases in the buffer area 230, and does not exist in the opening area 220. In other words, the black PDL 632 is patterned to form a cone-shaped black PDL 655 in the buffer area 230, and is removed in the opening area 220. Therefore, the buffer area 230 in the present embodiment includes the tapered black PDL 655, wherein the tapered black PDL 655 is attached to the multi-layer structure common to the opening area 220. Patterning of the tapered black PDL 655 may be performed simultaneously in the same process as the patterning of the EL layer 534 used to define the OLED. Further, in order to prevent any damage in the EL layer 534 and the cathode layer 536 formed thereon, a smooth taper angle is conventionally formed during etching of any PDL. Thus, the tapered black PDL 655 may also have substantially the same smooth taper angle.

In display pixel 600, tapered black PDL 655 may be provided as an intermediate transmissive layer instead of the redundant polysilicon layer 550 shown in FIG. 5. More specifically, the black PDL 632 may be added with a black pigment such that it has a transmittance close to zero at a given constant thickness in the opaque region 210. The tapered black PDL 655 may then provide a smooth graded transmittance that gradually increases from near zero to 100% as the thickness decreases from the opaque region 210 side to the open region 220 side.

The tapered black PDL 655 may advantageously eliminate discontinuous transmittance changes at the boundary between the opaque region 210 and the buffer region 230, and at the boundary between the buffer region 230 and the open region 220. This may cause additional diffraction buffering compared to the redundant polysilicon layer 550 shown in fig. 5.

On the other hand, the taper angle formed during patterning of the black PLD (632, 655) may be sharp, rather than smooth, due to design limitations or process limitations of the OLED. This means that the resulting tapered black PDL 655 may not provide a sufficiently smooth and/or wide enough region of transmittance variation. An embodiment suitable for this case is described below with reference to fig. 7.

Fig. 7 is a schematic cross-sectional view illustrating a portion of a display pixel 700 of a display panel according to another embodiment of the present application. Display pixel 700 primarily includes layers that are the same or similar to those in display pixel 500 shown in fig. 5 and/or display pixel 600 shown in fig. 6. These same or similar layers are denoted by the same or similar reference numerals and will not be described again here.

The buffer region 230 of the display pixel 700 includes a tapered black PLD 755, and the tapered black PLD 755 may be formed in a manner similar to the tapered black PLD 655 shown in fig. 6. However, the tapered black PLD 755 has a relatively sharp taper angle due to design constraints such as OLED. Accordingly, the buffer region 230 of the display pixel 700 further includes a redundant polysilicon layer 750, and the redundant polysilicon layer 750 may be formed in the same manner as the redundant polysilicon layer 550 shown in fig. 5. The tapered black PDL 755 and the redundant polysilicon layer 750 may together define a buffer area 230. Accordingly, the buffer region 230 in the present embodiment includes the tapered black PDL 755 and the redundant polysilicon layer 750, wherein the redundant polysilicon layer 750 is attached to the multi-layer structure common to the opening region 220. The tapered black PDL 755 may overlap a portion of the redundant polysilicon layer 750 adjacent to the opaque region 210. It should be noted that the redundant polysilicon layer 750 need not extend over the entire buffer region 230, but may extend over a portion of the buffer region 230 adjacent to the opening region 220.

In this way, the buffer region 230 of the display pixel 700 performs a diffraction buffer function by utilizing the following two intermediate transmissive layers: a redundant polysilicon layer 750 and a tapered black PLD 755. This may also cause additional diffraction buffering compared to the case shown in fig. 5 with only the redundant polysilicon layer 550.

The embodiments shown in fig. 5-7 are all advantageous in that they utilize one or more layers present in the opaque region 210 so that one or more intermediate transmissive layers (550, 655, 750, 755) in the buffer region 230 can be formed without any additional manufacturing steps. However, the embodiments of the present application are not limited in this respect. In other embodiments, one or more additional layers not present in the opaque region 210 may be formed in the buffer region 230 as one or more intermediate transmissive layers. Such additional layer(s) are preferably disposed in the display panel or at any level(s) on the display panel below the cathode layer 536. As an example, a thin metal layer (e.g., a silver (Ag) layer) having an intermediate transmittance may be deposited on the back surface of the substrate 510 in the buffer region 230. Furthermore, such additional layer(s) may be combined with the redundant polysilicon layer and/or the tapered black PLD described above.

Various variations of the pattern of the buffer region 230 (specifically, the one or more intermediate transmissive layers) will be described below with reference to fig. 8. Fig. 8 (a) to 8 (d) show display pixels 200a to 200d, respectively, in schematic top views, the display pixels 200a to 200d being exemplary variants of the display pixel 200 shown in fig. 2. The display pixels 200a to 200d respectively include buffer regions 230a to 230d, and the buffer regions 230a to 230d are four variations of the buffer regions 230 of the display pixels 200. Although fig. 2 and 8 (a) to 8 (d) illustrate the opaque regions 210 having the same pattern, the pattern of the opaque regions 210 may vary with different implementations of the display panel. Further, the areas surrounded by the buffer areas 230a to 230d will define the opening areas 220a to 220d, respectively.

The inner circumference of the buffer area 230a shown in fig. 8 (a) is rounded or chamfered, and thus, the opening area 220a also has a rounded or chamfered corner. In general, angles complicate the diffraction phenomenon and also tend to produce strong diffraction images in one or more specific directions. The rounded buffer region 230a may alleviate such complex diffraction phenomenon.

The buffer region 230b shown in fig. 8 (b) has a more rounded inner periphery than in fig. 8 (a), thus defining a smooth boundary with the opening region 220 b. As shown in fig. 8 (c), in the ideal diffraction case, the shape of the buffer region 230c is set such that the opening region 220c defines a circular opening, which causes uniform diffraction. However, as can be seen from the open area 220a to the open area 220c, approaching a circular open area 220c comes with the cost of a reduced aperture ratio, and there is a trade-off between uniformity of diffraction and aperture ratio.

In fig. 8 (d), the buffer region 230d includes a middle transmission portion 230d-1 as a portion that partially transmits incident light. The buffer region 230d also includes an opaque portion 230d-2 extending between the intermediate transmittance portion 230d-1 and the opaque region 210. The opaque portion 230d-2 may include an additional opaque layer that partially overlaps the intermediate transmissive layer in the buffer region 230 d. Thus, the intermediate transmissive part 230d-1 may correspond to a portion of the intermediate transmissive layer having a larger extension. For example, the intermediate transmissive layer may extend over the entire buffer region 230 d.

Accordingly, the display pixel 200d includes an opening region 220d, a middle transmissive portion 230d-1, and an opaque portion 230d-2 and an opaque region 210 surrounding the middle transmissive portion 230 d-1. This may not only improve the diffraction uniformity of light passing through the opening region 220d, but may also improve the diffraction uniformity of light partially passing through the buffer region 230d (i.e., the intermediate transmission portion 230 d-1), thereby providing additional diffraction buffering. In the case of ideal diffraction uniformity, the opening region 220d defines a circular opening, and the opaque layer in the opaque portion 230d-2 defines a circular inner circumference, so that the intermediate transmissive portion 230d-1 has a circular pattern as shown in fig. 8 (d).

The intermediate transmissive layer in the buffer region 230d may be, for example, the redundant polysilicon layer 550 shown in fig. 5 or the tapered black PDL 655 shown in fig. 6.

The opaque layer in opaque portion 230d-2 may be provided by extending the pattern of black PLD 632 shown in FIG. 6 into the buffer area or by forming a redundant metal layer as described below with reference to FIG. 9.

Fig. 9 is a schematic cross-sectional view illustrating a portion of a display pixel 900 of a display panel according to another embodiment of the present application, in which the buffer region pattern shown in fig. 8 (d) may be employed. The display pixel 900 is identical to the display pixel 500 shown in fig. 5, except that the display pixel 900 includes a buffer region 230d instead of the buffer region 230 of fig. 5.

The buffer region 230d includes a redundant polysilicon layer 950, which may be the same as the redundant polysilicon layer 550 in fig. 5. Buffer region 230d also includes a redundant metal layer 970 embedded in interlayer dielectric layer 514 through interlayer dielectric layer 518. In the illustrated example, the redundant metal layer 970 is provided in the same layer as the first metal layer 522 constituting the gate electrode of the TFT or the like, but the redundant metal layer 970 may be referred to as "redundancy" because it does not constitute a component of the pixel circuit. The redundant metal layer 970 may be formed simultaneously in the same process as the first metal layer 522, i.e., without any additional manufacturing steps. It should be appreciated that the redundant metal layer 970 may be disposed in other metal layers, for example, in the second metal layer 524 or the third metal layer 526.

The redundant metal layer 970 adjoins the opaque region 210 and partially overlaps the redundant polysilicon layer 950. Although the redundant polysilicon layer 950 extends over the entire buffer area 230d in fig. 9, it may be shaped to reduce overlap with the redundant metal layer 970.

Referring now to fig. 10, a schematic diagram of a display device 1000 provided by an embodiment of the present application is shown. In some embodiments, the display device 1000 may be a battery-powered mobile device, such as a smart phone, smart watch, tablet, notebook, or the like. In other embodiments, the display device 1000 may be a device commonly connected to a mains supply, such as a television or a display, or a device commonly connected to an external battery, such as an in-vehicle display. Further, the display device 1000 may be any other device, such as a digital signage device, regardless of the type of power source.

In the example shown in fig. 10, the display device 1000 includes a processor 1010, a memory 1020, a battery 1030, a display panel 1040, and a camera 1050. As shown by the solid lines in fig. 10, the display panel 1040 may be assembled with the housing of the display device 1000 in such a manner that the front surface of the display panel 1040 is visible to a user of the display device 1000. As shown in dashed lines in fig. 10, processor 1010, memory 1020, optional battery 1030, and camera 1050 may be contained within a housing. Processor 1010, memory 1020, optional battery 1030, display panel 1040, and camera 1050 may be electrically connected to each other.

Although not shown, the display device 1000 may optionally include Radio Frequency (RF) circuitry, speakers, microphones, input devices, sensors, antennas, near field communication modules, and the like.

The processor 1010 may be used to invoke software programs and data stored in the memory 1020 and to execute the software programs to perform various functions and/or data processing of the display device 1000. The processor 1010 may include any suitable special purpose or general purpose processing device or processing unit. Further, the processor 1010 may include any suitable number of processors. For example, the processor 1010 may include one or more of the following: microprocessors, microcontrollers, application processors, central processing units (central processing unit, CPU), graphics processors (graphics processing unit, GPU), digital signal processors (DIGITAL SIGNAL processor, DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (Field Programmable GATE ARRAY, FPGA), and the like.

Memory 1020 may be used for storing software programs and data and may include any suitable medium accessible by processor 1010. Further, memory 1020 may include any suitable amount of memory. Memory 1020 may include volatile memory and/or non-volatile memory and may include, for example, random access memory (random access memory, RAM), read-only memory (ROM), and/or flash memory. It should be noted that the term "memory" as used herein may refer to mass storage that may store large amounts of data. Accordingly, the memory 1020 may also include, for example, a hard disk drive (HARD DISK DRIVE, HDD), a solid state drive (SDD), an optical disk drive, and the like.

Battery 1030 may be used to power each component of display device 1000, such as processor 1010, memory 1020, display panel 1040, and camera 1050. Processor 1010 may run a power management program or module stored in memory 1020 to control the power consumption of one or more components, as well as the charging and discharging of battery 1030. In addition to battery 1030, or in place of battery 1030, display device 1000 may have a power connector, power adapter, etc. that connects to an external power source (e.g., mains).

The display panel 1040 may be used to display various information and content, including information entered by a user and information provided to the user. The display panel 1040 may include a user input device, such as a touch screen, on at least a portion of the surface exposed from the housing.

The display panel 1040 and the camera 1050 may be, for example, the display panel 20 and the camera 30 as shown in fig. 1, respectively, and may together constitute an off-screen camera (UDC) device 10 as shown in fig. 1. Thus, camera 1050 may capture light in a scene through display panel 1040 to produce an image. Further, by employing UDC technology, the display device 1000 may be a full screen device. Further, the display panel 1040 may perform the diffraction buffer function as described above with respect to light incident on the underlying camera 1050. Thus, the camera 1050 can generate an image with reduced unwanted effects (e.g., flare, fog, blur, and ghost) due to diffraction, thereby improving the imaging PQ.

Although a few preferred embodiments of the present application have been described, those skilled in the art may make changes and modifications to these embodiments without departing from the scope of this disclosure. It is therefore intended that the following claims be interpreted to cover all such variations and modifications as fall within the scope of the disclosure.

Claims (16)

1. A display panel comprising a camera area under which an image sensor is to be placed, the display panel comprising in the camera area:

a plurality of pixels, each pixel including an opaque region, an open region, and a buffer region surrounding the open region and extending between the opaque region and the open region;

Wherein the transmittance of the buffer region is higher than the transmittance of the opaque region and lower than the transmittance of the opening region.

2. The display panel of claim 1, wherein the buffer region comprises one or more intermediate transmissive layers, wherein the intermediate transmissive layers are attached to a multilayer structure, and the multilayer structure is common to the open region.

3. The display panel of claim 2, wherein the opaque region is embedded with pixel circuitry comprising a polysilicon thin film transistor, TFT, the one or more intermediate transmissive layers comprising a polysilicon layer having the same thickness as the polysilicon layer of the polysilicon TFT.

4. The display panel of claim 2, wherein the opaque region comprises a black pixel defining layer PDL, the one or more intermediate transmissive layers comprising a tapered black PDL that tapers in thickness toward the open region.

5. The display panel according to claim 2, wherein the opaque region is embedded with a pixel circuit including a polysilicon thin film transistor TFT, and includes a black pixel defining layer PDL;

Wherein the one or more intermediate transmissive layers include a polysilicon layer having the same thickness as the polysilicon layer of the polysilicon TFT, and a tapered black PDL having a gradually decreasing thickness toward the opening region, the tapered black PDL partially overlapping the polysilicon layer in the buffer region.

6. The display panel according to any one of claims 1 to 5, wherein the transmittance of the buffer region is in a range between 30% and 70%.

7. The display panel according to any one of claims 1 to 6, wherein a width of the buffer region is in a range between 1/20 to 1/5 of a width of the opening region.

8. The display panel of any one of claims 1 to 7, wherein the opening area defines an opening having rounded corners.

9. The display panel of any one of claims 1 to 7, wherein the opening area defines a circular opening.

10. The display panel of any one of claims 1 to 9, wherein the buffer region further comprises an opaque metal layer along its boundary with the opaque region, the metal layer partially overlapping the one or more intermediate transmissive layers.

11. The display panel of claim 10, wherein the metal layer is embedded in one or more interlayer dielectric layers that are continuous across the opaque region, the buffer region, and the open region.

12. The display panel of claim 10 or 11, wherein the opening region defines a circular opening and the metal layer defines a circular inner periphery.

13. The display panel of any one of claims 1 to 12, further comprising a non-camera region, wherein the camera region has a lower resolution than the non-camera region and/or each pixel circuit in the camera region comprises fewer transistors than each pixel circuit in the non-camera region.

14. The display panel according to any one of claims 1 to 13, wherein the display panel is an organic light emitting diode, OLED, panel or a micro light emitting diode, μled, panel.

15. An under-screen camera device comprising the display panel according to any one of claims 1 to 14 and an image sensor placed under the camera area of the display panel.

16. A display device comprising the off-screen camera device of claim 15.