CN118215910A

CN118215910A - Apparatus for managing cache memory penalty and method of operating the same

Info

Publication number: CN118215910A
Application number: CN202280070752.8A
Authority: CN
Inventors: 李准祐
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2021-10-25
Filing date: 2022-07-15
Publication date: 2024-06-18

Abstract

A host for managing a storage device is disclosed. The host may include: a storage host interface configured to communicate with a storage device comprising a cache memory and a nonvolatile memory; and at least one processor. The at least one processor may be configured to: receiving information from the storage device after a device reset of the storage device indicating that the cache memory is corrupted; stopping data input/output operations to the storage device; transmitting a buffer read command to the storage device; and receiving, from the storage device, cache information related to data remaining in the cache memory without being stored in the nonvolatile memory before the device reset in response to the buffer read command.

Description

Apparatus for managing cache memory penalty and method of operating the same

Technical Field

The present disclosure relates to an apparatus for managing cache memory penalty caused by device reset and a method of operating the same. More particularly, the present disclosure relates to a host for managing storage devices, the host comprising a storage host interface configured to communicate with a storage device comprising a cache memory and a non-volatile memory, and at least one processor operably coupled with the storage host interface.

Background

The storage system may include a host and a storage device. The storage device may include a nonvolatile memory that permanently stores data. The host and the storage device may be coupled to each other through various standard interfaces including at least one of an embedded multimedia card (eMMC) interface, a Secure Digital (SD) interface, a Universal Flash Storage (UFS), a Solid State Drive (SSD), a small computer interface (SCSI), or a Serial Attached SCSI (SAS). When the storage system is used for a mobile device, the mobile device may employ eMMC or UFS using a nonvolatile type NAND flash memory.

The storage device may include an internal cache memory to increase write and read speeds. Volatile memory, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), which is faster than NAND flash memory, may be used as the cache memory according to the type of memory device.

The above information is presented merely as background information to aid in the understanding of the present disclosure. No determination is made, nor an assertion is made, as to whether any of the above may be applied to the present disclosure as prior art.

Disclosure of Invention

Technical problem

Once the storage device stores the write data in the cache memory according to the write command from the host, the storage device may report a write complete response to the host before the write data is written to the NAND flash memory. The host may use commands or requests such as refresh or synchronize the cache, explicitly requesting that data stored in the cache be written to the NAND flash memory, i.e., a cache refresh.

The cache memory used in the storage device may be volatile and cache data may be lost due to power cycling, hardware reset, or software reset of the storage device. When the host resets the storage device for various reasons, such as correcting errors occurring in the storage device or the interface, the data remaining in the cache memory of the storage device may not be reserved and thus may be lost. However, because the host has received the write completion response from the storage device, the host may determine that the data has been completely written to the NAND flash memory.

More specifically, the file system included in the host is unaware of the device reset performed in the storage drive and/or the resulting data loss in the storage device. Thus, the file system may not immediately recognize the consistency error in the storage. As the file system continues to read/write data after the coherency error occurs, the coherency error may continue to increase until the file system again accesses the data loss region of the NAND flash memory and identifies a coherency mismatch.

In the event that a cache miss in the storage results in a consistency error that is difficult for the file system to understand, the file system may be restarted by causing a kernel failure (KERNEL PANIC) within the runtime. After restart, the file system may check and recover the region where the consistency error exists by performing a file system consistency check (FSCK) before being installed. The file system may execute FSCK at mount time in a similar manner even when the file system is restarted for other reasons without identifying a consistency error. In this case, when a large amount of data has been lost, the data may be unrecoverable, resulting in loss of user data. More specifically, when a file system cannot be installed due to damage to system data in the NAND flash memory or failure of recovery of file system metadata, the file system may not be started.

Aspects of the present disclosure address at least the problems and/or disadvantages noted above and provide at least the advantages described below. Accordingly, an aspect of the present disclosure provides an apparatus for managing cache memory loss caused by device reset and a method of operating the same.

Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented embodiments.

Technical solution

According to an aspect of the present disclosure, a host for managing a storage device is provided. The host includes: a storage host interface configured to communicate with the storage device including a cache memory and a nonvolatile memory; and at least one processor operatively coupled with the storage host interface. The at least one processor may be configured to receive information indicative of a cache miss from the storage device after a device reset of the storage device. The at least one processor may be configured to suspend data input/output operations to the storage device in response to the information indicating a cache miss. The at least one processor may be configured to send a buffer read command to the storage device. The at least one processor may be configured to receive cache information from the storage device based on the buffer read command related to data remaining in the cache without being stored in the non-volatile memory prior to the device reset.

According to another aspect of the present disclosure, a storage device is provided. The storage device includes: a cache memory; a nonvolatile memory; a device interface configured to communicate with a host; and at least one processor operatively coupled with the cache memory, the non-volatile memory, and the device interface. The at least one processor may be configured to receive a reset command from the host through the device interface, and to perform a device reset in response to the reset command. The at least one processor may be configured to determine whether there is cache information related to data remaining in the cache prior to the device reset that is not stored in the non-volatile memory. The at least one processor may be configured to send information indicative of a cache miss to the host through the device interface if the cache information is present. The at least one processor may be configured to receive a read command for the cache information from the host through the device interface after sending the information indicating a cache miss. The at least one processor may be configured to send the cache information to the host through the device interface in response to the read command.

According to another aspect of the present disclosure, a method of operating a host for managing a storage device including a cache memory and a nonvolatile memory is provided. The method may include receiving information indicating a cache miss from the storage device after a device reset of the storage device. The method may include suspending data input/output operations to the storage device in response to the information indicating a cache miss. The method may include sending a buffer read command to the storage device. The method may include receiving, from the storage device, cache information related to data remaining in the cache without being stored in the non-volatile memory prior to the device reset based on the buffer read command.

According to another aspect of the present disclosure, a method of operating a storage device including a cache memory and a nonvolatile memory is provided. The method may include receiving a reset command from a host, and performing a device reset in response to the reset command. The method may include determining whether there is cache information related to data remaining in the cache but not stored in the non-volatile memory prior to the device reset. The method may include: in the presence of the cache information, information indicating a cache miss is sent to the host. The method may include receiving a read command from the host for the cache information after sending the information indicating a cache miss. The method may include sending the cache information to the host in response to the read command.

Drawings

The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating an electronic device in a network environment, in accordance with various embodiments;

FIG. 2 is a block diagram illustrating a storage system according to an embodiment of the present disclosure;

Fig. 3 is a diagram showing a message flow of a write program in a storage device according to an embodiment of the present disclosure;

fig. 4 is a diagram showing a message flow of a read program in a storage device according to an embodiment of the present disclosure;

Fig. 5 is a diagram illustrating a format of a response message according to an embodiment of the present disclosure;

fig. 6 is a block diagram showing a configuration of a storage system that manages cache memory loss according to an embodiment of the present disclosure;

FIG. 7 is a flowchart illustrating a procedure to manage cache information in a storage device according to an embodiment of the present disclosure;

FIG. 8 is a flow chart illustrating a procedure to report cache memory loss in a storage device according to an embodiment of the present disclosure;

FIG. 9 is a flowchart illustrating a procedure to manage cache memory loss in a host according to an embodiment of the present disclosure;

Fig. 10 is a diagram illustrating a message flow of a program for reporting cache information to a host by a storage device according to an embodiment of the present disclosure.

Throughout the drawings, it should be noted that the same reference numerals are used to depict the same or similar elements, features and structures.

Detailed Description

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the disclosure defined by the claims and their equivalents. It includes various specific details to aid understanding, but these are to be considered exemplary only. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and constructions may be omitted for clarity and conciseness.

The terms and words used in the following description and claims are not limited to literature meanings, but are used only by the inventors to enable clear and consistent understanding of the present disclosure. Accordingly, it will be apparent to those skilled in the art that the following descriptions of the embodiments of the present disclosure are provided for illustration only and not for the purpose of limiting the disclosure as defined by the appended claims and their equivalents.

It should be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces.

For convenience of description, terms indicating components of the storage device and the host, terms indicating messages, terms indicating information, and the like used in the present disclosure are illustratively provided. Accordingly, the embodiments of the present disclosure are not limited to the terms described below, and other terms having equivalent technical meanings may be used.

Although the present disclosure may use terms and names defined in a specific system standard for convenience of description, the present disclosure is not limited by these terms and names and may be equally applied to systems conforming to other standards.

Embodiments of the present disclosure will be described below with reference to the accompanying drawings. To avoid obscuring the subject matter of the present disclosure, detailed descriptions of well-known functions and configurations will be avoided.

Fig. 1 is a block diagram illustrating an electronic device 101 in a network environment 100 according to various embodiments.

Referring to fig. 1, an electronic device 101 in a network environment 100 may communicate with the electronic device 102 via a first network 198 (e.g., a short-range wireless communication network) or with at least one of the electronic device 104 or the server 108 via a second network 199 (e.g., a long-range wireless communication network). According to an embodiment, the electronic device 101 may communicate with the electronic device 104 via the server 108. According to an embodiment, the electronic device 101 may include a processor 120, a memory 130, an input module 150, a sound output module 155, a display module 160, an audio module 170, a sensor module 176, an interface 177, a connection 178, a haptic module 179, a camera module 180, a power management module 188, a battery 189, a communication module 190, a Subscriber Identity Module (SIM) 196, or an antenna module 197. In some embodiments, at least one of the above-described components (e.g., connection end 178) may be omitted from electronic device 101, or one or more other components may be added to electronic device 101. In some embodiments, some of the above components (e.g., sensor module 176, camera module 180, or antenna module 197) may be implemented as a single integrated component (e.g., display module 160).

The processor 120 may run, for example, software (e.g., program 140) to control at least one other component (e.g., a hardware component or a software component) of the electronic device 101 that is connected to the processor 120, and may perform various data processing or calculations. According to one embodiment, as at least part of the data processing or calculation, processor 120 may store commands or data received from another component (e.g., sensor module 176 or communication module 190) into volatile memory 132, process commands or data stored in volatile memory 132, and store the resulting data in non-volatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a Central Processing Unit (CPU) or an Application Processor (AP)) or an auxiliary processor 123 (e.g., a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), an Image Signal Processor (ISP), a sensor hub processor, or a Communication Processor (CP)) that is operatively independent of or combined with the main processor 121. For example, when the electronic device 101 comprises a main processor 121 and an auxiliary processor 123, the auxiliary processor 123 may be adapted to consume less power than the main processor 121 or to be dedicated to a particular function. The auxiliary processor 123 may be implemented separately from the main processor 121 or as part of the main processor 121.

The auxiliary processor 123 (instead of the main processor 121) may control at least some of the functions or states related to at least one of the components of the electronic device 101 (e.g., the display module 160, the sensor module 176, or the communication module 190) when the main processor 121 is in an inactive (e.g., sleep) state, or the auxiliary processor 123 may control at least some of the functions or states related to at least one of the components of the electronic device 101 (e.g., the display module 160, the sensor module 176, or the communication module 190) with the main processor 121 when the main processor 121 is in an active state (e.g., running an application). According to an embodiment, the auxiliary processor 123 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 180 or the communication module 190) functionally related to the auxiliary processor 123. According to an embodiment, the auxiliary processor 123 (e.g., a neural processing unit) may include hardware structures dedicated to artificial intelligence model processing. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, by the electronic device 101 where artificial intelligence is performed or via a separate server (e.g., server 108). The learning algorithm may include, but is not limited to, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. The artificial intelligence model may include a plurality of artificial neural network layers. The artificial neural network may be a Deep Neural Network (DNN), a Convolutional Neural Network (CNN), a Recurrent Neural Network (RNN), a boltzmann machine limited (RBM), a Deep Belief Network (DBN), a bi-directional recurrent deep neural network (BRDNN), or a deep Q network, or a combination of two or more thereof, but is not limited thereto. Additionally or alternatively, the artificial intelligence model may include software structures in addition to hardware structures.

The memory 130 may store various data used by at least one component of the electronic device 101 (e.g., the processor 120 or the sensor module 176). The various data may include, for example, software (e.g., program 140) and input data or output data for commands associated therewith. Memory 130 may include volatile memory 132 or nonvolatile memory 134.

The program 140 may be stored as software in the memory 130, and the program 140 may include, for example, an Operating System (OS) 142, middleware 144, or applications 146.

The input module 150 may receive commands or data from outside the electronic device 101 (e.g., a user) to be used by other components of the electronic device 101 (e.g., the processor 120). The input module 150 may include, for example, a microphone, a mouse, a keyboard, keys (e.g., buttons) or a digital pen (e.g., a stylus).

The sound output module 155 may output a sound signal to the outside of the electronic device 101. The sound output module 155 may include, for example, a speaker or a receiver. Speakers may be used for general purposes such as playing multimedia or playing a record. The receiver may be used to receive an incoming call. Depending on the embodiment, the receiver may be implemented separate from the speaker or as part of the speaker.

The display module 160 may visually provide information to the outside (e.g., user) of the electronic device 101. The display device 160 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling a corresponding one of the display, the hologram device, and the projector. According to an embodiment, the display module 160 may comprise a touch sensor adapted to detect a touch or a pressure sensor adapted to measure the strength of the force caused by a touch.

The audio module 170 may convert sound into electrical signals and vice versa. According to an embodiment, the audio module 170 may obtain sound via the input module 150, or output sound via the sound output module 155 or headphones of an external electronic device (e.g., the electronic device 102) that is directly (e.g., wired) or wirelessly connected to the electronic device 101.

The sensor module 176 may detect an operational state (e.g., power or temperature) of the electronic device 101 or an environmental state (e.g., a state of a user) external to the electronic device 101 and then generate an electrical signal or data value corresponding to the detected state. According to an embodiment, the sensor module 176 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an Infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

Interface 177 may support one or more specific protocols that will be used to connect electronic device 101 with an external electronic device (e.g., electronic device 102) directly (e.g., wired) or wirelessly. According to an embodiment, interface 177 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface.

The connection end 178 may include a connector via which the electronic device 101 may be physically connected with an external electronic device (e.g., the electronic device 102). According to an embodiment, the connection end 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

The haptic module 179 may convert the electrical signal into a mechanical stimulus (e.g., vibration or motion) or an electrical stimulus that may be recognized by the user via his sense of touch or kinesthetic sense. According to an embodiment, the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrostimulator.

The camera module 180 may capture still images or moving images. According to an embodiment, the camera module 180 may include one or more lenses, an image sensor, an image signal processor, or a flash.

The power management module 188 may manage power supply to the electronic device 101. According to one embodiment, the power management module 188 may be implemented as at least part of, for example, a Power Management Integrated Circuit (PMIC).

Battery 189 may power at least one component of electronic device 101. According to an embodiment, battery 189 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

The communication module 190 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 101 and an external electronic device (e.g., the electronic device 102, the electronic device 104, or the server 108) and performing communication via the established communication channel. The communication module 190 may include one or more communication processors capable of operating independently of the processor 120 (e.g., an Application Processor (AP)) and supporting direct (e.g., wired) or wireless communication. According to an embodiment, the communication module 190 may include a wireless communication module 192 (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module 194 (e.g., a Local Area Network (LAN) communication module or a Power Line Communication (PLC) module). A respective one of these communication modules may communicate with external electronic devices via a first network 198 (e.g., a short-range communication network such as bluetooth, wireless fidelity (Wi-Fi) direct, or infrared data association (IrDA)) or a second network 199 (e.g., a long-range communication network such as a conventional cellular network, a 5G network, a next-generation communication network, the internet, or a computer network (e.g., a LAN or Wide Area Network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single chip), or may be implemented as multiple components (e.g., multiple chips) separate from each other. The wireless communication module 192 may identify and authenticate the electronic device 101 in a communication network, such as the first network 198 or the second network 199, using user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the user identification module 196.

The wireless communication module 192 may support a 5G network following a 4G network as well as next generation communication technologies (e.g., new Radio (NR) access technologies). The NR access technology can support enhanced mobile broadband (eMBB), large-scale machine type communications (mMTC), or ultra-reliable low-latency communications (URLLC). The wireless communication module 192 may support a high frequency band (e.g., millimeter wave band) to achieve, for example, a high data transmission rate. The wireless communication module 192 may support various techniques for ensuring performance over a high frequency band, such as, for example, beamforming, massive multiple-input multiple-output (massive MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, or massive antennas. The wireless communication module 192 may support various requirements specified in the electronic device 101, an external electronic device (e.g., electronic device 104), or a network system (e.g., second network 199). According to an embodiment, the wireless communication module 192 may support a peak data rate (e.g., 20Gbps or greater) for implementing eMBB, a loss coverage (e.g., 164dB or less) for implementing mMTC, or a U-plane delay (e.g., 0.5ms or less, or 1ms or less round trip for each of the Downlink (DL) and Uplink (UL)) for implementing URLLC.

The antenna module 197 may transmit or receive signals or power to or from the outside of the electronic device 101 (e.g., an external electronic device). According to an embodiment, the antenna module 197 may include an antenna including a radiating element composed of a conductive material or conductive pattern formed in or on a substrate, such as a Printed Circuit Board (PCB). According to an embodiment, the antenna module 197 may include a plurality of antennas (e.g., array antennas). In this case, at least one antenna suitable for a communication scheme used in a communication network, such as the first network 198 or the second network 199, may be selected from a plurality of antennas by, for example, the communication module 190 (e.g., the wireless communication module 192). Signals or power may then be transmitted or received between the communication module 190 and the external electronic device via the selected at least one antenna. According to an embodiment, further components (e.g., a Radio Frequency Integrated Circuit (RFIC)) other than radiating elements may additionally be formed as part of the antenna module 197.

According to various embodiments, antenna module 197 may form a millimeter wave antenna module. According to an embodiment, a millimeter-wave antenna module may include a printed circuit board, a Radio Frequency Integrated Circuit (RFIC) disposed on a first surface (e.g., a bottom surface) of the printed circuit board or adjacent to the first surface and capable of supporting a specified high frequency band (e.g., a millimeter-wave band), and a plurality of antennas disposed on a second surface (e.g., a top surface or a side surface) of the printed circuit board or adjacent to the second surface and capable of transmitting or receiving signals of the specified high frequency band.

At least some of the above components may be interconnected via an inter-peripheral communication scheme (e.g., bus, general Purpose Input Output (GPIO), serial Peripheral Interface (SPI), or Mobile Industrial Processor Interface (MIPI)) and communicatively communicate signals (e.g., commands or data) therebetween.

According to an embodiment, commands or data may be sent or received between the electronic device 101 and the external electronic device 104 via the server 108 connected to the second network 199. Each of the electronic device 102 or the electronic device 104 may be the same type of device as the electronic device 101 or a different type of device from the electronic device 101. According to embodiments, all or some of the operations to be performed at the electronic device 101 may be performed at one or more of the external electronic device 102, the external electronic device 104, or the server 108. For example, if the electronic device 101 should automatically perform a function or service or should perform a function or service in response to a request from a user or another device, the electronic device 101 may request one or more external electronic devices to perform at least part of the function or service instead of or in addition to the function or service, or the electronic device 101 may request one or more external electronic devices to perform at least part of the function or service. The one or more external electronic devices that received the request may perform at least part of the requested function or service, or perform additional functions or additional services related to the request, and communicate the result of the performance to the electronic device 101. The electronic device 101 may provide the result as at least a partial reply to the request with or without further processing of the result. For this purpose, for example, cloud computing technology, distributed computing technology, mobile Edge Computing (MEC) technology, or client-server computing technology may be used. The electronic device 101 may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device 104 may include an internet of things (IoT) device. Server 108 may be an intelligent server using machine learning and/or neural networks. According to an embodiment, the external electronic device 104 or the server 108 may be included in the second network 199. The electronic device 101 may be applied to smart services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology or IoT-related technology.

Fig. 2 is a block diagram illustrating a storage system according to an embodiment of the present disclosure.

Referring to FIG. 2, a storage system 200 may include a host 202 and a storage device 210. In an embodiment of the present disclosure, the storage system 200 may be included in one of computing systems (e.g., electronic device 101) such as a personal computer, laptop, tablet, smart phone, or wearable device. In an embodiment of the present disclosure, the host 202 may be the processor 120 included in the electronic device 101. In an embodiment of the present disclosure, the storage device 210 may be the memory 130 included in the electronic device 101.

The host 202 may write data to the storage device 210 or read data stored in the storage device 210. For example, the host 202 may send a write command and write data to the storage device 210 to store the data in the storage device 210. For example, to read data stored in the storage device 210, the host 202 may send a read command to the storage device 210 and receive data from the storage device 210.

In embodiments of the present disclosure, host 202 may include a host processor (e.g., host processor 121), such as a CPU or an AP. In embodiments of the present disclosure, the host 202 may include an auxiliary processor (e.g., auxiliary processor 123), such as a GPU or a Neural Processing Unit (NPU), to assist a main processor (e.g., main processor 121).

The storage device 210 may operate under control of the host 202. In an embodiment of the present disclosure, the storage device 210 may include a device controller 214 (e.g., at least one processor) and a non-volatile memory 216. The device controller 214 may operate in response to commands received from the host 202. In an embodiment of the present disclosure, the device controller 214 may be a processor configured to receive a write command and write data from the host 202 and store the write data in the non-volatile memory 216 in response to the write command.

In embodiments of the present disclosure, the device controller 214 may receive a read command from the host 202 and read data stored in the non-volatile memory 216 in response to the read command. Subsequently, the device controller 214 may send the read data to the host 202. In embodiments of the present disclosure, non-volatile memory 216 may be, but is not limited to, a NAND flash memory device.

In embodiments of the present disclosure, host 202 may communicate with storage device 210 based on a Universal Flash Storage (UFS) interface defined by the Joint Electronic Device Engineering Council (JEDEC) standard. For example, the host 202 and the storage 210 may exchange packets in the form of UFS Protocol Information Units (UPIU). UPIU may include, but is not limited to, various types of information defined by the interface between host 202 and storage 210 (e.g., UFS interface). For ease of description, terms, commands, UPIU, or messages may be used interchangeably, and each term has the same meaning or a different meaning according to the embodiments described in the detailed description.

The storage 210 may include a cache memory 212 (also referred to as a cache) to increase write and read speeds. Cache 212 may be a temporary storage space for storage 210. The cache memory 212 may include a faster volatile memory than the NAND flash memory, such as SRAM or DRAM, as compared to the nonvolatile memory 216 to shorten access times for writing and reading. In embodiments of the present disclosure, cache 212 may be used for some implementation-specific operations, such as running memory and/or address mapping tables for device controller 214.

Cache 212 is not directly accessed by host 202 and may be a separate component of storage 210. The cache 212 may temporarily store write data for the non-volatile memory 216 and read data from the non-volatile memory 216. In embodiments of the present disclosure, cache 212 may be configured to not retain valid data during a power cycle or hardware/software reset. The host 202 may explicitly request the device controller 214 to write data stored in the cache 212 to the non-volatile memory 216 (i.e., refresh the cache) using a command such as a cache refresh or a synchronize cache.

Fig. 3 is a diagram showing a message flow of a write program in a storage device according to an embodiment of the present disclosure. As an embodiment of the present disclosure, by way of example, the storage device is shown as being configured as a UFS.

Referring to fig. 3, in operation 302, host 202 may send COMMAND UPIU as a COMMAND message to storage 210 to request storage of write data. The COMMAND UPIU may include the expected data transfer length (e.g., 241 h) of the write data (e.g., 577 bytes of data) that the host 202 wants to store in the nonvolatile memory 216, as well as the information of the write request.

In operation 304, when ready to receive write data, the storage device 210 may send a Ready To Transfer (RTT) UPIU to the host 202. In embodiments of the present disclosure, RTT UPIU may include information about the range of data that storage 210 is able to receive. In operation 306, in response to the RTT UPIU, the host 202 may send a DATA output message (e.g., DATA OUT UPIU) including at least a portion of the write DATA to the storage device 210. In embodiments of the present disclosure, the DATA OUT UPIU may include a middle portion of the write DATA, a DATA segment length (e.g., 100 h), a DATA buffer offset (e.g., 100 h), or a DATA transfer count (e.g., 100 h).

As an optional operation, at least one of operation 308, operation 310, operation 312, or operation 314 may be performed.

In operation 308, the storage device 210 may send an RTT UPIU to the host 202 indicating that it is ready to receive the next data portion. In operation 310, the host 202 may send a DATAOUT UPIU including the last portion of the write data to the storage device 210. In operation 312, the storage device 210 may send RTT UPIU to the host 202. In operation 314, the host 202 may send a DATAOUT UPIU including the first portion of the write data to the storage 210. Each of the DATA OUT UPIU in operations 306, 310, and 314 may also include at least one of a DATA segment length, a DATA buffer offset, or a DATA transfer count for the corresponding DATA portion.

Recognizing that DATA OUT UPIU of operation 314 is the last write message, in operation 316, the storage device 210 may send a RESPONSE message (e.g., RESPONSE UPIU 500) to the host 202 to end the write procedure.

Fig. 4 is a diagram showing a message flow of a read program in a storage device according to an embodiment of the present disclosure. As an embodiment of the present disclosure, by way of example, storage device 210 is shown as being configured as a UFS.

Referring to fig. 4, in operation 402, host 202 may send COMMAND UPIU as a COMMAND message to storage 210 to request read data. The COMMAND UPIU may include an expected data transfer length (e.g., 241 h) of read data (e.g., 577 bytes of data) that the host 202 wants to read from the non-volatile memory 216. In embodiments of the present disclosure, the COMMAND UPIU may include a storage location (e.g., logical block address) where data is read.

IN operation 404, the storage device 210 may send a DATA input message (e.g., DATA IN UPIU) including at least a portion (e.g., a first portion) of the requested read DATA to the host 202. As an optional operation, at least one of operations 406 or 408 may be performed. IN operation 406, the storage device 210 may send a DATA IN UPIU including a middle portion of the read DATA to the host 202. IN operation 408, the storage device 210 may send the DATA IN UPIU including the last portion of the read DATA to the host 202. Each of the DATA IN UPIU of operations 404, 406, and 408 may also include at least one of a DATA segment length, a DATA buffer offset, or a DATA transfer count for the corresponding DATA portion.

Recognizing that DATA IN UPIU of operation 408 is the last read message, the storage device 210 may send a RESPONSE message (e.g., RESPONSE UPIU 500) to the host 202 to end the read procedure at operation 410.

Storage device 210 implemented as a UFS device may support a Small Computer System Interface (SCSI) command set. For example, the COMMAND UPIU in operation 302 or 402 and/or the RESPONSE UPIU in operation 316 or 410 may include a SCSI COMMAND set.

Fig. 5 is a diagram illustrating a format of a response message according to an embodiment of the present disclosure. Although the format of REPONSE UPIU a based on the JEDEC standard available in UFS devices is shown as an example of a response message, the response message is not limited to this format. The RESPONSE UPIU 500 shown may be used in either operation 316 or operation 410.

The reference map 5,RESPONSE UPIU 500 may include a transfer type field (e.g., xx100001 b), a flag field, a Logical Unit Number (LUN) field, a task tag field, an initiator Identifier (ID)/command set type (IID/CST) field, a response field, a status field, an extra header field (EHS) length field, a device information field, a data segment length field, a remaining transfer count field, a header-to-end cyclic redundancy check (E2 ECRC) field, a sensed data length and sensed data field 505, or a data E2ECRC field.

In embodiments of the present disclosure, the sense data field 505 may be configured according to the SCSI standard. When there is a problem in processing a command in the storage device 210 or a special accident occurs in the storage device 210, the storage device 210 may include a specified error code in the sense data field 505 of the RESPONSE UPIU 500. The host 202 may identify the sensed data field 505 and perform additional necessary operations based on the error code.

In the write procedure of fig. 3, in operations 306, 310, and 314, the storage device 210 may store the write data from the host 202 in the cache 212 according to the write command and report a response message to the host 202 indicating that the write is complete (e.g., in operation 316) before all of the write data is written to the non-volatile memory 216. The host 202 may receive the response message of operation 316 from the storage device 210 and determine that the write procedure has completed. Thus, an inconsistency error may occur in the host 202.

In an embodiment to be described below, the storage device 210 may store information about data remaining in the cache memory 212 (hereinafter referred to as cache information) in a storage area (e.g., SRAM or DRAM) that is not cleared even after reset or in a partial area of the nonvolatile memory 216. When the storage device 210 recognizes that cache information is stored after a device reset, the storage device 210 may report to the host 202 the presence of cache data that has not been refreshed. The host 202 may perform consistency checking and error correction in response to the report.

Fig. 6 is a block diagram illustrating a configuration of a storage system for managing cache memory loss according to an embodiment of the present disclosure.

Referring to fig. 6, a storage system 600 may include a host 202 and a storage device 210. In an embodiment of the present disclosure, the storage device 210 may be the memory 130 included in the electronic device 101.

Host 202 may include a processor 608 and a storage host interface (I/F) 606. In an embodiment of the present disclosure, the processor 608 may be the processor 120 included in the electronic device 101, such as an AP implemented as a system on chip (SoC), or an AP chipset. The processor 608 may execute software or program modules, such as the file system 602 and the storage drive 604. Storage host I/F606 may be a block of software and/or hardware responsible for communicating with storage device 210. In embodiments of the present disclosure, storage host I/F606 may include a link layer and a physical layer.

In embodiments of the present disclosure, the processor 608 (e.g., file system 602) may be configured to organize various data (e.g., configure the various data as files) generated from applications (not shown) running on the host 202, manage the data, and store the data in the storage 210. In an embodiment of the present disclosure, the processor 608 (e.g., the storage drive 604) may be configured to drive the storage device 210. The file system 602 and storage drive 604 may be implemented, for example, in software or firmware that may be executed by the processor 608.

In embodiments of the present disclosure, the processor 608 (e.g., the storage drive 604) may manage the storage host I/F606 to communicate with the storage device 210. The processor 608 may reset and restore the storage device 210 when an error occurs in communication via the storage host I/F606 or in the storage device 210. In embodiments of the present disclosure, the processor 608 (e.g., the storage drive 604) may send a reset command to the storage device 210 via the storage host I/F606. In an embodiment of the present disclosure, when a cache miss report is received from the storage 210, the processor 608 (e.g., the storage drive 604) may obtain cache information from the storage 210 and send the cache information to the file system 602 so that the file system 602 may perform a consistency check.

In embodiments of the present disclosure, when the storage device 210 is configured to store cache information described below in an internal memory (e.g., SRAM or DRAM) of the device controller 614, the processor 608 (e.g., storage driver 604) may ensure that the cache information stored in the storage device 210 is not deleted by maintaining power supplied to the storage device 210 during a device reset of the storage device 210. In embodiments of the present disclosure, when the storage device 210 is configured to store cache information in the non-volatile memory 618 (e.g., the metadata storage area 620), the processor 608 (e.g., the storage driver 604) may not maintain power supplied to the storage device 210 during a reset of the storage device 210.

In embodiments of the present disclosure, the processor 608 (e.g., the storage driver 604) of the host 202 may remain supplying power to the storage device 210 during a device reset of the storage device 210 to ensure that cache information stored in the storage device 210 is not deleted.

When the processor 608 (e.g., file system 602) receives a report from the storage drive 604 of information about cache memory loss (e.g., cache memory information) of the storage device 210, the processor 608 may perform a consistency check on the storage device 210 and recover and correct the detected non-consistency errors in the storage device 210. In embodiments of the present disclosure, upon detecting a cache miss, the processor 608 may perform consistency checking and error correction on the file system 602 according to the OS.

The storage 210 may include a cache memory 612, a device controller 614 (e.g., at least one processor), a device I/F616, and a non-volatile memory 618. The device I/F616 may be a block of software and/or hardware responsible for communication with the host 202. In embodiments of the present disclosure, the device I/F616 may include a link layer and a physical layer.

Non-volatile memory 618 may store data from host 202 and output the stored data to host 202 under the control of device controller 614. In an embodiment of the present disclosure, non-volatile memory 618 may include a metadata storage area 620 and a user data storage area 622. Metadata storage area 620 may store metadata for firmware 614a that is run by device controller 614 of storage device 210. The user data storage area 622 may store user data in response to a write request from the host 202.

The device controller 614 may run firmware 614a responsible for device management and communication with the host 202. In an embodiment of the present disclosure, the device controller 614 may store data generated by the operation of the firmware 614a (e.g., firmware metadata) in the metadata storage area 620 or an internal memory (not shown). In an embodiment of the present disclosure, the device controller 614 may include a memory (not shown) (e.g., SRAM or DRAM (hereinafter referred to as SRAM/DRAM)) that may be used for the firmware 614a.

The cache memory 612 may share internal memory (e.g., SRAM/DRAM) used by the device controller 614, or may be configured as a separate memory. The cache memory 612 may temporarily store data to be stored in the nonvolatile memory 618 of the storage device 210, or temporarily store data read from the nonvolatile memory 618, under the control of the device controller 614.

The device controller 614 may refresh the data stored in the cache memory 612 to the non-volatile memory 618 in response to an explicit refresh request from the host 202. In an embodiment of the present disclosure, the device controller 614 may store information (hereinafter, referred to as cache information) about data (hereinafter, referred to as cache data) that remains in the cache memory 612 without being refreshed. In an embodiment of the present disclosure, the cache information may be cache information 614b stored in an internal memory of the device controller 614. To this end, the internal memory of the device controller 614 may be configured not to be cleared by the device reset. In an embodiment of the present disclosure, the cache information may be cache information 620a stored in a metadata storage area 620 of the nonvolatile memory 618.

When data stored in cache memory 612 is refreshed to non-volatile memory 618, the cache memory information may be deleted by device controller 614. In embodiments of the present disclosure, the cache information may include at least one of a start address or a data size of the write data provided from the host 202. In an embodiment of the present disclosure, device controller 614 may generate cache information including a start address and a data size obtained from a write COMMAND received by host 202 (e.g., COMMAND UPIU in operation 302) and store the cache information in metadata storage area 620 of internal memory or nonvolatile memory 618.

In embodiments of the present disclosure, the device controller 614 may perform a device reset when it receives a reset command from the host 202 via the device I/F616, or after it determines that a device reset is necessary and reports the need for a device reset to the host 202. In embodiments of the present disclosure, the device controller 614 may reset at least one of the plurality of components of the storage device 210 (e.g., the cache memory 612, the device controller 613, the device I/F616, and the non-volatile memory 618) through a device reset.

When the storage device 210 is reset, the device controller 614 may identify whether cache information is present in the metadata storage area 620 of the internal memory or nonvolatile memory 618. In the event that cache information is present, the device controller 614 may report information to the host 202 indicating that a cache miss is present (e.g., RESPONSE UPIU 500), thereby determining that a cache miss has occurred.

Fig. 7 is a flowchart illustrating a procedure of managing cache information in a storage device according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the illustrated program may be executed by the device controller 614 of the storage device 210.

Referring to FIG. 7, in operation 705, the storage device 210 may receive a write COMMAND message (e.g., a COMMAND UPIU of operation 302) from the host 202. In operation 710, the storage device 210 may receive a DATA write message (e.g., DATA OUT UPIU of operation 306, 310, or 314) including at least a portion of write DATA to be stored in the nonvolatile memory 618. The storage device 210 may temporarily store at least a portion of the write data in the cache memory 612 before it is stored in the non-volatile memory 618.

In operation 715, the storage device 210 may determine whether the data write message includes the last portion of the write data, or whether the write procedure has been completed, for example. When the last portion of the write data is received, the storage device 210 may proceed to operation 720. Otherwise, the storage device 210 may return to operation 710.

In operation 720, the storage device 210 may send a write RESPONSE message (e.g., RESPONSE UPIU of operation 316) to the host 202 to indicate that the write procedure has completed.

In operation 725, after sending the write response message, the storage device 210 may determine whether at least some of the write data (referred to as cache data) that has not been refreshed to the nonvolatile memory 618 remains in the cache memory 612. In the event that cache data is present in the cache 612, the storage device 210 may proceed to operation 730. Otherwise, the storage device 210 may end the operation.

In operation 730, the storage device 210 may generate cache information related to the write data (i.e., cache data) remaining in the cache memory 612 and store the cache information. In an embodiment of the present disclosure, the cache information may include a start address and a data size associated with the write data remaining in the cache 612. In embodiments of the present disclosure, cache information may be stored in an internal memory (e.g., SRAM or DRAM) of the device controller 614 or in a metadata storage area 620 of a non-volatile memory 618 (e.g., NAND flash). In embodiments of the present disclosure, cache information may be stored in a storage area that is not cleared, even when a device reset of storage device 210 is performed.

In operation 735, the storage device 210 may determine whether the cache data remaining in the cache memory 612 has been refreshed, i.e., whether the cache data has been stored in the non-volatile memory 618. The memory device 210 may repeat operation 735 when the cache data has not been refreshed. Conversely, when the cache data has been refreshed, the storage device 210 may delete cache information associated with the cache data in operation 740.

Fig. 8 is a flowchart illustrating a procedure of reporting cache memory loss in a storage device according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the illustrated program may be run by the device controller 614 of the storage device 210.

Referring to fig. 8, in operation 805, the storage device 210 may receive a reset command from the host 202. In embodiments of the present disclosure, the storage device 210 may determine to run a power-on reset, a hardware reset, or a software reset. In operation 810, the storage device 210 may perform a device reset according to the reset command.

After the device reset is completed, the storage device 210 may determine whether cache information is present in the designated storage area in operation 815. In an embodiment of the present disclosure, the storage device 210 may identify whether the cache information is stored in the internal memory of the device controller 614 or in the metadata storage area 620 of the non-volatile memory 618. In embodiments of the present disclosure, the cache information may include a start address and/or data size of the write data remaining in the cache 612. In the case where cache information is present, the storage device 210 may proceed to operation 820. Conversely, without cache information, the storage device 210 may end the operation.

In operation 820, the storage device 210 may send a RESPONSE message (e.g., RESPONSE UPIU 500 of fig. 5) to the host 202 to indicate the cache memory loss after the device has been reset. In embodiments of the present disclosure, the response message may be a status message or a data message sent in accordance with a status request message (e.g., a TUR UPIU or SCSI READ command) from the host 202. Specific examples will be described below.

In an embodiment of the present disclosure, after a device reset, host 202 may download boot code from storage 210. For example, the host 202 may send a TEST UNIT READY (TUR) UPIU to the storage device 210. The storage 210 may send a status message in response to the turupiu. The host 202 may determine whether a boot Logical Unit (LU) or a boot-aware LU of the storage 210 is available based on the status information included in the status message.

When a boot LU is available, the host 202 may send a SCSI READ command to the storage 210. In embodiments of the present disclosure, the SCSI READ command may correspond to a boot LU. The storage device 210 may send data messages and status messages to the host 210 in response to SCSI READ commands.

In embodiments of the present disclosure, the storage device 210 may include information in a data message or status message sent to the host 210 indicating that cache information is stored or that the storage device 210 has a cache miss after a device reset.

In embodiments of the present disclosure, the storage device 210 may include a specified value, e.g., a value (e.g., 06 h) that indicates that the storage device 210 has been reset in a sense data field (e.g., sense data field 505) of a RESPONSE message (e.g., RESPONSE UPIU 500 of fig. 5) sent to the host 210, and an additional sense code/additional sense code qualifier (ASC/ASCQ) is included in the sense data field 505. In embodiments of the present disclosure, the ASC may include information about errors reported by the sense key field. In embodiments of the present disclosure, the ASCQ may indicate detailed information related to the additional sensing code. In embodiments of the present disclosure, the storage device 210 may report the cache miss to the host 202 by setting a given value in the ASC/ASCQ field of the response message transmitted to the host 210 indicating that there is a cache miss.

Table 1 below shows values set in the sense key field.

TABLE 1

In operation 825, the storage device 210 may receive a read COMMAND message (e.g., COMMAND UPIU of operation 402) from the host 202 requesting cache information. In embodiments of the present disclosure, the read command message may include information of a read request related to the cache information. In embodiments of the present disclosure, the information of the read request included in the read command message may be related to the internal memory of the device controller 614 or the nonvolatile memory 618. In embodiments of the present disclosure, the read command message may include information of the read buffer command.

In operation 830, the storage device 210 may send the cache information to the host 202 in response to the read command message. IN embodiments of the present disclosure, the cache information may be included IN a DATA input message (e.g., DATA IN UPIU of operation 404, operation 406, or operation 408) corresponding to the read command message and sent to the host 202.

Fig. 9 is a flowchart illustrating a procedure for managing cache memory loss in a host according to an embodiment of the present disclosure. In one embodiment of the present disclosure, the illustrated program may be executed by the processor 608 (e.g., storage drive 604) of the host 202.

Referring to fig. 9, in operation 905, the host 202 may recognize that an error has occurred in an interface between the host 202 and the storage device 210 or in the storage device 210. In embodiments of the present disclosure, the host 202 may determine that a device reset of the storage device 210 is required based on the occurrence of an error.

In operation 910, the host 202 may reset the storage device 210. In embodiments of the present disclosure, the host 202 may cause the storage device 210 to reset by sending a reset command to the storage device 210. In embodiments of the present disclosure, the processor 608 (e.g., the storage driver 604) of the host 202 may maintain power supplied to the storage device 210 during a device reset of the storage device 210 to ensure that cache information stored in the cache is not deleted.

In operation 915, the host 202 may send a status request message (e.g., a TUR UPIU or SCSI READ command) to the storage device 210 according to the device reset of the storage device 210, and receive a RESPONSE message (e.g., RESPONSE UPIU 500 of FIG. 5) corresponding to the status request message from the storage device 210.

In operation 920, the host 202 may determine whether information indicating a cache miss in the storage 210 (e.g., ASC/ASCQ in the sense data field 505) is included in the response message. When information indicating a cache miss is not included, the host 202 may perform a data input/output (I/O) operation (e.g., the write program of fig. 3 and the read program of fig. 4) on the storage device 210 in operation 950. Conversely, when information indicating a cache miss is included, such as when the ASC/ASCQ in the sense data field 505 is set to a predetermined value, the host 202 may proceed to operation 925.

In operation 925, the host 202 may suspend data I/O operations for the storage device 210. In embodiments of the present disclosure, the processor 608 (e.g., storage drive 604) of the host 202 may hold data write and/or read requests from the file system 602 or request the file system 602 to suspend writing and/or reading data.

In operation 930, host 202 may send a read COMMAND message (e.g., COMMAND UPIU in operation 402) to storage 210 requesting cache information related to the cache miss. In embodiments of the present disclosure, the read command message may include information of a read request (e.g., a read buffer command) related to the cache information. In embodiments of the present disclosure, the information of the read request included in the read command message may be related to the internal memory of the device controller 614 or the nonvolatile memory 618.

IN operation 935, the host 202 may receive a DATA input message (e.g., DATA IN UPIU IN operation 404, operation 406, or operation 408 of fig. 4) including the cache information from the storage device 210. In an embodiment of the present disclosure, the cache information may include a start address and a data size associated with write data that the host 202 has requested to write but has not yet been stored in the non-volatile memory 618 of the storage device 210.

In operation 940, the host 202 may perform consistency error detection, error correction, and recovery by performing a consistency check on the storage 210 based on the cache information. In embodiments of the present disclosure, the processor 608 (e.g., the storage drive 604) of the host 202 may provide the file system 602 with cache information obtained from the storage 210, and the processor 608 (e.g., the file system 602) may perform a consistency check based on the cache information. In an embodiment of the present disclosure, the processor 608 (e.g., the storage drive 604) may send information to the file system 602 indicating a device reset and/or cache miss for the storage device 210 along with the cache information.

In embodiments of the present disclosure, the coherency checks may include detecting a coherency error at a start address indicated by the cache information, and correcting and recovering the error. Since the specific details of the consistency check are not related to the embodiments of the present disclosure, a detailed description thereof will be omitted. In an embodiment of the present disclosure, the processor 608 (e.g., the file system 602) may inform the storage drive 604 that error correction and recovery according to the consistency check has been completed.

In operation 945, the host 202 may determine whether error recovery has been completed through a consistency check. In an embodiment of the present disclosure, the processor 608 (e.g., storage drive 604) of the host 202 may identify whether a signal indicating that error recovery is complete has been received from the file system 602. When the error check has not been completed, the processor 608 may return to operation 945. Conversely, when the error checking has been completed, the processor 608 may perform operation 950.

In operation 950, the host 202 may resume data I/O operations (e.g., the write program of FIG. 3 or the read program of FIG. 4) for the storage device 210. In embodiments of the present disclosure, the processor 608 (e.g., storage drive 604) of the host 202 may again process pending data write and/or read requests or request the file system 602 to resume writing and/or reading data.

Fig. 10 is a diagram illustrating a message flow of a program for reporting cache information to a host by a storage device according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the illustrated program may correspond to operation 830 or operation 935.

Referring to fig. 10, in operation 1002, host 202 may send COMMAND UPIU to storage 210 as a COMMAND message requesting information related to cache memory loss (e.g., cache memory information) stored in storage 210. In an embodiment of the present disclosure, the COMMAND UPIU may be a SCSI-based read buffer COMMAND for reading cache information stored in the storage device 210, and the read buffer COMMAND may include information indicating a buffer read (e.g., 0x3 c). In an embodiment of the present disclosure, the COMMAND UPIU may include information about the storage area in which cache information is stored in storage 210.

IN operation 1004, the storage device 210 may send a DATA input message (e.g., DATA IN UPIU) including the requested cache information to the host 202. In embodiments of the present disclosure, cache information may be communicated to host 202 via at least one data input message. In embodiments of the present disclosure, the cache information may include a start address and/or a data size. The start address and/or data size may be related to write data that the host has requested to write but has not yet been stored in the non-volatile memory 618 of the storage device 210.

In operation 1006, the storage device 210 may send a read RESPONSE message (e.g., RESPONSE UPIU 500) to the host 202, thereby completing the procedure of sending the cache information.

The apparatus and the operating method thereof according to the embodiments of the present disclosure may reduce consistency errors in a host caused by a reset of a storage device.

An apparatus and method of operation thereof according to embodiments of the present disclosure may enable a computer to immediately perform coherency checks and error correction upon occurrence of a cache miss. Accordingly, consistency errors and user data loss can be reduced, and installation failure or boot failure caused by file system failure (panic) or metadata corruption can be prevented.

According to an embodiment of the present disclosure, a host 202 for managing a storage device 210 may include a storage host interface 606 configured to communicate with the storage device 210 including a cache memory 612 and a non-volatile memory 618, and a processor 608 operatively coupled with the storage host interface. The processor may be configured to receive information indicating a cache miss from the storage device after a device reset of the storage device. The processor may be configured to suspend data input/output operations for the storage device in response to information indicating a cache miss. The processor may be configured to send a buffer read command to the storage device. The at least one processor may be configured to receive, from the storage device, cache information related to data remaining in the cache prior to the device reset and not stored in the non-volatile memory based on the buffer read command.

According to an embodiment of the present disclosure, the processor may be configured to identify an occurrence of an error associated with the storage device, send a reset command indicating a reset of the device to the storage device through the storage host interface according to the identification of the occurrence of the error, and wait to receive information indicating a cache miss from the storage device after sending the reset command.

According to embodiments of the present disclosure, the cache information may include a start address and/or a data size associated with the data remaining in the cache.

According to an embodiment of the present disclosure, a processor may be configured to perform a consistency check on a storage based on cache information.

According to an embodiment of the present disclosure, the processor may be configured to maintain power supplied to the storage device during a device reset of the storage device.

According to an embodiment of the present disclosure, the processor may be configured to send a status request message to the storage device after the device resets, and to receive a response message including information indicating a cache miss from the storage device in response to the status request message. The information indicating the cache miss may be a sense key field and an ASC/ASCQ included in a sense data field in the response message.

According to an embodiment of the present disclosure, the storage device 210 may include a cache memory 612, a non-volatile memory 618, a device interface 616 configured to communicate with the host 202, and a device controller 614 operatively coupled to the cache memory, the non-volatile memory, and the device interface. The device controller may be configured to receive a reset command from the host through the device interface. The device controller may be configured to perform a device reset in response to the reset command. The device controller may be configured to determine whether there is cache information related to data remaining in the cache but not stored in the non-volatile memory prior to the device reset. The device controller may be configured to send information indicative of cache loss to the host over the device interface in the presence of cache information. The device controller may be configured to receive a read command for cache information from the host over the device interface after sending the information indicating the cache miss. The device controller may be configured to send the cache information to the host over the device interface in response to the read command.

According to an embodiment of the present disclosure, a device controller may be configured to receive a write command from a host through a device interface, receive at least a portion of write data corresponding to the write command from the host, send a write response message to the host indicating that a write procedure of the write data is complete, determine whether at least some data, among the write data, that is not refreshed to a non-volatile memory remains in a cache memory, store cache information related to the write data when at least some data remains in the cache memory, and delete the cache information when at least some data is refreshed to the non-volatile memory.

According to embodiments of the present disclosure, cache information may be stored in a metadata storage area of an internal memory or a nonvolatile memory of a device controller.

According to embodiments of the present disclosure, the internal memory of the device controller may be configured such that cache information is not deleted by a device reset of the storage device.

According to an embodiment of the present disclosure, the device controller may be configured to send information indicating a cache loss to the host in a response message corresponding to a command message received from the host after the device reset. The information indicating the cache miss may be a sense key field and an ASC/ASCQ included in a sense data field in the response message.

According to an embodiment of the present disclosure, a method of operating a host 202 for managing a storage device 210 including a cache memory 612 and a nonvolatile memory 618 may include receiving information indicating a cache miss from the storage device after a device reset of the storage device in operations 915 and 920. The method may include: in operation 925, data input/output operations for the storage device are suspended in response to the information indicating the cache miss. The method may include: a buffer read command is sent to the storage device in operation 930. The method may include: in operation 935, cache information relating to data remaining in the cache but not stored in the non-volatile memory prior to the device reset is received from the storage device based on the buffer read command.

According to an embodiment of the present disclosure, the method may further include: the method includes identifying an occurrence of an error associated with a storage device, transmitting a reset command to the storage device indicating a reset of the device based on the identification of the occurrence of the error, and waiting to receive information indicating a cache miss from the storage device after transmitting the reset command.

According to an embodiment of the present disclosure, the method may further include: in operation 940, a consistency check is performed on the storage based on the cache information.

According to an embodiment of the present disclosure, the method may further include maintaining power supplied to the storage device during a device reset of the storage device.

According to an embodiment of the present disclosure, receiving information indicating a cache miss may include transmitting a status request message to a storage device after a device reset, and receiving a response message including the information indicating the cache miss from the storage device in response to the status request message. The information indicating the cache miss may be a sense key field and an ASC/ASCQ included in a sense data field in the response message.

According to an embodiment of the present disclosure, a method of operating a storage device 210 including a cache memory 612 and a non-volatile memory 618 may include: in operation 805, a reset command is received from a host. The method may include: in operation 810, a device reset is performed in response to a reset command. The method may include: in operation 815, it is determined whether there is cache information related to data remaining in the cache but not stored in the non-volatile memory prior to the device reset. The method may include: in operation 820, in the presence of cache information, information indicating a cache miss is sent to the host. The method may include: in operation 825, after sending information indicating a cache miss, a read command for the cache information is received from the host. The method may include: in operation 830, cache information is sent to the host in response to the read command.

According to an embodiment of the present disclosure, the method may further include: in operation 705, receiving a write command from a host; in operation 710, at least a portion of write data corresponding to a write command is received from a host; transmitting a write response message indicating that a write procedure for writing data is completed to the host in operation 720; in operation 725, it is determined whether at least some of the write data that is not refreshed to the non-volatile memory remains in the cache; when at least some data remains in the cache memory, in operation 730, cache information related to the write data is stored; and deleting the cache information in operation 740 when at least some of the data is refreshed to the non-volatile memory.

According to embodiments of the present disclosure, cache information may be stored in a metadata storage area of an internal memory or a nonvolatile memory of a storage device.

According to embodiments of the present disclosure, the internal memory may be configured such that cache information is not deleted by a device reset of the storage device.

According to an embodiment of the present disclosure, reporting information indicative of cache memory loss may include: after the device resets, information indicating a cache miss is sent to the host in a response message corresponding to the command message received from the host. The information indicating the cache miss may be a sense key field and an ASC/ASCQ included in a sense data field in the response message.

The electronic device according to various embodiments of the present disclosure may be one of various types of electronic devices. The electronic device may include, for example, a computer device, a portable communication device (e.g., a smart phone), a portable multimedia device, a portable medical device, a camera, a wearable device, or a household appliance. According to the embodiments of the present disclosure, the electronic device is not limited to those described above.

It should be understood that the various embodiments of the disclosure and the terminology used therein are not intended to limit the technical features set forth herein to the particular embodiments, but rather include various modifications, equivalents or alternatives to the respective embodiments. For the description of the drawings, like reference numerals may be used to refer to like or related elements. It will be understood that a noun in the singular corresponding to an item may include one or more things unless the context clearly indicates otherwise. As used herein, each of the phrases such as "a or B", "at least one of a and B", "at least one of a or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may include any or all possible combinations of the items listed with the corresponding one of the plurality of phrases. As used herein, terms such as "1 st" and "2 nd" or "first" and "second" may be used to simply distinguish a corresponding component from another component and not to limit the component in other respects (e.g., importance or order). It will be understood that if an element (e.g., a first element) is referred to as being "coupled to," "connected to," or "connected to" another element (e.g., a second element) with or without the use of the terms "operatively" or "communicatively," it can be directly (e.g., wired) connected to the other element, wirelessly connected to the other element, or connected to the other element via a third element.

As used in various embodiments of the present disclosure, the term "module" may include units implemented in hardware, software, or firmware, and may be used interchangeably with other terms (e.g., logic blocks, portions, or circuitry). A module may be a single integrated component adapted to perform one or more functions or a minimal unit or portion of the single integrated component. For example, according to an embodiment, a module may be implemented in the form of an Application Specific Integrated Circuit (ASIC).

Various embodiments of the disclosure set forth herein may be implemented as software (e.g., program 140) comprising one or more instructions stored in a storage medium (e.g., internal memory 136 or external memory 138) readable by a machine (e.g., electronic device 101). For example, under control of a processor, a processor (e.g., processor 120) of a machine (e.g., electronic device 101) may invoke and execute at least one of one or more instructions stored in a storage medium with or without the use of one or more other components. This enables the machine to operate to perform at least one function in accordance with the at least one instruction invoked. The one or more instructions may include code generated by a compiler or code capable of being executed by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Wherein the term "non-transitory" merely means that the storage medium is a tangible device and does not include a signal (e.g., electromagnetic waves), but the term does not distinguish between data being semi-permanently stored in the storage medium and data being temporarily stored in the storage medium.

According to embodiments, methods according to embodiments of the present disclosure may be included and provided in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disk read only memory (CD-ROM)), or may be distributed (e.g., downloaded or uploaded) online via an application Store (e.g., play Store ^TM), or may be distributed (e.g., downloaded or uploaded) directly between two user devices (e.g., smartphones). At least a portion of the computer program product may be temporarily generated if published online, or may be at least temporarily stored in a machine-readable storage medium, such as a memory of a manufacturer's server, an application store's server, or a forwarding server.

According to various embodiments, each of the above-described components (e.g., modules or programs) may include a single entity or multiple entities. Depending on the embodiment, one or more of the above components may be omitted, or one or more other components may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as a corresponding one of the plurality of components performed the one or more functions prior to integration. According to embodiments, operations performed by a module, a program, or another component may be performed sequentially, in parallel, repeatedly, or in a heuristic manner, or one or more of the operations may be performed in a different order or omitted, or one or more other operations may be added.

While the present disclosure has been shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A host for managing a storage device, the host comprising:

a storage host interface configured to communicate with the storage device including a cache memory and a nonvolatile memory; and

At least one processor operatively coupled with the storage host interface,

Wherein the at least one processor is configured to:

Information indicating a cache miss is received from the storage device after a device reset of the storage device,

In response to the information indicating a cache miss, suspending data input/output operations to the storage device,

Transmitting a buffer read command to the memory device, and

Cache information relating to data remaining in the cache memory but not stored in the nonvolatile memory prior to the device reset is received from the storage device based on the buffer read command.

2. The host of claim 1, wherein the at least one processor is further configured to:

identifying an occurrence of an error associated with the storage device;

According to the occurrence of the error is identified, a reset command indicating the device to reset is sent to the storage device through the storage host interface; and

After sending the reset command, waiting to receive the information from the storage device indicating the cache miss.

3. The host of claim 1, wherein the cache information includes a start address and/or a data size associated with data remaining in the cache.

4. The host of claim 1, wherein the at least one processor is further configured to perform a consistency check on the storage based on the cache information.

5. The host of claim 1, wherein the at least one processor is further configured to maintain power supplied to the storage device during the device reset of the storage device.

6. The host machine according to claim 1,

Wherein the at least one processor is further configured to:

After the device resets, sending a status request message to the storage device, and

Receiving a response message including the information indicating the cache memory loss from the storage device in response to the status request message, and

Wherein the information indicating the cache miss is a sense key field and an additional sense code/additional sense code qualifier (ASC/ASCQ) included in a sense data field in the response message.

7. A storage device, the storage device comprising:

a cache memory;

A nonvolatile memory;

a device interface configured to communicate with a host; and

At least one processor operatively coupled with the cache memory, the non-volatile memory, and the device interface,

Wherein the at least one processor is configured to:

receiving a reset command from the host through the device interface;

performing a device reset in response to the reset command,

Determining whether there is cache information related to data remaining in the cache prior to the device reset that was not stored in the non-volatile memory,

In the presence of the cache information, sending information indicative of cache loss to the host via the device interface,

After sending the information indicating a cache miss, receiving a read command for the cache information from the host through the device interface, and

The cache information is sent to the host through the device interface in response to the read command.

8. The storage device of claim 7, wherein the cache information includes a start address and/or a data size associated with data remaining in the cache.

9. The storage device of claim 7, wherein the at least one processor is further configured to:

Receiving a write command from the host through the device interface;

receiving at least a portion of write data corresponding to the write command from the host;

transmitting a write response message to the host indicating that a write procedure of the write data is completed;

Determining whether at least some of the write data that is not refreshed to the non-volatile memory remains in the cache;

Storing the cache information related to the write data when the at least some data remains in the cache; and

The cache information is deleted when the at least some data is refreshed to the non-volatile memory.

10. The storage device of claim 7, wherein the cache information is stored in an internal memory of the at least one processor or a metadata storage area of the non-volatile memory.

11. A method of operating a host for managing a storage device comprising a cache memory and a non-volatile memory, the method comprising:

receiving information indicating a cache miss from the storage device after a device reset of the storage device;

Suspending data input/output operations to the storage device in response to the information indicating a cache miss;

transmitting a buffer read command to the storage device; and

12. The method of claim 11, the method further comprising:

identifying an occurrence of an error associated with the storage device;

According to the occurrence of the error is identified, a reset command indicating the device to be reset is sent to the storage device; and

13. The method of claim 11, wherein the cache information includes a start address and/or a data size associated with data remaining in the cache.

14. A method of operating a storage device comprising a cache memory and a non-volatile memory, the method comprising:

receiving a reset command from a host;

performing a device reset in response to the reset command;

Determining whether there is cache information related to data remaining in the cache but not stored in the non-volatile memory prior to the device reset;

Transmitting information indicating a cache miss to the host in the presence of the cache information;

Receiving a read command for the cache information from the host after sending the information indicating a cache miss; and

The cache information is sent to the host in response to the read command.

15. The method of claim 14, wherein the cache information includes a start address and/or a data size associated with data remaining in the cache.