CN118199605A - Capacitance detection circuit, detection method, detection chip and detection device - Google Patents

Abstract

The application relates to the technical field of capacitance detection, in particular to a capacitance detection circuit, a detection method, a detection chip and a detection device. When a user touches, the capacitance Cx to be detected at the capacitance detection end changes in size. In the capacitance detection circuit provided by the application, based on the constant current source charging principle, the voltage in the charging and discharging process of the capacitance Cx to be detected is respectively compared with the high turnover voltage and the low turnover voltage of the first trigger, the second driving signal is output, the first driving signal and the second driving signal are subjected to exclusive OR operation to obtain the first charging driving signal, and the first charging driving signal is used for charging the integrating capacitance Cs, so that the capacitance value of the capacitance Cx to be detected is converted into the time for charging the integrating capacitance. Therefore, fewer peripheral elements are used, the effect of detecting capacitance change is achieved, the complexity of the system is reduced, and the accuracy of a detection result is improved.

Description

Capacitance detection circuit, detection method, detection chip and detection device

Technical Field

The application relates to the technical field of capacitance detection, in particular to a capacitance detection circuit, a detection method, a detection chip and a detection device.

Background

The capacitive sensor is a conversion device for converting a measured physical quantity or mechanical quantity into a capacitance change, and is widely applied to the fields of industrial and consumer electronics products due to the advantages of simple structure, stable performance, high sensitivity, long service life and the like, such as: pressure, displacement, acceleration, thickness, liquid level, etc. Capacitive touch screens or keys and the like are widely applied to electronic products because of good performance and long service life.

Parasitic capacitance exists between the sensing electrode of the capacitive sensor and the ground, for the capacitive sensor with a self-capacitance structure, the self-capacitance is only provided with one polar plate, and an inherent parasitic capacitance is formed between the polar plate and the ground, so that when a finger approaches the sensor, a capacitance variation is generated, and further whether touch operation exists or not can be determined according to the capacitance variation.

However, in the existing capacitive detection scheme, many peripheral elements are required for capacitive detection, and the detection process is complex.

Disclosure of Invention

The embodiment of the application provides a capacitance detection circuit, a detection method, a detection chip and a detection device.

In a first aspect, an embodiment of the present application provides a capacitance detection circuit, applied to a capacitance detection device, including: the device comprises a capacitor unit to be tested, an operation unit and an integration unit, wherein the capacitor unit to be tested is used for outputting a first control signal according to a first driving signal; an operation unit for determining a first charging drive signal supplied to the integration power supply according to the first drive signal and the first control signal; and the integrating unit is used for generating an integrated voltage according to the first charging driving signal and the charging frequency threshold value provided by the operation unit.

It can be understood that, when the user performs a touch operation, the capacitance Cx to be measured at the capacitance detecting end changes in size. In the capacitance detection circuit provided by the application, based on the constant current source charging principle, the voltage in the charging and discharging process of the capacitance Cx to be detected is respectively compared with the high turnover voltage and the low turnover voltage of the first trigger, the first control signal is output, the first driving signal and the first control signal are subjected to exclusive OR operation to obtain the first charging driving signal, and the first charging driving signal is used for charging the integrating capacitance Cs, so that the capacitance value of the capacitance Cx to be detected is converted into the time for charging the integrating capacitance, fewer peripheral elements are used, the effect of detecting the capacitance change is also achieved, and the complexity of the detection process is reduced.

In a possible implementation of the first aspect, the data processing unit is configured to perform quantization processing on the integrated voltage; and determining whether the capacitance variation to be measured corresponds to the touch operation result of the user based on the quantization result.

In a possible implementation of the first aspect, the method further includes: the capacitor unit to be tested at least comprises a capacitor to be tested, a first charge-discharge unit and a first trigger, wherein: the first charge-discharge unit is used for charging and discharging the capacitor to be tested according to the first driving signal; the first trigger is used for outputting a first control signal to the operation unit according to the input voltage at two ends of the capacitor to be detected; wherein the first flip-flop is a schmitt trigger.

In a possible implementation manner of the first aspect, the operation unit includes at least a first operator, where the first operator is an exclusive-or operator; the first operator processes the first drive signal and the first control signal to determine a first charge drive signal to be supplied to the integration power supply.

In a possible implementation of the first aspect, the first driving signal includes a first target driving signal and a second target driving signal, including: when the first driving signal is a first target driving signal, the capacitor unit to be tested charges the capacitor to be tested; when the first driving signal is a second target driving signal, the capacitor unit to be tested discharges the capacitor to be tested; wherein the first target drive signal and the second target drive signal are inverse signals.

In a possible implementation of the first aspect, the first charging drive signal includes a first target charging drive signal and a second target charging drive signal, wherein: when the first charging driving signal is a first target charging driving signal, the integration unit generates an integration voltage; when the first charging driving signal is the second target charging driving signal, no integrated voltage is generated any more and the voltage value of the integrated capacitor is kept unchanged; the first target charging driving signal and the second target charging driving signal are inverted signals.

In a possible implementation of the first aspect, the threshold number of charges is used to limit the number of times the integration unit charges the integration capacitor; when the number of times of the integration unit charging the integration capacitor reaches a threshold value of the number of times of the integration capacitor, the integration unit no longer charges the integration capacitor.

In a possible implementation of the first aspect, the circuit further includes: a reference capacitance unit; the reference capacitor unit is used for outputting a second control signal according to a second driving signal; wherein the first driving signal and the second driving signal are the same driving signal; or the first drive signal and the second drive signal are different drive signals.

In a possible implementation of the first aspect, the arithmetic unit further includes at least a second arithmetic unit and a third arithmetic unit.

In a possible implementation manner of the first aspect, the reference capacitor unit includes at least a reference capacitor, a second charge-discharge unit, and a second trigger, and includes: the second charge-discharge unit is used for charging and discharging the reference capacitor according to a second driving signal; the second trigger is used for outputting a second control signal to the second arithmetic unit according to the input voltage of the two ends of the reference capacitor; wherein the second flip-flop is a schmitt trigger.

In a possible implementation of the first aspect, the second driving signal includes a third target driving signal and a fourth target driving signal, including: when the second driving signal is a third target driving signal, the second charging and discharging unit charges the reference capacitor; when the second driving signal is a fourth target driving signal, the second charging and discharging unit discharges the reference capacitor; wherein the third target drive signal and the fourth target drive signal are inverse signals.

In a possible implementation manner of the first aspect, the second arithmetic unit performs arithmetic processing on the second driving signal and the second control signal to obtain a second charging driving signal; the third arithmetic unit carries out arithmetic processing on the first charging driving signal and the second charging driving signal to obtain a third charging driving signal; wherein the second and third operators are exclusive-or operators.

In a possible implementation of the first aspect, the third charging drive signal includes a third target charging drive signal and a fourth target charging drive signal; when the third charging driving signal is a third target charging driving signal, the integration unit charges the integration capacitor; when the third charging driving signal is a fourth target charging driving signal or when the third charging driving signal charges the integration capacitor for a charging time reaching a charging threshold value, the integration unit does not charge the integration capacitor and keeps the voltage of the integration capacitor unchanged; wherein the third target charge driving signal and the fourth target charge driving signal are inverted signals.

In a second aspect, an embodiment of the present application provides a capacitance detection method, which is applied to a capacitance detection circuit including the above-mentioned capacitance detection circuit, and the method includes: the capacitor unit to be tested charges or discharges the capacitor to be tested according to the first driving signal and the current source; the operation unit determines a first charging driving signal provided for the integral power supply according to the first driving signal and the first control signal; the integration unit generates an integrated voltage according to the first charging driving signal and the charging frequency threshold value provided by the operation unit.

In a possible implementation of the second aspect, the reference capacitance unit outputs a second control signal according to a second driving signal; the data processing unit carries out quantization processing on the integrated voltage and determines whether the capacitance change quantity to be detected corresponds to the touch operation result of the user.

In a possible implementation of the second aspect, the operation unit is further configured to determine a second charging driving signal according to the second driving signal and the second control signal, and to determine a third charging driving signal according to the first charging driving signal and the second charging driving signal.

In a third aspect, an embodiment of the present application provides a capacitance detection chip, including the capacitance detection circuit described above, where the capacitance detection circuit may be used to perform the capacitance detection method described above.

In a fourth aspect, an embodiment of the present application provides a capacitance detection device, including the capacitance detection circuit described above.

Drawings

Fig. 1 shows a schematic diagram of a conventional capacitance detection circuit.

Fig. 2 shows a charging graph before and after a change in the capacitance to be measured in the prior art.

Fig. 3 is a schematic diagram showing a structure of a capacitance detection circuit according to the present embodiment.

Fig. 4 shows a voltage graph before and after a change in capacitance to be measured according to the present embodiment.

Fig. 5A shows a flowchart of an implementation of a capacitance detection method according to the present embodiment.

Fig. 5B shows a flowchart of another implementation of the capacitance detection method according to the present embodiment.

Fig. 6 shows an operation timing chart of a capacitance detection circuit according to the present embodiment.

Fig. 7 is a schematic diagram showing another configuration of the capacitance detection circuit according to the present embodiment.

Fig. 8 shows a flowchart of another implementation of the capacitance detection method according to the present embodiment.

Fig. 9 is a schematic diagram showing a structure of another capacitance detection circuit according to the present embodiment.

Fig. 10 shows a voltage graph before and after a change in capacitance to be measured according to the present embodiment.

Fig. 11 shows a flowchart of another implementation of the capacitance detection method according to the present embodiment.

Fig. 12 shows an operation timing chart of another capacitance detection circuit according to the present embodiment.

Fig. 13 is a schematic diagram showing a structure of another capacitance detection circuit according to the present embodiment.

Detailed Description

The following detailed description of the application will be made in conjunction with the accompanying drawings, and it is evident that the described embodiments are only some, but not all, examples of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to fall within the scope of the present application.

Fig. 1 shows a schematic diagram of a capacitance detection circuit. As shown in fig. 1, the vicinity of the sensing electrode of the capacitance sensor forms a capacitance Cx to be measured due to wiring or the like. When a conductor, such as a finger, is brought close to the sensing electrode, a positive capacitance change Δcx occurs. The circuit structure comprises a resistor RS, a pin capacitor C, a start comparator 1, an end comparator 2, a digital converter, a buffer and a current mirror. Where C is the total capacitance at the pin, including chip pin parasitic capacitance and sense capacitance. The reference voltage VREF generates a reference current I1 through a buffer and a resistor RS, wherein the buffer is composed of an error amplifier and an NMOS tube MN1 connected with a source follower. The reference current I1 is converted into a charging current I2 by a current mirror to charge the capacitor C, when the pin of the capacitor C reaches the rated level VSTA, the comparator 1 turns over, and the digital converter starts timing; when the capacitor C pin reaches a higher nominal level VEND, the comparator 2 turns over and the digitizer ends the timer. Finally, the time interval is converted into data for processing by the processor.

It will be appreciated that fig. 2 shows a charge curve before and after a change in the induced capacitance. The abscissa of the graph shown in fig. 2 represents the charging time of the capacitor C, and the unit may be T; the ordinate represents the voltage value, which may be in volts (V). With continued reference to FIG. 2, cl1 is the capacitance charge curve before the change of the sense capacitance C; CL2 is the capacitance charge curve after the change of the sensing capacitance C. T is the charge time before the change of the sense capacitance C, and T' is the charge time after the change of the sense capacitance C. When a conductor (such as a finger) approaches or contacts the sensing electrode of the capacitive sensor, the capacitance value between the sensing electrode and the ground changes, the charging time becomes longer, the capacitance near the sensing electrode is detected, and the capacitance is converted into a time digital signal by a digital converter, so that the magnitude and the change of the measured physical quantity are determined.

It can be understood that the process of implementing capacitance detection based on the capacitance detection circuit is complex, the number of components forming the circuit is large, and the circuit connection is complex.

In order to solve the above problems, embodiments of the present application provide a capacitance detection circuit and a capacitance detection method based on the capacitance detection circuit. Specifically, the capacitance detection circuit includes: the device comprises a capacitor unit to be tested, an operation unit and an integration unit, wherein the capacitor unit to be tested is used for outputting a first control signal according to a first driving signal; an operation unit for determining a first charging drive signal supplied to the integration power supply according to the first drive signal and the first control signal; and the integrating unit is used for generating an integrated voltage according to the first charging driving signal and the charging frequency threshold value provided by the operation unit.

In some optional embodiments, the capacitance detection circuit may further include a reference capacitance unit, and the reference capacitance unit is configured to output a second control signal according to the second driving signal. It is understood that the first driving signal and the second driving signal are the same driving signal; or the first drive signal and the second drive signal are different drive signals.

It will be appreciated that the above-described arithmetic unit may also be used for the second drive signal and the second control signal, for determining the second charge drive signal, and for determining the third charge drive signal from the first charge drive signal and the second charge drive signal.

It can be understood that, when the user performs a touch operation, the capacitance Cx to be measured at the capacitance detecting end changes in size. In the capacitance detection circuit provided by the application, based on the constant current source charging principle, the voltage in the charging and discharging process of the capacitance Cx to be detected is respectively compared with the high turnover voltage and the low turnover voltage of the first trigger, the first control signal is output, the first driving signal and the first control signal are subjected to exclusive OR operation to obtain the first charging driving signal, and the first charging driving signal is used for charging the integrating capacitance Cs, so that the capacitance value of the capacitance Cx to be detected is converted into the time for charging the integrating capacitance, fewer peripheral elements are used, the effect of detecting the capacitance change is also achieved, and the complexity of the detection process is reduced.

The structure of the capacitance detection circuit provided by the embodiment of the present application is described first, and then the capacitance detection method provided by the embodiment is described based on the capacitance detection circuit.

Example 1

Fig. 3 is a schematic diagram showing a structure of a capacitance detection circuit according to the present embodiment.

As shown in fig. 3, the capacitance detection circuit of the present embodiment includes: the device comprises a capacitor unit 110 to be measured, an operation unit 120, an integration unit 130 and a data processing unit 140. The capacitor unit 110, the arithmetic unit 120, the integrating unit 130 and the data processing unit 140 are directly connected by wires.

Wherein the capacitor unit under test 110 includes: the capacitive sensor, the first switch K1, the second switch K2, the constant current source I ₁ and the constant current source I ₂, the capacitance Cx to be measured and the first trigger. The arithmetic unit 120 includes a first operator. The integrating unit 130 includes a third switch K3, a fourth switch K4, a constant current source I ₃, and an integrating capacitor Cs. The capacitance Cx to be measured includes: the intrinsic capacitance of the capacitance detection end and the parasitic capacitance inside the capacitance detection end. In other embodiments, the capacitance Cx to be measured further includes an external parasitic capacitance generated by the capacitance detection ground, and the like. The data processing unit 140 comprises an analog-to-digital converter, i.e. an ADC converter.

In some embodiments, the capacitance to be measured unit 110 charges and discharges the capacitance to be measured CX based on the first driving signal cx_drive. Specifically, the first driving signal cx_drive is a charging/discharging driving signal for controlling the first switch K1 and the second switch K2 to be alternately turned on, and charging/discharging the capacitance CX to be measured. When the voltage at two ends of the capacitance Cx to be measured is at VTL, the first switch K1 is closed, the second switch K2 is opened, and the constant current source I ₁ charges the capacitance Cx to be measured.

The first trigger is used for outputting a first control signal according to the voltages at two ends of the capacitance Cx to be detected. When the voltage at two ends of the capacitance Cx to be detected is increased to VTH, the signal output by the first trigger is overturned, namely VTH is the high overturned voltage of the first trigger; at this time, the first switch K1 is opened, the second switch K2 is closed, and the constant current source I ₂ discharges the capacitance Cx to be measured. When the voltage at two ends of the capacitance Cx to be detected is reduced to VTL from VTH, the signal output by the first trigger is turned over again, namely the VTL is the low turning voltage of the first trigger. And the first trigger outputs a first control signal. In some embodiments, constant current sources I1 and I2 may be the same constant current source, without limitation. The first trigger may be, for example, a schmitt trigger, configured to perform shaping processing on a charge-discharge waveform of the capacitor to be tested, so as to obtain a first control signal.

It is understood that the operation unit 120 includes at least a first operator, where the first operator may be, for example, an exclusive-or operator, and is configured to exclusive-or the first driving signal and the first control signal to obtain a first charging driving signal for controlling the charging of the integrating capacitor Cs. In other embodiments, the first arithmetic unit may be other arithmetic units, and may be specifically set or selected according to actual requirements, which is not limited herein.

It will be appreciated that the integration unit 130 is configured to charge the integration capacitor Cs according to the first charging driving signal. Specifically, when the first charge driving signal is high, the third switch K3 is closed, and the constant current source I3 charges the integration capacitance Cs, that is, injects charge into the integration capacitance Cs. When the first charge driving signal is low, the third switch K3 is turned off, the charge in the integrating capacitor Cs is maintained, the charge is gradually accumulated in the integrating capacitor Cs, and the voltage rises along with the charge, and the next charge operation of the second charge driving signal is waited. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise. When the first charging driving signal charges the integrating capacitor for N times, the Cs voltage is kept unchanged.

The data processing unit 140 is configured to perform quantization processing on the voltages across the integrating capacitor Cs. Specifically, the present integrating capacitor Cs voltage is quantized by an analog-to-digital converter, i.e., an a/D converter (analog to digital converter, ADC). After the ADC is completed, the fourth switch K4 is turned on to reset the charge in the integrating capacitor Cs, that is, to bleed the charge, so as to prepare for accurate measurement in the next detection period, and meanwhile, no longer generate a periodic first driving signal for charging and discharging the capacitance Cx to be detected.

In some alternative embodiments, according to the charge amount formulas q=it and q=cv, the pulse width generated by charging and discharging the capacitance Cx to be measured can be calculated, and the specific calculation process is as follows:

the charging time of the capacitance Cx to be measured:

the discharge time of the capacitance Cx to be measured:

it can be understood that the charge and discharge time of the capacitance Cx to be measured is calculated according to the formulas (1) to (2). Therefore, when the time of single charging of the integrating capacitor Cs is T ₀+T₁, the voltage of Cs after the charging operation of the integrating capacitor Cs is performed N times is:

It can be understood that when the capacitance Cx to be measured becomes larger after a touch, the charging time for the integrating capacitor Cs becomes longer in a corresponding one period, and thus the voltage of the large capacitor Cs becomes higher after charging N times. The CS voltage V' _cs after touch is:

only C _x changes before and after touch, so that other invariant terms can be set as a constant k, and the above equation can be obtained:

the corresponding k value obtained through the calculation is constant,

When a user operates, the size of the capacitance Cx to be detected changes, so that the charge and discharge rate of the integration capacitance Cs changes, and the current voltage of the integration capacitance Cs is quantized through the ADC converter, so that whether touch operation exists or not is judged according to a quantization result. In some embodiments, the integration voltage may be processed to obtain a time of integration for use, so as to determine the touch operation of the user according to a preset time threshold. For example, when the integration time is greater than or equal to a preset time threshold, determining that the user has a touch operation; and when the integration time is smaller than a preset time threshold value, determining that the user has no touch operation.

It will be appreciated that fig. 4 shows a voltage graph before and after a change in capacitance to be measured according to an embodiment of the present application.

The abscissa of the graph shown in fig. 4 represents the charge and discharge time of the capacitor to be measured and the reference capacitor, and the unit may be T; the ordinate represents the voltage value, which may be in volts (V). With continued reference to fig. 4, L1 is a charge-discharge curve before the capacitance of the capacitance Cx to be measured changes, and L2 is a charge-discharge curve after the capacitance of the capacitance Cx to be measured changes. T0 is the charging time before the capacitance of the capacitance Cx to be measured changes, and T1 is the discharging time before the capacitance of the capacitance Cx to be measured changes. T2 is the charging time after the capacitance of the capacitance Cx to be measured changes, and T3 is the discharging time after the capacitance of the capacitance Cx to be measured changes. The 1 period is 1 cx_drive clock period.

As can be seen from fig. 4, when the user performs the operation, the size of the capacitance Cx to be measured changes, the charging time of the capacitance Cx to be measured correspondingly increases, and the charging time of the capacitance Cx to be measured affects the charging time of the integrating capacitor Cs. Therefore, after the capacitance value of the capacitance Cx to be measured is changed, the charging time for the integrating capacitor Cs is also changed. Accordingly, the touch operation of the user can be determined from the charging time required for the integration capacitance Cs to be charged to the preset voltage value and the preset time threshold.

Based on the capacitance detection circuit shown in fig. 3, a specific implementation procedure of the capacitance detection method provided by the embodiment of the application is described below with reference to a flow shown in fig. 5A.

As shown in fig. 5A, the capacitance detection method provided by the embodiment of the application includes the following steps:

501: the capacitance unit to be tested outputs a first control signal according to the first driving signal.

Illustratively, the first drive signal includes a first target drive signal and a second target drive signal. When the first driving signal is a first target driving signal, the capacitor unit to be tested charges the capacitor to be tested; when the first driving signal is a second target driving signal, the capacitor unit to be tested discharges the capacitor to be tested; wherein the first target drive signal and the second target drive signal are inverse signals.

It is understood that the capacitor unit under test 110 in fig. 3 is taken as an example. Specifically, the first driving signal cx_drive is a charging/discharging driving signal for controlling the first switch K1 and the second switch K2 to be alternately turned on, and charging/discharging the capacitance CX to be measured. When the voltage at two ends of the capacitance Cx to be detected is increased to VTH, the signal output by the first trigger is overturned, namely VTH is the high overturned voltage of the first trigger; at this time, the first switch K1 is opened, the second switch K2 is closed, and the constant current source I ₂ discharges the capacitance Cx to be measured. When the voltage at two ends of the capacitance Cx to be detected is reduced to VTL from VTH, the signal output by the first trigger is turned over again, namely the VTL is the low turning voltage of the first trigger. And the first trigger outputs a first control signal. In some embodiments, constant current sources I1 and I2 may be the same constant current source, without limitation. The first trigger may be, for example, a schmitt trigger, configured to perform shaping processing on a charge-discharge waveform of the capacitor to be tested, so as to obtain a first control signal.

502: The operation unit determines a first charging drive signal supplied to the integration power supply according to the first drive signal and the first control signal.

It is understood that the above-mentioned arithmetic unit includes at least a first arithmetic unit. The first calculator is configured to determine a first charging driving signal provided to the integration power supply according to the first driving signal and the first control signal.

It will be appreciated that, taking the integrating unit 130 in fig. 3 as an example, the first arithmetic unit may be, for example, an exclusive-or arithmetic unit, and perform an exclusive-or operation on the first control signal and the first driving signal to obtain a first charging driving signal for controlling charging of the integrating capacitor.

503: The integration unit generates an integration voltage according to the first charging driving signal and the charging frequency threshold value provided by the operation unit.

The integration unit is used for generating an integrated voltage according to a first charging driving signal and a charging frequency threshold value provided by the first arithmetic unit. The first charging driving signal includes a first target charging driving signal and a second target charging driving signal. When the first charging driving signal is a first target charging driving signal, the integration unit generates an integration voltage; when the first charging driving signal is the second target charging driving signal, no integrated voltage is generated any more and the voltage value of the integrated capacitor is kept unchanged; the first target charging driving signal and the second target charging driving signal are inverted signals.

It will be appreciated that the integration unit 130 in fig. 3 is taken as an example. The integration unit 130 is configured to charge the integration capacitor Cs according to the first charging driving signal (i.e., cs_drive). Specifically, when the first charging drive signal is high, that is, the first charging drive signal is the first target charging drive signal, the third switch K3 is closed, and the constant current source I3 charges the integration capacitor Cs, that is, charges are injected into the integration capacitor Cs; when the first charging driving signal is low, that is, the first charging driving signal is the second target charging driving signal, the third switch K3 is turned off, the charge in the integrating capacitor Cs is maintained, the charge is gradually accumulated in the integrating capacitor Cs, the voltage rises along with the charge, and the next charging action of the first charging driving signal is waited. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise. When the first charging driving signal charges the integrating capacitor for N times, the Cs voltage is kept unchanged.

Optionally, after step 503, 504 may also be included, as shown in fig. 5B.

504: The data processing unit performs quantization processing on the integrated voltage.

The data processing unit is used for carrying out quantization processing on the integrated voltage to obtain time information corresponding to the integrated voltage. And determining whether the capacitance variation to be detected corresponds to a touch operation result of the user based on the time information and the preset time information.

It will be appreciated that taking the data processing unit 140 in fig. 3 as an example, the data processing unit 140 is configured to perform quantization processing on the voltages across the integrating capacitor Cs. Specifically, the current integrating capacitor Cs voltage is quantized by an analog-digital converter, i.e., an a/D converter (analog to digital converter, ADC), to obtain time information corresponding to the integrating voltage. And determining whether the capacitance variation to be detected corresponds to a touch operation result of the user based on the time information and the preset time information. After the ADC is completed, the fourth switch K4 is turned on to reset the charge in the integrating capacitor Cs, that is, to bleed the charge, so as to prepare for accurate measurement in the next detection period, and meanwhile, no longer generate a periodic first driving signal for charging and discharging the capacitance Cx to be detected.

Fig. 6 shows an operation timing chart of a capacitance detection circuit according to the present embodiment.

The above-described process of changing the capacitance Cx to be measured and the integrating capacitance Cs in steps 501 to 504 may be referred to as a timing diagram shown in fig. 6.

As shown in fig. 6, cx_driv is used as a first driving signal for charging and discharging the capacitance Cx to be measured, and when cx_driv is high, the driving power supply voltage charges and discharges the capacitance Cx to be measured.

With continued reference to fig. 6, it can be seen from the circuit operation timing chart shown in fig. 6 that when cs_drive (first charging DRIVE signal) is high, the integrating capacitor Cs is charged, that is, charges are injected into the integrating capacitor Cs; when cs_drive is low, the charge in the integration capacitance Cs is held, and the charge is gradually accumulated in the integration capacitance Cs. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise, as shown by Cs in fig. 6, until cs_drive reaches a preset number of times of charging operation of the integrating capacitor, and the Cs voltage remains unchanged.

It can be understood that, when the user performs a touch operation, the capacitance Cx to be measured at the capacitance detecting end changes in size. In the capacitance detection circuit provided by the embodiment of the application, based on the constant current source charging principle, the voltage in the charging and discharging process of the capacitance Cx to be detected is respectively compared with the high turnover voltage and the low turnover voltage of the first trigger, the first control signal is output, the first driving signal and the first control signal are subjected to exclusive OR operation to obtain the first charging driving signal, and the first charging driving signal is used for charging the integration capacitance Cs, so that the capacitance value of the capacitance Cx to be detected is converted into the time for charging the integration capacitance, fewer peripheral elements are used, the effect of detecting the capacitance change is achieved, and the complexity of a system is reduced.

The capacitive sensing scheme provided by another embodiment of the present application is described below.

Example 2

Fig. 7 is a schematic diagram showing another configuration of the capacitance detection circuit according to the present embodiment. As shown in fig. 7, the capacitance detection circuit of the present embodiment includes: the device comprises a capacitor unit 210 to be measured, an operation unit 220, an integration unit 230 and a data unit 240. The capacitor unit 210, the operation unit 220, the integration unit 230 and the data unit 240 are directly connected by wires.

Wherein the capacitance unit to be measured 210 includes: a capacitance sensor, a fifth switch K5, a sixth switch K6, a resistor R1 and a resistor R2, a capacitance Cx to be measured and a trigger 1. The arithmetic unit 220 includes an operator 1. The integrating unit 220 includes the seventh switch K7, the eighth switch K8, the resistor R3, and the integrating capacitor Cs. The capacitance Cx to be measured includes: the intrinsic capacitance of the capacitance detection end and the parasitic capacitance inside the capacitance detection end. In other embodiments, the capacitance Cx to be measured further includes an external parasitic capacitance generated by the capacitance detection ground, and the like. The data processing unit 240 includes a first comparator, a first latch, and a first counter.

It can be understood that the charging and discharging process of the capacitance Cx to be measured in fig. 7 is similar to that of fig. 3. In contrast, the capacitance to be measured unit 210 charges and discharges the capacitance to be measured Cx based on the driving signal 1. When the voltage across the capacitance Cx to be measured is at VTL1, the fifth switch K5 is closed and the sixth switch K6 is opened, charging the capacitance Cx to be measured based on the resistor R1. When the voltage at two ends of the capacitance Cx to be detected is increased to VTH1, the signal output by the trigger 1 is overturned, namely VTH1 is the high overturned voltage of the trigger 1; at this time, the fifth switch K5 is opened, the sixth switch K6 is closed, and the capacitance Cx to be measured is discharged based on the resistor R2. When the voltage at two ends of the capacitance Cx to be detected is reduced to VTL1 from VTH1, the signal output by the trigger 1 is inverted again, namely VTL1 is the low inverted voltage of the trigger 1. And (3) circularly oscillating so that the voltage at two ends of the capacitance Cx to be measured oscillates between VTH1 and VTL1, and the trigger 1 outputs a control signal 1.

It is to be understood that the operation unit 220 includes an operator 1, for example, an exclusive-or operator, for exclusive-or operating the driving signal 1 and the control signal 1 to obtain the charging driving signal 1 for controlling the charging of the integrating capacitor Cs.

It will be appreciated that the integration unit 230 is configured to charge the integration capacitor Cs according to the charging driving signal 1. Specifically, when the charging drive signal 1 is high, the seventh switch K7 is closed, and the resistor R3 charges the integrating capacitor Cs, that is, charges are injected into the integrating capacitor Cs; when the charge driving signal 1 is low, the seventh switch K7 is turned off, the charge in the integrating capacitor Cs is maintained, the charge is gradually accumulated in the integrating capacitor Cs, and the voltage rises accordingly, and the next charging operation of the charge driving signal 1 is waited. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise. When the charging action of the charging driving signal 1 on the integrating capacitor reaches the preset times of N times, the Cs voltage is kept unchanged.

The data processing unit 240 is configured to perform quantization processing on the voltages across the integrating capacitor Cs. Specifically, the first comparator determines the voltage Vcs at the first input terminal and the reference voltage Vref at the second input terminal, latches the comparison result according to the first clock CLK, and the first counter counts the period of the second charging driving signal cs_drive. The result of the counting is taken as first sampling data. When the voltage of the first input terminal is less than the reference voltage Vref of the second input terminal, the eighth switch K8 is kept in an open state. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise until it stabilizes at the reference voltage Vref. When the voltage of the first input terminal is greater than the reference voltage Vref of the second input terminal, the periodic charge-discharge driving signal Cx_DRIVE is not generated. The measurement phase of the capacitance detection circuit has ended. The eighth switch K8 resets the charge in the integration capacitance Cs, and initializes the voltage across the integration capacitance Cs to an initial voltage. Preparation is made for accurate measurement of the next detection period. If the voltage at both ends of the integrating capacitor Cs exceeds the reference voltage Vref for a preset time in the measurement stage, the capacitor detection result is forcibly terminated, so that the circuit is prevented from being blocked.

Based on the capacitance detection circuit shown in fig. 7, a specific implementation procedure of a capacitance detection method according to another embodiment of the present application is described below with reference to the flowchart shown in fig. 8.

As shown in fig. 8, a capacitance detection method according to another embodiment of the present application includes the following steps:

801: the capacitance unit to be tested outputs a control signal 1 according to the driving signal 1.

It is understood that the capacitor unit to be measured 210 in fig. 7 is taken as an example. Specifically, the driving signal 1 is a charging and discharging driving signal of the capacitance Cx to be measured, and is used for controlling the fifth switch K5 and the sixth switch K6 to be opened alternately, and the resistor R1 and the resistor R2 charge and discharge the capacitance Cx to be measured. When the voltage at two ends of the capacitance Cx to be detected is increased to VTH1, the signal output by the trigger 1 is overturned, namely VTH1 is the high overturned voltage of the trigger 1; at this time, the fifth switch K5 is closed, the sixth switch K6 is opened, and the resistor R1 charges the capacitance Cx to be measured. When the voltage at two ends of the capacitance Cx to be measured is in VTH1, the fifth switch K5 is opened, the sixth switch K6 is closed, and the resistor R2 discharges the capacitance Cx to be measured. When the voltage at two ends of the capacitance Cx to be detected is reduced to VTL1 from VTH1, the signal output by the trigger 1 is inverted again, namely VTL1 is the low inverted voltage of the trigger 1. And (3) circularly oscillating so that the voltage at two ends of the capacitance Cx to be measured oscillates between VTH1 and VTL1, and the trigger 1 outputs a control signal 1. The trigger 1 may be, for example, a schmitt trigger, and is configured to shape a charge-discharge waveform of a capacitor to be tested to obtain the control signal 1.

802: The operation unit obtains a charging driving signal 1 according to the driving signal 1 and the control signal 1.

It will be appreciated that, taking the operation unit 220 in fig. 7 as an example, the operation unit 220 includes an operator 2, for example, an exclusive or operator, for exclusive-or operating the driving signal 1 and the control signal 1 to obtain the charging driving signal 1 for controlling the charging of the integrating capacitor.

803: The integrating unit generates an integrated voltage according to the charging threshold and the charging driving signal 1.

It will be appreciated that the integration unit 230 in fig. 7 is taken as an example. The integrating unit 230 is configured to charge the integrating capacitor Cs according to the charging driving signal 1. Specifically, when the charging drive signal 1 is high, the seventh switch K7 is closed, and the resistor R3 charges the integrating capacitor Cs, that is, charges are injected into the integrating capacitor Cs; when the charge driving signal 1 is low, the seventh switch K7 is turned off, the charge in the integrating capacitor Cs is maintained, the charge is gradually accumulated in the integrating capacitor Cs, and the voltage rises accordingly, and the next charging operation of the charge driving signal 1 is waited. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise. When the charging action of the charging driving signal cs_drive on the integrating capacitor reaches the preset number of times N, the Cs voltage remains unchanged.

804: The data processing unit performs quantization processing on the integrated voltage.

It will be appreciated that the data processing unit 240 in fig. 7 is taken as an example. The data processing unit 240 is configured to perform quantization processing on the voltages across the integrating capacitor Cs. Specifically, the first comparator determines the voltage Vcs at the first input terminal and the reference voltage Vref at the second input terminal, and then the first clock CLK latches the comparison result, and the first counter counts the period of the charging driving signal 1. The result of the counting is taken as first sampling data. When the voltage of the first input terminal is less than the reference voltage Vref of the second input terminal, the eighth switch K8 is kept in an open state. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise until it stabilizes at the reference voltage Vref. When the voltage at the first input terminal is greater than the reference voltage Vref at the second input terminal, the periodic driving signal 1 is not generated. The measurement phase of the capacitance detection circuit has ended. The eighth switch K8 is closed to reset the charge in the integrating capacitor Cs, and the voltage across the integrating capacitor Cs is initialized to the initial voltage. Preparation is made for accurate measurement of the next detection period. If the voltage at both ends of the integrating capacitor Cs exceeds the reference voltage Vref for a preset time in the measurement stage, the capacitor detection result is forcibly terminated, so that the circuit is prevented from being blocked.

It can be appreciated that the present application also provides another capacitance detection circuit based on the above embodiment 1, and the accuracy of the capacitance detection result is made higher by providing the reference capacitance unit. Another capacitance detection circuit is described in detail below by example 3.

Example 3

Fig. 9 is a schematic diagram showing a configuration of a capacitance detection circuit according to the present embodiment.

As shown in fig. 9, the capacitance detection circuit of the present embodiment includes: the device comprises a capacitor unit 110 to be measured, an operation unit 120, an integration unit 130, a data processing unit 140 and a reference capacitor unit 150. The capacitance unit to be measured 110, the operation unit 120, the integration unit 130, the data processing unit 140 and the reference capacitance unit 150 are directly connected through wires.

Wherein the capacitor unit under test 110 includes: the capacitive sensor, the first switch K1, the second switch K2, the first power supply unit (namely the constant current source I ₁ and the constant current source I ₂), the capacitance Cx to be measured and the first trigger. The integrating unit 120 includes a third switch K3, a fourth switch K4, a constant current source I ₃, and an integrating capacitor Cs. The reference capacitance unit 140 includes: pin, fifth switch K5, sixth switch K6, reference capacitor Cref, second power supply unit (i.e., constant current sources I ₄ and I ₅), and third flip-flop. The data processing unit 130 includes an analog-to-digital converter, i.e., an a/D converter.

The capacitance Cx to be measured includes: the intrinsic capacitance of the capacitance detection end and the parasitic capacitance inside the capacitance detection end. In other embodiments, the capacitance Cx to be measured further includes an external parasitic capacitance generated by the capacitance detection ground, and the like.

It can be understood that the connection manner and specific operation principle of each element in the capacitor unit under test 110 can be referred to the related description of the capacitor unit under test 110 in embodiment 1, which is not described herein.

The reference capacitor unit 150 is configured to output a second control signal cref_in. Specifically, cs_drive (i.e., the second driving signal) is used as a charge/discharge driving signal of the reference capacitor, and is used to control the fifth switch K5 and the sixth switch K6 to be opened alternately, so as to charge/discharge the reference capacitor Cref. When the voltage at two ends of the reference capacitor Cref is in VTL2, the fifth switch K5 is closed, the sixth switch K6 is opened, and the constant current source I ₄ charges the reference capacitor Cref; when the voltage at two ends of the reference capacitor Cref is increased to VTH2, the signal output by the second trigger is overturned, namely VTH2 is the high overturned voltage of the second trigger; at this time, the fifth switch K5 is opened, the sixth switch K6 is closed, and the constant current source I ₅ discharges the reference capacitor Cref. When the voltage at two ends of the capacitor Cx to be detected is reduced to VTL2 from VTH2, the signal output by the second trigger is inverted again, namely VTL2 is the low inverted voltage of the second trigger. The second trigger outputs a second control signal CREF_IN, and the second trigger is cycled back and forth so that the voltage at two ends of the capacitance Cx to be detected oscillates back and forth between VTH2 and VTL 2. In some embodiments the constant current sources I ₄ and I ₅ may be the same constant current source, without limitation.

The low inversion voltage VTL of the first trigger is the same as the low inversion voltage VTL2 of the second trigger, and the values are VTL-A The high inversion voltage VTH of the first flip-flop is the same as the high inversion voltage VTH2 of the second flip-flop, and the values are VTH-B.

It is understood that the operation unit 120 includes a first operator, a second operator, and a third operator. The first arithmetic unit is used for processing the first control signal and the first driving signal and determining a first charging driving signal; the second arithmetic unit processes the second control signal and the second driving signal to determine a second charging driving signal; the third arithmetic unit is used for determining the charging driving signal of the integration capacitor Cs for the first charging driving signal and the second charging driving signal. The specific processing process comprises the following steps:

The first control signal and the first DRIVE signal are subjected to signal processing, such as exclusive or operation processing, by the first operator to obtain a first charge DRIVE signal (i.e., cs_drive_cx) of the integration capacitor Cs. And, performing signal processing, such as exclusive or operation, on the second control signal and the second driving signal by the second arithmetic unit to obtain a second charging driving signal (i.e., cs_drive_cref) of the integrating capacitor Cs. Further, the third arithmetic unit performs signal processing, such as exclusive or operation, on the first charging driving signal and the second charging driving signal to obtain a third charging driving signal (i.e., cs_drive) of the integrating capacitor Cs after the reference channel compensation.

It will be appreciated that the integration unit 130 is configured to charge the integration capacitor Cs according to the third charging driving signal. Specifically, when the third charging driving signal is high, the third switch K3 is closed, and the constant current source I ₃ charges the integrating capacitor Cs, that is, charges are injected into the integrating capacitor Cs; when the third charge driving signal is low, the third switch K3 is turned off, the charge in the integrating capacitor Cs is maintained, the charge is gradually accumulated in the integrating capacitor Cs, and the voltage rises accordingly, and the next charging operation of the third charge driving signal is waited. Along with the continuous accumulation of the charges, the voltage of the integrating capacitor Cs is increased stepwise until the third charging driving signal charges the integrating capacitor for N times, and the voltage of Cs is kept unchanged.

The data processing unit 140 is configured to perform quantization processing on the voltages across the integrating capacitor Cs. Specifically, the present integrating capacitor Cs voltage is quantized by an analog-to-digital converter, i.e., an a/D converter (analog to digital converter, ADC). When the ADC is completed, the fourth switch K4 is turned on to reset the charge in the integrating capacitor Cs, that is, to bleed the charge, so as to prepare for accurate measurement in the next detection period, and at the same time, no longer generate the periodic Cx driving signal cx_drive.

In some alternative embodiments, according to the charge amount formulas q=it and q=cv, the pulse width generated by charging and discharging the reference capacitor Cref can be calculated, and the specific calculation process is as follows:

reference capacitor Cref charge time:

reference capacitor Cref discharge time:

It can be understood that the charge and discharge time of the capacitance Cx to be measured and the charge and discharge time of the reference capacitance Cref are calculated according to the formula (1), the formula (2), the formula (8), and the formula (9). Further obtaining the charging time T ₂＝T₀ -T' of the integrating capacitor Cs after the reference capacitor Cref is compensated; the discharge time T ₃＝T₁ -T of the integrating capacitor Cs after compensation by the reference capacitor Cref.

For example, assuming that the constant current sources I ₁ and I ₂ are the same constant current source, and the constant current sources I ₄ and I ₅ are the same constant current source, at this time, the single charging time of the integrating capacitor Cs is T ₂+T₃, and when the charging operation of the integrating capacitor Cs reaches N times, the voltage V _Cs across the integrating capacitor Cs is:

it can be understood that when the external environment changes, only the capacitance values of the capacitance Cx to be measured and the reference capacitance Cref change. Therefore, other invariant terms can be set to constants K1 and K2.

When the environment is changed, and the charging action of the integrating capacitor Cs is performed N times, the voltage V _Cs at two ends of the integrating capacitor Cs is:

When the environment is changed, the capacitance C _x′＝C_x+ΔC_x to be measured changes to C _ref′＝C_ref+ΔC_ref, and when the charging action of the integrating capacitor Cs is performed for N times, the voltage V _Cs' at two ends of the integrating capacitor Cs is:

as can be seen from the above-described formula (11) and formula (12), the amount of change Δvcs of the voltage across the integrating capacitor Cs due to the environmental change is:

it can be understood that if the reference channel compensation is not performed, the variation Δvcs' of the voltages across the integrating capacitor Cs is:

From equations (13) and (14), it can be seen that the reference channel compensation reduces the effects of environmental changes.

When a user operates, the magnitude of the capacitance Cx to be detected changes, so that the charge and discharge rate of the integration capacitance Cs changes, and the current voltage of the integration capacitance Cs is quantized through the A/D converter, so that whether touch operation exists or not is judged according to a quantization result.

It will be appreciated that fig. 10 shows a voltage plot of a measured capacitance versus an environmental change and a reference capacitance in accordance with an embodiment of the present application.

The abscissa of the graph shown in fig. 10 represents the charge and discharge time of the capacitor to be measured and the reference capacitor, and the unit may be T; the ordinate represents the voltage value, which may be in volts (V). With continued reference to fig. 10, R1 is a capacitance charge-discharge curve before the environmental change of the capacitance Cx to be measured, and R2 is a capacitance charge-discharge curve after the environmental change of the capacitance Cx to be measured; l1 is a capacitance charge-discharge curve before the reference capacitance Cref environment changes, and L2 is a capacitance charge-discharge curve after the reference capacitance Cref environment changes. Δt1 is the amount of change in the charging time of the capacitance Cx to be measured due to the environmental change, and Δt2 is the amount of change in the discharging time of the capacitance Cx to be measured due to the environmental change. Δt3 is the amount of change in the reference capacitance discharge time due to environmental changes, and Δt4 is the amount of change in the reference capacitance charge time due to environmental changes. T2 is the charging time of the integrating capacitor Cs after the reference capacitor Cref is compensated, and T3 is the discharging time of the integrating capacitor Cs after the reference capacitor Cref is compensated. The 1 period is 1 cx_drive clock period.

As can be seen from fig. 10, when the environment changes, the charging time of the capacitor Cx to be measured increases correspondingly, such as Δt1 in fig. 3, and the charging time of the capacitor Cx to be measured affects the charging time of the integrating capacitor Cs. Therefore, when the user performs a touch operation after the environment changes, the capacitance change Δcx of the capacitance Cx to be measured caused by the environment change affects the judgment of the user's touch operation. The added reference capacitance Cref also generates a capacitance change quantity DeltaCref when the environment changes, and part or all DeltaCx can be counteracted, so that the influence of the environment change on the detection result is reduced.

Based on the capacitance detection circuit shown in fig. 9, a specific implementation procedure of the capacitance detection method according to the embodiment of the present application is described below with reference to the flow shown in fig. 11.

As shown in fig. 11, the capacitance detection method provided by the embodiment of the application includes the following steps:

1101: the capacitance unit to be tested outputs a first control signal according to the first driving signal.

It is to be appreciated that step 1101 may be described with reference to step 501, which is not described herein.

1102: The reference capacitance unit outputs a second control signal according to the second driving signal.

The second driving signal includes a third target driving signal and a fourth target driving signal. When the second driving signal is a third target driving signal, the second charging and discharging unit charges the capacitor to be tested; and when the second driving signal is a fourth target driving signal, the second charging and discharging unit discharges the capacitor to be tested. Wherein the third target drive signal and the fourth target drive signal are inverse signals. The second driving signal may be, for example, a driving signal cs_drive for charging and discharging the reference capacitor. In some alternative embodiments, the first driving signal and the second driving signal may be the same driving signal or different driving signals, which is not limited herein.

It can be understood that taking the reference capacitor unit 150 in fig. 9 as an example, when the voltage across the reference capacitor Cref is VTL2, the second driving signal drives the fifth switch K5 to be closed, the sixth switch K6 is opened, and the constant current source I ₄ charges the reference capacitor Cref; when the voltage at two ends of the reference capacitor Cref is increased to VTH2, the signal output by the second trigger is overturned, namely VTH2 is the high overturned voltage of the second trigger; at this time, the second driving signal drives the fifth switch K5 to open, the sixth switch K6 to close, and the constant current source I ₅ discharges the reference capacitor Cref. When the voltage at two ends of the capacitor Cx to be detected is reduced to VTL2 from VTH2, the signal output by the second trigger is inverted again, namely VTL2 is the low inverted voltage of the second trigger. The second trigger outputs a second control signal CREF_IN, and the second trigger is cycled back and forth so that the voltage at two ends of the capacitance Cx to be detected oscillates back and forth between VTH2 and VTL 2. In some embodiments the constant current sources I ₄ and I ₅ may be the same constant current source, without limitation.

1103: The operation unit obtains a third charging driving signal according to the first driving signal, the second driving signal, the first control signal and the second control signal.

The third charge driving signal may be, for example, a third charge driving signal cs_drive that controls the integration capacitance Cs to be charged.

It is understood that, taking the operation unit 120 in fig. 9 as an example, the operation unit includes a first operator, a second operator and a third operator. Specifically, the first charge driving signal is determined by performing signal processing, such as exclusive or operation processing, on the first control signal and the first control signal by the first operator. The second charge driving signal of the integrating capacitor Cs is obtained by performing signal processing, such as exclusive-or operation, on the second control signal and the second driving signal by the second operator. Further, the third arithmetic unit performs signal processing, such as exclusive or operation, on the first charging driving signal and the second charging driving signal to obtain a third charging driving signal of the integrating capacitor Cs after the reference channel compensation.

1104: The integration unit generates an integrated voltage according to the charging threshold value and the third charging driving signal.

The third charging driving signal includes a third target charging driving signal and a fourth target charging driving signal, and the third target charging driving signal and the fourth target charging driving signal are inverse signals. For example, when the third charge drive signal is high, the third charge drive signal is the third target charge drive signal. When the third charge driving signal is low, the third charge driving signal is a fourth target charge driving signal.

Illustratively, taking the integration unit 230 in fig. 9 as an example, when the third charging driving signal is high, the third switch K3 is closed, and the constant current source I ₃ charges the integration capacitor Cs, that is, injects charge into the integration capacitor Cs; when the third charge driving signal is low, the third switch K3 is turned off, the charge in the integrating capacitor Cs is maintained, the charge is gradually accumulated in the integrating capacitor Cs, and the voltage rises accordingly, and the next charging operation of the third charge driving signal is waited. Along with the continuous accumulation of the charges, the voltage of the integrating capacitor Cs is increased stepwise until the third charging driving signal charges the integrating capacitor for N times, and the voltage of Cs is kept unchanged.

1105: The data processing unit performs quantization processing on the integrated voltage.

Illustratively, when the third charging driving signal cs_drive charges the integrating capacitor N times, the analog-digital converter, i.e., the a/D converter (analog to digital converter, ADC) quantizes the current voltage of the integrating capacitor Cs, and determines the touch operation of the user according to the quantized result, in some embodiments, the type of the touch operation may be clicking, long pressing, or the like.

In some alternative embodiments, when the ADC operation is completed, the fourth switch K4 is closed, resetting the charge in the integrating capacitor Cs, i.e. bleeding the charge, in preparation for accurate measurement of the next detection period, while no longer generating the periodic first and second drive signals.

It can be understood that the compensation is based on the same directional change of the reference capacitance unit and the capacitance to be measured of the capacitance to be measured unit in the circuit structure of the capacitance detection circuit. Namely, when the environment changes, the capacitance to be measured of the capacitance unit to be measured can generate a change capacitance delta Cx, and the reference capacitance of the reference capacitance unit can also generate a change capacitance delta Cref, wherein the delta Cref can offset part or all of the delta Cx. Thus, the influence of environmental change on the detection result is reduced based on the method.

Fig. 12 shows an operation timing chart of a capacitance detection circuit according to the present embodiment.

The above-mentioned steps 1101 to 1105 refer to the timing schematic shown in fig. 12 for the changing process of the capacitance Cx to be measured, the reference capacitance Cref, and the integration capacitance Cs. Cx is the change curve of the voltages at two ends IN the charging and discharging process of the capacitance Cx to be measured, cx_IN is the change curve of the first control signal output by the capacitance unit to be measured; cs_drive_cx is the variation curve of the first charge DRIVE signal; cref is a change curve of voltages at two ends in the process of charging and discharging the reference capacitor Cref; cref_IN is the second control signal output by the reference capacitance unit; cs_drive_cref is a change curve of the second charge driving signal; cs_drive is a change curve of the third charge DRIVE signal; vcs is the maximum voltage of two ends of the integrating capacitor Cs; cs is a change curve of the voltage across the integrating capacitor Cs when the integrating capacitor Cs is charged based on the third charging drive signal.

As shown in fig. 12, the charge and discharge driving signals of the capacitor Cx to be measured and the reference capacitor Cref are the same driving signal, for example, cx_drive. When cx_drive is high, the driving power supply voltage charges and discharges the capacitance to be measured Cx and the reference capacitance Cs. The change curves of the voltages at two ends of the capacitor Cx to be measured and the reference capacitor Cref in FIG. 12 are the same-direction changes.

With continued reference to fig. 12, it can be seen from the circuit operation timing chart shown in fig. 12 that when cs_drive (i.e., the third charging DRIVE signal) is high, the integrating capacitor Cs is charged, i.e., charges are injected into the integrating capacitor Cs; when cs_drive is low, the charge in the integration capacitance Cs is held, and the charge is gradually accumulated in the integration capacitance Cs. Along with the continuous accumulation of the charge, the voltage of the integrating capacitor Cs rises stepwise, as shown in Cs in fig. 12, until cs_drive charges the integrating capacitor N times, the voltage across the reference capacitor Cs remains unchanged.

It can be understood that, when the user performs a touch operation, the capacitance Cx to be measured at the capacitance detecting end changes in size. In the capacitance detection circuit provided by the embodiment of the application, two paths of charging current and discharging current can effectively reduce the charging and discharging period of the capacitance detection end, so that the voltage change period of the capacitance detection end is correspondingly reduced, and the oscillation period of the trigger is reduced. Finally, the count value of the counter in the sampling time can be changed to a larger extent, and the sensitivity of capacitance detection is further improved.

The capacitive detection scheme provided by another embodiment of the present application can improve the detection accuracy.

Example 4

Fig. 13 is a schematic diagram showing another configuration of the capacitance detection circuit according to the present embodiment. As shown in fig. 13, the capacitance detection circuit of the present embodiment includes: the device comprises a capacitor unit 210 to be measured, an operation unit 220, an integration unit 230, a data processing unit 240 and a reference capacitor unit 250. The capacitance unit 210 to be measured, the operation unit 220, the integration unit 230, the data processing unit 240 and the reference capacitance unit 250 are directly connected through wires.

Wherein the capacitance unit to be measured 210 includes: a capacitance sensor, a seventh switch K7, an eighth switch K8, a resistor R1 and a resistor R2, a capacitance Cx to be measured and a trigger 1. The arithmetic unit 220 includes an arithmetic unit 1, an arithmetic unit 2, and an arithmetic unit 3. The integrating unit 230 includes the ninth switch K9, the tenth switch K10, a resistor R3, and an integrating capacitor Cs. The data processing unit 240 includes a first comparator, a first latch, and a first counter. The reference capacitance unit 250 includes: pin, eleventh switch K11, twelfth switch K12, reference capacitor Cref, resistor R4 and resistor R5, and flip-flop 2.

The capacitance Cx to be measured includes: the intrinsic capacitance of the capacitance detection end and the parasitic capacitance inside the capacitance detection end. In other embodiments, the capacitance Cx to be measured further includes an external parasitic capacitance generated by the capacitance detection ground, and the like.

It can be understood that the charging and discharging process of the capacitor to be measured Cx and the reference capacitor Cref in fig. 13 is similar to the charging and discharging process of the capacitor to be measured Cx and the reference capacitor Cref in fig. 9.

Specifically, the capacitance unit under test 210 is configured to output the control signal 1. The driving signal 1 is a charging and discharging driving signal of the capacitance to be detected Cx, and is used for controlling the seventh switch K7 and the eighth switch K8 to be opened alternately, and charging and discharging the capacitance to be detected Cx. When the voltage at two ends of the capacitance Cx to be measured is at VTL1, the seventh switch K7 is closed and the eighth switch K8 is opened, charging the capacitance Cx to be measured based on the resistor R1. When the voltage at two ends of the capacitance Cx to be detected is increased to VTH1, the signal output by the trigger 1 is overturned, namely VTH1 is the high overturned voltage of the trigger 1; at this time, the seventh switch K7 is opened, the eighth switch K8 is closed, and the capacitance Cx to be measured is discharged based on the resistor R2. When the voltage at two ends of the capacitance Cx to be detected is reduced to VTL1 from VTH1, the signal output by the trigger 1 is inverted again, namely VTL3 is the low inverted voltage of the trigger 1. And (3) circularly oscillating so that the voltage at two ends of the capacitance Cx to be measured oscillates between VTH1 and VTL1, and the trigger 1 outputs a control signal 1.

The reference capacitance unit 250 is used for outputting the control signal 2. Specifically, the driving signal 2 is used as a reference capacitor charging and discharging driving signal for controlling the eleventh switch K11 and the twelfth switch K12 to be alternately opened, so as to charge and discharge the reference capacitor Cref. When the voltage across the reference capacitor Cref is at VTL3, the eleventh switch K11 is closed, the twelfth switch K12 is opened, and the reference capacitor Cref is charged based on the resistor R4; when the voltage at two ends of the reference capacitor Cref is increased to VTH3, the signal output by the trigger 2 is overturned, namely VTH3 is the high overturned voltage of the trigger 2; at this time, the eleventh switch K11 is opened, the twelfth switch K12 is closed, and the reference capacitor Cref is discharged based on the resistor R5. When the voltage at two ends of the capacitor Cx to be detected is reduced to VTL3 from VTH3, the signal output by the trigger 2 is inverted again, namely VTL3 is the low inverted voltage of the trigger 2. And the trigger 2 outputs a control signal 2 by circularly reciprocating so that the voltage at two ends of the capacitance Cx to be detected oscillates reciprocally between VTH3 and VTL 3.

In some embodiments, the low inversion voltage VTL1 of the flip-flop 1 and the low inversion voltage VTL3 of the flip-flop 2 are the same, and the values are VTL-B; the high inversion voltage VTH1 of the flip-flop 1 is the same as the high inversion voltage VTH3 of the flip-flop 2, and the values are VTH-B.

It is understood that the arithmetic unit 220 includes an arithmetic unit 1, an arithmetic unit 2, and an arithmetic unit 3. Specifically, the control signal 1 and the drive signal 1 are subjected to signal processing, for example, exclusive or operation processing, by the operator 1 to obtain the charge drive signal 1 of the integration capacitance Cs. And, the charge driving signal 2 of the integrating capacitor Cs is obtained by performing signal processing, such as exclusive or operation, on the control signal 2 and the driving signal 2 by the operator 2. Further, the charge driving signal 1 and the charge driving signal 2 are subjected to signal processing, such as exclusive or operation processing, by the operator 3, to obtain the charge driving signal 3 of the integrating capacitor Cs after the reference channel compensation.

It will be appreciated that the integration unit 230 is configured to charge the integration capacitor Cs according to the charging driving signal 3. Specifically, when the charge driving signal 3 is high, the ninth switch K9 is closed, and the integration capacitance Cs is charged based on the resistor R3, that is, charges are injected into the integration capacitance Cs; when the charge driving signal 3 is low, the ninth switch K9 is turned off, the charge in the integration capacitance Cs is held, the charge is gradually accumulated in the integration capacitance Cs, and the voltage rises with it, waiting for the next charging action of the charge driving signal 3. Along with the continuous accumulation of the charge, the voltage of the integrating capacitor Cs rises stepwise until the charging action of the charging driving signal 3 on the integrating capacitor reaches the preset number of times N, and the Cs voltage remains unchanged.

The data processing unit 240 is configured to perform quantization processing on the voltages across the integrating capacitor Cs. Specifically, the first comparator determines the magnitudes of the voltage Vx at the first input terminal and the reference voltage Vref at the second input terminal, latches the comparison result according to the first clock CLK, and the first counter counts the period of the fourth charging driving signal cs_drive. The result of the counting is taken as first sampling data. When the voltage of the first input terminal is less than the reference voltage Vref of the second input terminal, the tenth switch K10 is kept in an open state. As the charge is continuously accumulated, the voltage of the integrating capacitor Cs increases stepwise until it stabilizes at the reference voltage Vref. When the voltage at the first input terminal is greater than the reference voltage Vref at the second input terminal, the periodic drive signals 1 and 2 are no longer generated. The measurement phase of the capacitance detection circuit has ended. The tenth switch K10 is turned off, resetting the charge in the integrating capacitor Cs, and initializing the voltage across the integrating capacitor Cs to the initial voltage. Preparation is made for accurate measurement of the next detection period. If the voltage at both ends of the integrating capacitor Cs exceeds the reference voltage Vref for a preset time in the measurement stage, the capacitor detection result is forcibly terminated, so that the circuit is prevented from being blocked.

It can be appreciated that the embodiments of the present application provide a chip including the capacitance detection circuit described above.

It can be appreciated that the embodiment of the present application provides a capacitance detection device, including the capacitance detection circuit, where the capacitance detection circuit is configured to perform the capacitance detection method.

It should be noted that in the examples and descriptions of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

While the application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims (18)

1. A capacitance detection circuit, comprising: a capacitor unit to be measured, an operation unit and an integration unit, wherein,

The capacitor unit to be tested is used for outputting a first control signal according to a first driving signal;

An operation unit for determining a first charging drive signal provided to an integration power supply according to the first drive signal and the first control signal;

And the integrating unit is used for generating an integrated voltage according to the first charging driving signal and the charging frequency threshold value provided by the operation unit.

2. The capacitance detection circuit according to claim 1, further comprising: the data processing unit is used for carrying out quantization processing on the integral voltage;

and determining whether the capacitance variation to be measured corresponds to the touch operation result of the user based on the quantification result.

3. The capacitance detection circuit according to claim 1, wherein the capacitance unit to be measured includes at least a capacitance to be measured, a first charge-discharge unit, a first trigger, wherein:

The first charge-discharge unit is used for charging and discharging the capacitor to be tested according to the first driving signal;

the first trigger is used for outputting a first control signal to the operation unit according to the input voltage at two ends of the capacitor to be detected;

wherein the first trigger is a schmitt trigger.

4. The capacitance detection circuit according to claim 1, wherein the arithmetic unit includes at least a first arithmetic unit, wherein the first arithmetic unit is an exclusive-or arithmetic unit;

The first operator processes the first drive signal and the first control signal to determine a first charge drive signal to be supplied to an integration power supply.

5. The capacitance detection circuit according to claim 1, wherein the first drive signal includes a first target drive signal and a second target drive signal, comprising:

When the first driving signal is a first target driving signal, the capacitor unit to be tested charges the capacitor to be tested;

when the first driving signal is a second target driving signal, the capacitor unit to be tested discharges the capacitor to be tested; wherein the first target drive signal and the second target drive signal are inverse signals.

6. The capacitance detection circuit of claim 1, wherein the first charge drive signal comprises a first target charge drive signal and a second target charge drive signal, wherein:

when the first charging driving signal is a first target charging driving signal, the integration unit generates an integrated voltage;

When the first charging driving signal is a second target charging driving signal, no integrated voltage is generated any more and the voltage value of the integrated capacitor is kept unchanged;

wherein the first target charge drive signal and the second target charge drive signal are inverted signals.

7. The capacitance detection circuit according to claim 1, wherein the charge number threshold is used to limit the number of times the integration unit charges the integration capacitance;

When the number of times of charging the integrating capacitor by the integrating unit reaches a threshold value of the number of times of charging, the integrating unit does not charge the integrating capacitor any more.

8. The capacitance detection circuit according to claim 1, wherein the circuit further comprises: a reference capacitance unit;

The reference capacitor unit is used for outputting a second control signal according to a second driving signal;

wherein the first drive signal and the second drive signal are the same drive signal; or the first driving signal and the second driving signal are different driving signals.

9. The capacitance detection circuit according to claim 1, wherein the arithmetic unit further includes at least a second arithmetic unit and a third arithmetic unit.

10. The capacitance detection circuit according to claim 8, wherein the reference capacitance unit includes at least a reference capacitance, a second charge-discharge unit, a second trigger, comprising:

The second charge-discharge unit is used for charging and discharging the reference capacitor according to a second driving signal;

The second trigger is used for outputting a second control signal to a second arithmetic unit according to the input voltage at two ends of the reference capacitor;

Wherein the second trigger is a schmitt trigger.

11. The capacitance detection circuit according to claim 10, wherein the second drive signal includes a third target drive signal and a fourth target drive signal, comprising:

When the second driving signal is a third target driving signal, the second charging and discharging unit charges the reference capacitor;

When the second driving signal is a fourth target driving signal, the second charging and discharging unit discharges the reference capacitor; wherein the third target drive signal and the fourth target drive signal are inverse signals.

12. The capacitance detecting circuit according to claim 9, wherein the second operator performs an operation process on the second driving signal and the second control signal to obtain a second charging driving signal;

The third arithmetic unit carries out arithmetic processing on the first charging driving signal and the second charging driving signal to obtain a third charging driving signal;

wherein the second operator and the third operator are exclusive-or operators.

13. The capacitance detection circuit according to claim 12, wherein the third charging drive signal includes a third target charging drive signal and a fourth target charging drive signal; wherein,

When the third charging driving signal is a third target charging driving signal, the integration unit charges an integration capacitor;

when the third charging driving signal is a fourth target charging driving signal or the number of times of charging the integration capacitor by the third charging driving signal reaches a charging threshold value, the integration unit does not charge the integration capacitor and keeps the voltage of the integration capacitor unchanged; wherein the third target charge driving signal and the fourth target charge driving signal are inverted signals.

14. A capacitance detection method, characterized by being applied to a capacitance detection circuit including any one of claims 1 to 13, the method comprising:

the capacitance unit to be tested outputs a first control signal according to the first driving signal;

The operation unit determines a first charging driving signal provided to an integral power supply according to the first driving signal and the first control signal;

The integration unit generates an integrated voltage according to the first charging driving signal and the charging frequency threshold value provided by the operation unit.

15. The method of claim 14, wherein the method further comprises:

The reference capacitance unit outputs a second control signal according to the second driving signal;

and the data processing unit carries out quantization processing on the integrated voltage and determines whether the capacitance change quantity to be detected corresponds to the touch operation result of the user.

16. The method of claim 15, wherein the arithmetic unit is further configured to determine a second charge drive signal based on the second drive signal and the second control signal,

And determining a third charge drive signal based on the first charge drive signal and the second charge drive signal.

17. A chip comprising the capacitance detection circuit of any one of claims 1 to 13.

18. A capacitance detecting device, characterized by comprising the capacitance detecting circuit according to any one of claims 1 to 13.