CN118198006A

CN118198006A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN118198006A
Application number: CN202211596322.8A
Authority: CN
Inventors: 郑韦志; 李家豪; 廖志成
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2024-06-14

Abstract

A semiconductor device includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate, a passivation layer covering the semiconductor barrier layer, a first gate electrode and a second gate electrode laterally separated and at least partially disposed in the passivation layer, respectively, wherein a first gate length of the first gate electrode is smaller than a second gate length of the second gate electrode along a first direction, and a source electrode and a drain electrode disposed on the semiconductor channel layer, wherein the second gate electrode is electrically connected to the source electrode, and the first gate electrode and the second gate electrode are electrically isolated from each other.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

The present invention relates generally to the field of semiconductors, and more particularly to semiconductor devices including integrated high electron mobility transistors.

Background

In semiconductor technology, group III-V compound semiconductors may be used to form a variety of integrated circuit devices, such as: high power field effect transistors, high frequency transistors or high electron mobility transistors (high electron mobility transistor, HEMT). HEMTs are a type of transistor with two-dimensional electron gas (two dimensional electron gas,2 DEG) that is adjacent to the junction between two materials that differ in energy gap (i.e., the heterojunction). Because HEMTs do not use doped regions as the carrier channel of the transistor, but rather use 2DEG as the carrier channel of the transistor, HEMTs have a variety of attractive characteristics compared to existing Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), such as: high electron mobility and the ability to transmit signals at high frequencies.

HEMTs can be classified as normally-off (normal-on) and normally-on (normal-on), and HEMTs can be affected by processes (e.g., etching) during the process, resulting in poor electrical performance or uniformity. While existing high electron mobility transistors have been generally desirable, they are not satisfactory in all respects.

Disclosure of Invention

In view of the above, the present invention provides a semiconductor device that integrates normally-off and normally-on High Electron Mobility Transistors (HEMTs), and includes two gate electrodes disposed in a passivation layer, wherein the stress of the passivation layer on the first gate electrode and the second gate electrode is different, so as to adjust the threshold voltages of the normally-off and normally-on HEMTs of the semiconductor device.

According to an embodiment of the present invention, a semiconductor device is provided, which includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a passivation layer, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The semiconductor channel layer and the semiconductor barrier layer are arranged on the substrate, the passivation layer covers the semiconductor barrier layer, the first gate electrode and the second gate electrode are laterally separated and are arranged in the passivation layer, wherein the first gate length of the first gate electrode is smaller than the second gate length of the second gate electrode along the first direction, the source electrode and the drain electrode are arranged on the semiconductor channel layer, the second gate electrode is electrically connected to the source electrode, and the first gate electrode and the second gate electrode are electrically isolated from each other.

In order to make the features of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

For a better understanding of the present invention, reference should be made to the drawings and to the detailed description thereof when read in light of the accompanying drawings. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein the present embodiments are illustrated in the accompanying drawings. Furthermore, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and therefore the dimensions of some features in some of the drawings may be exaggerated or reduced in size.

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.

Fig. 2 is an enlarged cross-sectional view of the wire area a of fig. 1, wherein relevant dimensions of some components of the semiconductor device are indicated, according to an embodiment of the present invention.

Fig. 3 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) according to a comparative embodiment of the present invention.

Fig. 5 is a graph of drain current versus gate voltage for HEMTs of some embodiments of the invention.

Fig. 6 is a graph of drain current versus gate voltage for HEMTs of some embodiments of the invention.

Fig. 7 is a graph of drain current and source current versus drain voltage for a HEMT of a comparative embodiment of the invention.

Fig. 8 is a graph of drain current versus gate voltage for a semiconductor device according to an embodiment of the invention.

Fig. 9 is a graph of drain current versus drain voltage for a semiconductor device according to an embodiment of the invention.

The reference numerals are explained as follows:

100 … semiconductor device

100T … high electron mobility transistor

100A … normally-off transistor

100B … normally-on transistor

101 … Substrate

103 … Buffer layer

105 … Semiconductor channel layers

107 … Semiconductor barrier layer

110 … Passivation layer

110T … passivation layer

111 … Gate dielectric layer

112 … Source electrode

114 … Drain electrode

116 … First gate electrode

116-1 … First part

116-2 … Second part

117 … Gate electrode

118 … Second gate electrode

118-1 … Third section

118-2 … Fourth part

T1 … first groove

T2 … second trench

Lg1 … first gate length

Lg2 … second gate length

Lg3 … third gate length

Lg4 … fourth Gate Length

L1 … first distance

L2 … second distance

L3 … third distance

L4 … fourth distance

Lg … gate length

Lsg … source-gate distance

Lgd … gate-drain distance

G. G1, G2 … grid electrode

S, S1S 2 … source

D. D1, D2 … drain

Detailed Description

The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of "a first feature being formed on or over a second feature" may refer to "the first feature being in direct contact with the second feature" or may refer to "there being other features between the first feature and the second feature" such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference numerals and/or text labels. These repeated reference numerals and marks are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.

In addition, for the spatially related narrative terms mentioned in the present invention, for example: "under," "low," "under," "above," "over," "upper," "top," "bottom," and the like, when used in this specification, are defined as a relative relationship of one element or feature to another element(s) or feature(s) in the drawings. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.

Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. The terms "comprises," "comprising," or "having," are used herein to distinguish one element, component, region, layer, and/or section from another element, component, region, layer, and/or section, that does not necessarily require a preceding ordinal number or order of arrangement or method of manufacture. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.

The term "about" or "substantially" as referred to herein generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," what may still be implied by the meaning of "about" or "substantially.

The terms "coupled," "coupled," and "electrically connected" as used herein are intended to encompass any direct or indirect means of electrical connection. For example, if a first element is coupled to a second element, that connection may be directly to the second element or indirectly to the second element through other means of attachment or connection.

In the present invention, the "compound semiconductor (compound semiconductor)" refers to a compound semiconductor containing at least one group III element and at least one group V element. Among them, the group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Further, the "compound semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor, or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (inaias), gallium indium arsenide (InGaAs), the like, or a combination of the above compounds, but are not limited thereto. In addition, a dopant may be included in the compound semiconductor as required, and is a compound semiconductor having a specific conductivity type, for example, an n-type or p-type compound semiconductor. Hereinafter, the compound semiconductor may also be referred to as a III-V semiconductor.

Although the invention is described below by way of specific embodiments, the inventive principles of this patent are applicable to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted are within the knowledge of persons of ordinary skill in the art.

The present invention relates to a semiconductor device integrating normally-off and normally-on High Electron Mobility Transistors (HEMTs) and comprising first and second gate electrodes of different lengths disposed in a compressively stressed passivation layer. The stress of the passivation layer on the first gate electrode is different from that of the second gate electrode, so that the critical voltage of the normally-off HEMT and the normally-on HEMT of the semiconductor device is adjusted.

Fig. 1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the invention, wherein the semiconductor device 100 comprises a substrate 101, and in some embodiments, the substrate 101 may comprise ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire (sapphire), or silicon. When the substrate 101 is made of a material having high hardness, high thermal conductivity, and low electrical conductivity, such as a ceramic substrate, it is more suitable for a high-voltage semiconductor device. The high hardness, high thermal conductivity and low electrical conductivity are compared with a single crystal silicon substrate, and the high voltage semiconductor device is a semiconductor device having an operating voltage higher than 50V. In some embodiments, the substrate 101 may be a semiconductor-on-insulator (semiconductor on insulator, SOI) substrate. In other embodiments, the substrate 101 may be provided by a composite substrate (also referred to as a QST substrate) formed by wrapping a core substrate with a composite material layer, wherein the core substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire or silicon, the composite material layer comprises an insulating material layer and a semiconductor material layer, wherein the insulating material layer may be single-layer or multi-layer silicon oxide, silicon nitride or silicon oxynitride, the semiconductor material layer may be silicon or polysilicon, and the composite material layer on the back of the core substrate is removed through a thinning process, such as a polishing or etching process, so that the back of the core substrate is exposed.

In addition, the semiconductor device 100 further includes a buffer layer 103, a semiconductor channel layer 105, and a semiconductor barrier layer 107 sequentially stacked on the substrate 101 from bottom to top, wherein the buffer layer 103 can be used to reduce the degree of stress or lattice mismatch existing between the substrate 101 and the semiconductor channel layer 105. In some embodiments, a seed layer (nucleation layer) may also be disposed between buffer layer 103 and substrate 101, and a high-resistance layer (HIGH RESISTANCE LAYER) (otherwise known as an electrical isolation layer) may also be disposed between buffer layer 103 and semiconductor channel layer 105. The materials of the seed layer, buffer layer 103, high resistance layer, semiconductor channel layer 105, and semiconductor barrier layer 107 comprise a compound semiconductor, and in some embodiments, the seed layer is, for example, an aluminum nitride (AlN) layer, and buffer layer 103 may be a superlattice (superlattice, SL) structure, for example, comprising a plurality of alternating layers of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN) layers, and the high resistance layer is, for example, a carbon doped gallium nitride (C-GaN) layer, but is not limited thereto. In some embodiments, the semiconductor channel layer 105 is, for example, an undoped gallium nitride (u-GaN) layer, and the semiconductor barrier layer 107 is a compound semiconductor layer having a larger energy gap than the semiconductor channel layer 105, for example, an aluminum gallium nitride (AlGaN) layer, but is not limited thereto. The composition and structural arrangement of the above-described compound semiconductor layers of the semiconductor device 100 may be determined according to various requirements of the electronic element.

Still referring to fig. 1, the semiconductor device 100 further includes a source electrode 112 and a drain electrode 114 disposed on the semiconductor channel layer 105, and in some embodiments, the source electrode 112 and the drain electrode 114 may extend downward into the semiconductor channel layer 105 through the semiconductor barrier layer 107. In other embodiments, the source electrode 112 and the drain electrode 114 may pass through the semiconductor barrier layer 107 and be located on the top surface of the semiconductor channel layer 105. In other embodiments, the source electrode 112 and the drain electrode 114 may be disposed on the top surface of the semiconductor barrier layer 107. According to some embodiments of the present invention, the semiconductor device 100 further comprises a passivation layer 110 covering the semiconductor barrier layer 107 and disposed between the source electrode 112 and the drain electrode 114. The passivation layer 110 may be made of silicon nitride or other dielectric material having a compressive stress, and in some embodiments, the compressive stress of the passivation layer 110 may be, for example, -2.0GPa or higher, the compressive stress of the passivation layer 110 may be adjusted by a deposition process parameter, for example, the compressive stress of the passivation layer 110 may be adjusted by an ac frequency of an applied plasma of a plasma enhanced chemical vapor deposition (PLASMA ENHANCED CHEMICAL vapor deposition (PECVD) process, and the reduction of the ac frequency may result in a compressive stress (compressive stress, stress value < 0), but the invention is not limited thereto.

In addition, the semiconductor device 100 further includes a first gate electrode 116 and a second gate electrode 118 laterally separated, and the first gate electrode 116 is filled in the first trench T1 of the passivation layer 110 and the second gate electrode 118 is filled in the second trench T2 of the passivation layer 110. In addition, along a first direction (e.g., the X-axis direction), the first gate length of the first gate electrode 116 is less than the second gate length of the second gate electrode 118. In some embodiments, the first gate length is about 0.1 microns to about 2.0 microns and the second gate length is about greater than about 2.0 microns and less than or equal to about 5.0 microns. When the first gate length is short enough, for example, 0.1 to 2.0 microns, the passivation layer 110 can generate a compressive stress on the first gate electrode 116, so that a built-in electric field is generated between the semiconductor barrier layer 107 and the semiconductor channel layer 105 to form a depletion region, so that the threshold voltage of the first gate electrode 116 is greater than 0, and the function of the normally-off transistor is achieved. According to some embodiments of the present invention, the semiconductor barrier layer 107 has a flat top surface, and the first gate electrode 116 and the second gate electrode 118 are disposed on the flat top surface of the semiconductor barrier layer 107, so that the first gate electrode 116 can be used to achieve the function of a normally-off transistor without etching the semiconductor barrier layer 107 and the semiconductor channel layer 105 to generate a recess, and thus the semiconductor device of the present invention has no problem of damage to the semiconductor layer and can improve reliability. In addition, when the compressive stress of the passivation layer 110 is increased due to the process parameters or material development, the first gate length of the first gate electrode 116 can be increased, so as to avoid breakdown (punch-through) of the first gate electrode 116, and still enable the threshold voltage of the first gate electrode 116 to be greater than 0. In addition, when the second gate length is long enough, for example, greater than 2.0 micrometers and less than or equal to 5.0 micrometers, the passivation layer 110 does not generate compressive stress on the second gate electrode 118, and does not generate a depletion region, so that the critical voltage of the second gate electrode 118 is less than 0, the function of a normally-on transistor is achieved, and the second gate electrode 118 is not easily broken down and can withstand high voltage.

In addition, the semiconductor device 100 further includes a gate dielectric layer 111 formed conformally (conformally) on the sidewalls and bottom surfaces of the first trench T1 and the second trench T2 and on the top surface of the passivation layer 110 such that the gate dielectric layer 111 is disposed between the first gate electrode 116 and the semiconductor barrier layer 107 and between the second gate electrode 118 and the semiconductor barrier layer 107. In one embodiment, the composition of the gate dielectric layer 111 is, for example, silicon oxide (SiOx), silicon nitride (Si ₃N₄), yttrium oxide (Y ₂O₃), yttrium titanium oxide (Y ₂TiO₅), ytterbium oxide (Yb ₂O₃), hafnium oxide (HfO ₂), zirconium oxide (ZrO ₂), titanium oxide (TiO ₂), aluminum oxide (Al ₂O₃), tantalum oxide (Ta ₂O₅), other dielectric materials, or a combination thereof. In some embodiments, the first gate electrode 116 and the second gate electrode 118 are composed of a metal material, the gate dielectric layer 111 is composed of an insulating material, and the semiconductor barrier layer 107 and the semiconductor channel layer 105 are composed of a semiconductor material to constitute a metal-insulator-semiconductor (MIS) structure.

According to some embodiments of the present invention, the passivation layer 110 may apply a compressive stress to the first gate electrode 116 having a shorter gate length, such that the threshold voltage of the first gate electrode 116 is greater than 0 (Vth > 0) and has the function of a normally-off HEMT. The second gate electrode 118 with a longer gate length is not affected by the compressive stress in the passivation layer 110, and has a threshold voltage less than 0 (Vth < 0), and has the function of a normally-on HEMT. Accordingly, the semiconductor device 100 of the present invention can integrate the functions of the normally-off and normally-on HEMTs, wherein the first gate electrode 116 forms the gate of the normally-off transistor, and the threshold voltage can be controlled by the first gate electrode 116 such that the semiconductor device 100 achieves the function of the normally-off HEMT, and thus the first gate electrode 116 can also be referred to as a control gate (control gate). The second gate electrode 118 forms a gate of the normally-on transistor, and the second gate electrode 118 can block a high drain bias voltage, so that the semiconductor device 100 can withstand high voltage, and thus the second gate electrode 118 can be also referred to as a blocking gate (blocking gate).

Furthermore, according to some embodiments of the present invention, the first gate electrode 116 and the second gate electrode 118 are electrically isolated from each other, and the second gate electrode 118 is electrically connected to the source electrode 112. In one embodiment, the second gate electrode 118 and the source electrode 112 may be electrically coupled to ground, thereby reducing the gate-drain capacitance (Cgd) of the semiconductor device 100 and thus reducing the switching loss (SWITCHING LOSS). In addition, the first gate electrode 116 having a shorter gate length may also reduce the gate-drain coupling area, thereby reducing the parasitic gate-drain capacitance (PARASITIC CGD) of the semiconductor device 100. In addition, since the semiconductor device 100 of the present invention can realize the function of a normally-off element by the first gate electrode 116 and the passivation layer 110 having a short gate length without etching the semiconductor barrier layer 107 and the semiconductor channel layer 105 to form recesses, the conventional damage to the semiconductor barrier layer and the semiconductor channel layer due to the recess formed by etching can be avoided, thereby improving the reliability of the semiconductor device, and avoiding the reduction of the on-resistance (Ron) and further reducing the on-loss (conduction loss).

Fig. 2 is an enlarged cross-sectional view of the wire area a of fig. 1, wherein relevant dimensions of some components of the semiconductor device 100 are indicated, according to an embodiment of the present invention. As shown in fig. 2, in one embodiment, the first gate electrode 116 comprises a first portion 116-1 within the passivation layer 110 and a second portion 116-2 over the passivation layer, the second gate electrode 118 comprises a third portion 118-1 within the passivation layer 110 and a fourth portion 118-2 over the passivation layer 110, wherein the first portion 116-1 and the third portion 118-1 are laterally separated, the second portion 116-2 and the fourth portion 118-2 are laterally separated, and along a first direction (e.g., X-axis direction), the first portion 116-1 of the first gate electrode 116 has a first gate length Lg1, the third portion 118-1 of the second gate electrode 118 has a second gate length Lg2, the second portion 116-2 of the first gate electrode 116 has a third gate length Lg3, and the fourth portion 118-2 of the second gate electrode 118 has a fourth gate length Lg4, wherein the fourth portion 118-2 of the second gate electrode 118 conforms to the fourth gate length Lg2 of the fourth gate electrode 118 as a result of the conductive material is deposited in the second trench T2 of the passivation layer 110. According to some embodiments of the invention, the first gate length Lg1 is less than the second gate length Lg2 and the third gate length Lg3 is less than the fourth gate length Lg4. In one embodiment, the first gate length Lg1 is greater than 0 microns and less than 1 micron and the second gate length Lg2 is greater than 1 micron and less than or equal to 3 microns. In one embodiment, the first gate length Lg1 is, for example, 0.1, 0.5, 0.8 micrometers (μm), and the second gate length Lg2 is, for example, 1.5, 2.0, 3.0 micrometers (μm).

In addition, along the first direction (for example, the X-axis direction), a first distance L1 is provided between the first gate electrode 116 and the source electrode 112, a second distance L2 is provided between the second gate electrode 118 and the drain electrode 114, and the first distance L1 is smaller than the second distance L2, and the first distance L1 is, for example, 2 micrometers to 4 micrometers. In addition, the first gate electrode 116 and the second gate electrode 118 have a third distance L3 therebetween, the third distance L3 is, for example, 2 micrometers to 4 micrometers, the first distance L1 and the third distance L3 may both be in the range of 2 micrometers to 4 micrometers, and the relationship therebetween may be greater than, less than, or equal to. In addition, when the third distance L3 and the first distance L1 are less than 2 microns, the passivation layer 110 cannot exert a compressive stress on the first gate electrode 116, and when the third distance L3 and the first distance L1 are greater than 4 microns, the device size is increased. In addition, the first gate electrode 116 and the drain electrode 114 have a fourth distance L4 therebetween, and the second distance L2 between the second gate electrode 118 and the drain electrode 114 is smaller than the fourth distance L4, i.e., the second gate electrode 118 (blocking gate) is closer to the drain electrode 114 than the first gate electrode 116 (control gate), wherein the first gate electrode 116 is located between the source electrode 112 and the second gate electrode 118, and the second gate electrode 118 is located between the first gate electrode 116 and the drain electrode 114.

Furthermore, in one embodiment, the first gate electrode 116 and the second gate electrode 118 are different in composition. The first gate electrode 116 has a composition such as a metal, such as nickel (Ni), gold (Au), platinum (Pt), tungsten (W), titanium (Ti), aluminum (Al), molybdenum (Mo), or a multi-layered stack structure of the foregoing metal layers, polysilicon (polysilicon), or metal silicide (silicide), such as a silicide of the foregoing metal. The second gate electrode 118 has a composition of, for example, titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), gold (Au), or a multi-layered stack structure of the foregoing metal layers. In some embodiments, the compositions of the source electrode 112, the drain electrode 114, and the second gate electrode 118 are the same, and the compositions of the second gate electrode 118, the source electrode 112, and the drain electrode 114 are, for example, titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), gold (Au), or a multi-layered stack structure of the foregoing metal layers. In another embodiment, the first gate electrode 116 and the second gate electrode 118 may have the same composition, and the first gate electrode 116 and the second gate electrode 118 may have a composition of, for example, titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), gold (Au), or a multi-layered stack structure of the foregoing metal layers.

Fig. 3 is an equivalent circuit diagram of a semiconductor device 100 according to an embodiment of the present invention, and as shown in fig. 3, the semiconductor device 100 includes a normally-off transistor (HEMT) 100A and a normally-on transistor (HEMT) 100B to form a cascode (cascode) normally-off semiconductor device. In one embodiment, the first gate electrode 116 of fig. 1 forms the gate G1 of the normally-off transistor 100A, the second gate electrode 118 forms the gate G2 of the normally-off transistor 100B, and the drain D1 of the normally-off transistor 100A is electrically connected to the source S2 of the normally-on transistor 100B (the semiconductor channel layer 107 in fig. 1 is electrically connected to the source S2 in an equivalent manner to the drain D1, and thus not shown), the gate G2 of the normally-on transistor 100B is electrically connected to the source S1 of the normally-off transistor 100A, and the source S1 of the normally-off transistor 100A is electrically coupled to ground, such that the gate G2 of the normally-on transistor 100B is also electrically coupled to ground. As shown in fig. 3, the circuit of the semiconductor device 100 has three terminals, i.e., the gate G is provided by the gate G1 of the normally-off transistor 100A, the source S is provided by the source S1 of the normally-off transistor 100A, and the drain D is provided by the drain D2 of the normally-on transistor 100B. According to an embodiment of the present invention, the gate G1 of the normally-off transistor 100A may be used as a control gate to determine the threshold voltage (Vth) of the semiconductor device 100, and the gate G2 of the normally-on transistor 100B may be used as a blocking gate to increase the breakdown voltage of the semiconductor device 100. In some embodiments, the semiconductor device 100 may withstand high voltages of 600 volts (V) or above 600V.

Fig. 4 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) 100T according to a comparative embodiment of the present invention, the HEMT 100T comprises a substrate 101, a buffer layer 103, a semiconductor channel layer 105 and a semiconductor barrier layer 107 stacked on the substrate 101 in this order from top, a source electrode 112 and a drain electrode 114 passing through the semiconductor barrier layer 107 and disposed in the semiconductor channel layer 105, a passivation layer 110T covering the semiconductor barrier layer 107, the source electrode 112 and the drain electrode 114, a gate electrode 117 disposed within the passivation layer 110T, and a gate electrode 117 having a gate length Lg within the passivation layer 110T along a first direction (e.g., X-axis direction), a source-gate distance Lsg between the source electrode 112 and the gate electrode 117, and a gate-drain distance Lgd between the gate electrode 117 and the drain electrode 114. A gate dielectric layer 111 is formed in the trench of the passivation layer 110T and on the top surface thereof, with the gate dielectric layer 111 being located between the gate electrode 117 and the semiconductor barrier layer 107. The HEMT 100T of fig. 4 is used to illustrate the effect of different gate lengths Lg in the compressively stressed and non-compressively stressed passivation layer 110T and the electrical behavior of different gate lengths Lg in the compressively stressed passivation layer 110T.

Fig. 5 is a graph of drain current I _DS versus gate voltage V _GS for HEMT 100T according to some embodiments of the present invention, which is a plot of compressive stress (e.g., compressive stress = -2 GPa) and non-compressive stress (e.g., compressive stress =0gpa) for passivation layer 110T, respectively, with gate length Lg of 0.1 micrometers (μm), source-gate distance Lsg of 2.0 micrometers (μm), and gate-drain distance Lgd of 2.0 micrometers (μm). As shown in fig. 5, when the gate length Lg is 0.1 μm and the voltage curve of the drain current I _DS corresponding to the gate voltage V _GS is within the passivation layer 110T without compressive stress, the gate voltage V _GS corresponding to the drain current I _DS equal to 1e-7 amperes/millimeter (a/mm) is smaller than 0, and thus the threshold voltage (Vth) is smaller than 0. When the gate length Lg is 0.1 μm and the voltage curve of the drain current I _DS corresponding to the gate voltage V _GS is within the passivation layer 110T under compressive stress, the drain current I _DS is equal to 1e-7 amperes/millimeter (a/mm) and the corresponding gate voltage V _GS is greater than 0, so the threshold voltage (Vth) is greater than 0. As can be seen from fig. 5, when the gate length Lg is 0.1 μm, the passivation layer 110T having compressive stress can apply compressive stress to the gate electrode 117 having the gate length Lg of 0.1 μm so that the threshold voltage (Vth) thereof is changed from less than 0 to greater than 0, compared with the gate electrode disposed in the passivation layer 110T having no compressive stress.

Fig. 6 is a graph of drain current I _DS versus gate voltage V _GS for a HEMT 100T according to some embodiments of the present invention, which is a plot of compressive and non-compressive stress for a passivation layer 110T, respectively, and a gate length of about 1-3 microns (e.g., 3.0 μm). As shown in fig. 6, no matter the gate electrode 117 is disposed in the passivation layer 110T with or without compressive stress, the drain current I _DS corresponds to the gate voltage V _GS, and the drain current I _DS is equal to 1e-7 amperes/millimeter (a/mm), and the corresponding gate voltage V _GS is less than 0, so the threshold voltage (Vth) is less than 0. As can be seen from fig. 6, when the gate length Lg is 3.0 μm, the passivation layer 110T with or without compressive stress cannot exert a compressive stress effect on the gate electrode 117, and the threshold voltage (Vth) cannot be changed from less than 0 to greater than 0.

Fig. 7 Is a graph showing the drain current Id and the source current Is of the HEMT 100T of a comparative example with respect to the drain voltage V _DS, the gate length Lg being exemplified by 0.1 micrometers (μm) and 3.0 micrometers (μm), and the passivation layer 110T having a compressive stress, the gate voltage Vg applied in this example being-6V, such that the HEMT 100T of the comparative example Is in an off state (off). As shown in fig. 7, when the gate length Lg Is less than 1 micron, the drain current Id and the source current Is sharply increased when the drain voltage V _DS Is 100V, which means that the voltage of 100V or more cannot be tolerated when the gate length Lg Is less than 1 micron (for example, 0.1 μm). When the gate length Lg Is greater than 1 micrometer (for example, 3.0 μm), the drain current Id and the source current Is can maintain a stable low current at the drain voltage V _DS of 600V, which means that a high voltage of 600V or more can be tolerated at the gate length Lg of 3.0 μm.

As can be seen from fig. 5 and 6, the compressively stressed passivation layer can apply compressive stress to the gate electrode with a relatively short gate length, e.g., 0.1 μm to 1.0 μm, making the HEMT a normally off transistor with a threshold voltage (Vth) greater than 0. In addition, the passivation layer having compressive stress cannot apply compressive stress to the gate electrode having a long gate length, for example, greater than 1.0 μm, so that the HEMT becomes a normally-on transistor having a threshold voltage (Vth) of less than 0. In addition, as can be seen from fig. 7, a gate electrode having a shorter gate length, for example, 0.1 μm, can provide the function of a normally-off transistor, while a gate electrode having a longer gate length, for example, 3.0 μm, can provide the function of a normally-on transistor, and can withstand a higher voltage, for example, 600V or more.

Fig. 8 is a graph of drain current I _DS versus gate voltage V _GS for a semiconductor device 100 according to an embodiment of the invention, and referring to fig. 1, the semiconductor device 100 includes a first gate electrode 116 and a second gate electrode 118 disposed within a compressively stressed passivation layer 110, in an embodiment, the first gate electrode 116 has a first gate length of 0.1 micrometers (μm) and the second gate electrode 118 has a second gate length of 3.0 micrometers (μm), a gate voltage V _GS is applied to the first gate electrode 116, and the second gate electrode 118 is electrically connected to the source electrode 112 and further electrically coupled to ground. As can be seen from fig. 8, when the gate voltage V _GS applied to the first gate electrode 116 is a negative bias or 0V, the generated drain current I _DS is very low, about 1e-12 amperes/millimeter (a/mm); when the gate voltage V _GS applied to the first gate electrode 116 is a positive bias, the resulting drain current I _DS increases sharply, and the application of 1V increases the current from about 1e-12A/mm to about 1e-4A/mm, which means that the first gate electrode 116 of the semiconductor device 100 can realize the operation of a normally-off transistor.

Fig. 9 is a graph of drain current Id versus drain voltage Vd for the semiconductor device 100 according to an embodiment of the present invention, and referring to fig. 1, the semiconductor device 100 includes a first gate electrode 116 and a second gate electrode 118 disposed in the compressively stressed passivation layer 110, in an embodiment, the first gate electrode 116 has a first gate length of 0.1 micrometers (μm), the second gate electrode 118 has a second gate length of 3.0 micrometers (μm), the gate voltage Vg is-6V and is applied to the first gate electrode 116, and the second gate electrode 118 is electrically connected to the source electrode 112 and further electrically coupled to the ground. As can be seen from fig. 9, when the drain voltage Vd is in the range of more than 0V to less than 600V, the drain current Id is maintained at about 1e-8A/mm to 1e-7A/mm, and when the drain voltage Vd is more than 600V, the drain current Id is rapidly increased to 0.01A/mm, which means that the second gate electrode 118 of the semiconductor device 100 can achieve the capability of blocking high voltage, for example, the breakdown voltage of 600V can be achieved when the second gate length is 3.0 micrometers (μm), so that the breakdown voltage of the semiconductor device 100 can be increased by the second gate electrode 118, which makes it suitable for high voltage applications.

According to some embodiments of the present invention, a semiconductor device incorporates normally-off and normally-on High Electron Mobility Transistors (HEMTs) including first and second gate electrodes of different lengths disposed in a passivation layer. And the stress values of the passivation layer on the first gate electrode and the second gate electrode are different, so that the critical voltages of the normally-off HEMT and the normally-on HEMT of the semiconductor device are adjusted.

According to some embodiments of the present invention, the passivation layer has a compressive stress on the first gate electrode such that the threshold voltage of the first gate electrode is greater than 0 (Vth > 0), has a function of a normally-off transistor, and can enhance the switching speed of the semiconductor device. The passivation layer has no compressive stress on the second gate electrode, so that the threshold voltage of the second gate electrode is less than 0 (Vth < 0), has the function of a normally-on transistor, and can improve the breakdown voltage of the semiconductor device.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A semiconductor device, comprising:

a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate;

a passivation layer covering the semiconductor barrier layer;

A first gate electrode and a second gate electrode laterally separated and at least partially disposed within the passivation layer, respectively, wherein a first gate length of the first gate electrode is smaller than a second gate length of the second gate electrode along a first direction; and

And a source electrode and a drain electrode disposed on the semiconductor channel layer, wherein the second gate electrode is electrically connected to the source electrode, and the first gate electrode and the second gate electrode are electrically isolated from each other.

2. The semiconductor device of claim 1, wherein the first gate length is 0.1 microns to 2 microns.

3. The semiconductor device according to claim 1, wherein the second gate length is greater than 2 microns and less than or equal to 5 microns.

4. The semiconductor device according to claim 1, wherein the first gate electrode is located between the source electrode and the second gate electrode, and the second gate electrode is located between the first gate electrode and the drain electrode.

5. The semiconductor device of claim 1, further comprising a gate dielectric layer disposed between the first gate electrode and the semiconductor barrier layer and between the second gate electrode and the semiconductor barrier layer.

6. The semiconductor device of claim 5, wherein the first gate electrode is filled in a first trench of the passivation layer, the second gate electrode is filled in a second trench of the passivation layer, and the gate dielectric layer is disposed in the first trench and the second trench, and on a top surface of the passivation layer.

7. The semiconductor device of claim 5, wherein the passivation layer comprises silicon nitride and the gate dielectric layer comprises silicon oxide, silicon nitride, yttrium oxide, yttrium titanium oxide, ytterbium oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, tantalum oxide, or a combination of the foregoing.

8. The semiconductor device of claim 1, wherein the first gate electrode forms a gate of a normally-off transistor, the second gate electrode forms a gate of a normally-on transistor, and a drain of the normally-off transistor is electrically connected to a source of the normally-on transistor.

9. The semiconductor device of claim 1, wherein a first distance between the first gate electrode and the source electrode is less than a second distance between the second gate electrode and the drain electrode.

10. The semiconductor device of claim 9, wherein a third distance between the first gate electrode and the second gate electrode is 2 microns to 4 microns, the first distance being 2 microns to 4 microns.

11. The semiconductor device of claim 1, wherein the semiconductor barrier layer has a planar top surface and the first gate electrode and the second gate electrode are disposed on the planar top surface.

12. The semiconductor device of claim 1, wherein the first gate electrode comprises a first portion located within the passivation layer and a second portion located above the passivation layer, the second gate electrode comprises a third portion located within the passivation layer and a fourth portion located above the passivation layer, the second portion and the fourth portion are laterally separated, and a length of the second portion is less than a length of the fourth portion along the first direction.

13. The semiconductor device according to claim 1, wherein a composition of the first gate electrode and the second gate electrode is the same.

14. The semiconductor device of claim 1, wherein the source electrode and the second gate electrode are electrically coupled to ground.

15. The semiconductor device according to claim 1, wherein the first gate electrode is a control gate.

16. The semiconductor device according to claim 15, wherein a distance between the second gate electrode and the drain electrode is smaller than a distance between the first gate electrode and the drain electrode.