CN118192928A - Dual-tone ordering method based on FPGA and FPGA - Google Patents

Abstract

The application discloses an FPGA. The FPGA is used for double-tone ordering of 2 n data, n is a positive integer, and the FPGA comprises: the first double-tone ordering module is used for executing double-tone ordering of 16 data; the second double-tone ordering module is used for executing double-tone ordering of 2-m data, wherein m is a positive integer, and n is more than m > n/2; the first double-tone ordering module inputs 16 data for multiple times in sequence each time to provide 2 n data, and the second double-tone ordering module is repeatedly invoked along with the running time to repeatedly execute double-tone ordering of the 2m data, so that double-tone ordering of the 2 n data is realized. The application also discloses a double-tone ordering method based on the FPGA. According to the application, the first double-tone ordering module is used for performing double-tone ordering of 16 data, and the second double-tone ordering module is used for performing double-tone ordering of 2-m data, so that double-tone ordering of 2-n data is realized, and the problem that more idle resources are occupied when FPGA is used for double-tone ordering is solved.

Description

Dual-tone ordering method based on FPGA and FPGA

Technical Field

The disclosed embodiments of the present application relate to the field of electronics, and more particularly, to a dual tone ordering method based on an FPGA and the FPGA.

Background

Some current calculations require ordering of data, and there are many ordering algorithms, such as bubbling ordering, merging ordering, double-tone ordering, etc. The dual-tone ordering can be realized through the FPGA device, but if the ordering array is longer, the overall ordering consumes a large amount of resources, and if the data is not pipeline input, the overall idle resources are more, so that the FPGA resource consumes a large amount of pressure.

Disclosure of Invention

According to the embodiment of the application, the application provides the FPGA and the double-tone ordering method based on the FPGA, so as to solve the problem that more idle resources are occupied when the FPGA is utilized for double-tone ordering.

The first aspect of the application discloses an FPGA for double-tone ordering of 2 n data, n being a positive integer, comprising: the first double-tone ordering module is used for executing double-tone ordering of 16 data; the second double-tone ordering module is used for executing double-tone ordering of 2-m data, wherein m is a positive integer, and n is more than m > n/2; the first double-tone ordering module inputs the 16 data for multiple times in turn according to each time of inputting the 16 data to provide the 2 n data for the second double-tone ordering module, and the second double-tone ordering module is repeatedly invoked along with the running time to repeatedly execute the double-tone ordering of the 2m data, thereby realizing the double-tone ordering of the 2 n data.

In some embodiments, the FPGA further comprises: the RAM is used for caching intermediate data when the double-tone ordering of the 2 ^{^} n data is executed; the RAM is repeatedly called with the running time to buffer intermediate data when the double-tone ordering of the 2 ^{^} n data is executed.

In some embodiments, the first double-tone ordering module includes a sequence sub-module for ordering the 16 data into a double-tone sequence and an ordering sub-module for ordering the double-tone sequence.

In some embodiments, the RAM is used to cache the 16 data entered by the first double-tone ordering module at a time.

In some embodiments, the second bi-level ordering module includes an (i+1) th pair of tone sub-modules, wherein the (i+1) th pair of tone sub-modules is configured to exchange 2 ^{^} j data in a bisection comparison, i is 0 to n-m, j is n to m, j=n when i=0, and j=m when i=n-m; wherein, according to a preset sequence, each (i+1) th opposite tone sub-module is called 2^i times to realize double tone sequencing of the 2 ^{^} m data.

In some embodiments, after the (i+1) th call sub-module is called 2^i times, the RAM is called to cache the ordering data output by the (i+1) th call sub-module called 2^i times.

In some embodiments, when n=6, m=4, the second double-tone ordering module includes a first pair of tone sub-modules for halving comparison interchange of 2 ^{^} data, a second pair of tone sub-modules for halving comparison interchange of 2 ^{^} 5 data, and a third pair of tone sub-modules for halving comparison interchange of 2 ^{^} data; the first pair of the tone sub-modules is called 1 time, the second pair of the tone sub-modules is called 2 times, and the third pair of the tone sub-modules is called 4 times according to a preset sequence, so that double tone ordering of the 2 ^{^} m data is achieved.

In some embodiments, the preset sequence includes: the order in which the second pair of tuning sub-modules is called 2 times, the third pair of tuning sub-modules is called 4 times, and the first pair of tuning sub-modules is called 1 time.

In some embodiments, the first double-tone ordering module includes a sequence sub-module for ordering the 16 data into a double-tone sequence and an ordering sub-module for ordering the double-tone sequence; wherein the third pair of tuning sub-modules is multiplexed by the sorting sub-module.

The second aspect of the application discloses a double-tone ordering method based on an FPGA, wherein the FPGA is the FPGA in the first aspect, is used for double-tone ordering of 2 ^{^} n data, and comprises the following steps: sequentially inputting the 16 data for a plurality of times according to each time of inputting to provide 2 ^{^} n data; the double-tone ordering of 2 ^{^} m data is repeatedly performed, so that the double-tone ordering of 2 ^{^} n data is realized.

The application has the beneficial effects that: the method comprises the steps of executing double-tone ordering of 16 data through a first double-tone ordering module, executing double-tone ordering of 2-m data through a second double-tone ordering module, wherein m is a positive integer, and n is larger than m and is larger than n/2, wherein the first double-tone ordering module sequentially inputs the 16 data for a plurality of times according to each time to provide the 2-n data, and the second double-tone ordering module is repeatedly invoked along with running time to repeatedly execute the double-tone ordering of the 2-m data, so that the double-tone ordering of the 2-n data is realized, and the problem that more idle resources are occupied when the double-tone ordering is performed through an FPGA is solved.

Drawings

The application will be further described with reference to the accompanying drawings and embodiments, in which:

FIG. 1 is a schematic diagram of the structure of an FPGA according to one embodiment of the present application;

FIG. 2 is a schematic diagram of the structure of an FPGA in accordance with yet another embodiment of the present application;

FIG. 3 is a schematic diagram of the effect of a sequence sub-module according to an embodiment of the application;

FIG. 4 is a schematic diagram of the effect of the sorting sub-module according to an embodiment of the present application;

FIG. 5 is a partial flow diagram of a call pair calling sub-module according to one embodiment of the application;

FIG. 6 is a schematic diagram showing the effect of an embodiment of the present application on a tuning sub-module;

FIG. 7 is a schematic diagram showing the effect of a further pair of tuning sub-modules according to an embodiment of the present application;

fig. 8 is a flow chart of a dual tone ordering method based on FPGA according to an embodiment of the present application.

Detailed Description

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The term "and/or" in the present application is merely an association relation describing the association object, and indicates that three kinds of relations may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. Further, "a plurality" herein means two or more than two. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C. Furthermore, the terms "first," "second," and "third" in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.

In order to make the technical scheme of the present application better understood by those skilled in the art, the technical scheme of the present application will be further described in detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an FPGA according to an embodiment of the application. The FPGA10 is used for double-tone ordering of 2 ^{^} n data, where n is a positive integer, that is, a MAX sequence and a MIN sequence are obtained by comparing a double-tone sequence composed of 2 ^{^} n data, and an ordered sequence of 2 ^{^} n data is obtained by processing with a double-tone merger. It should be noted that those skilled in the art will appreciate that 2 ^{^} n represents the power n of 2, e.g., 2 ^{^} represents the power 7 of 2, i.e., 128.

Specifically, the FPGA10 includes a first double-tone sequencing module 11 and a second double-tone sequencing module 12, and the first double-tone sequencing module 11 and the second double-tone sequencing module 12 are connected.

The first double-tone ordering module 11 is configured to perform double-tone ordering of 16 data, for example, an original sequence composed of 16 data, perform double-tone ordering of 16 data, i.e., divide the original sequence into two halves with equal length, for example, divide the original sequence into a middle sequence X and a middle sequence Y, compare 8 data in the middle sequence X with 8 data in the middle sequence Y one by one according to the original sequence, for example, use a comparator to perform a comparison operation, where the comparator is not specifically limited, i.e., data ai is compared with data a _i+n (i < n), the larger one is placed in a MAX sequence, the smaller one is placed in a MIN sequence, and thus the obtained MAX and MIN sequences are still double-tone sequences, and any element in the MAX sequence is not less than any element in the MAX sequence, i.e., double-tone ordering of 16 data at a time is completed.

The second bi-level ordering module 12 is configured to perform bi-level ordering of 2≡m data, where m is a positive integer, and n > m > n/2, for example, when n=7, the FPGA10 is used for bi-level ordering of 2 ^{^} data, and the first bi-level ordering module 11 is configured to perform bi-level ordering of 16 data for each 16 data elements in 2 ^{^} data, where the second bi-level ordering module 12 is configured to perform bi-level ordering of 2≡m data, for example, m may be equal to 3 or 4, and if m=3, the second bi-level ordering module 12 is configured to perform bi-level ordering of 2^3 data, that is, perform bi-level ordering of 8 data for each 8 data elements in 2 ^{^} data, respectively.

The first double-tone ordering module 11 inputs 16 data in turn for multiple times according to each time to provide 2 n data to the second double-tone module 12, and the second double-tone ordering module 12 is repeatedly invoked along with the running time to repeatedly execute double-tone ordering of the 2m data, thereby realizing double-tone ordering of the 2 n data.

The first double-tone ordering module 11 inputs 16 data each time to provide 2n data, for example, n=7, the first double-tone ordering module 11 inputs 16 data each time to provide 8 times, that is, the first double-tone ordering module 11 inputs 16 data each time to provide 8 double-tone sequences of 16 data of 2^7 data to the second double-tone module 12, the second double-tone ordering module 12 is repeatedly invoked with the running time to repeatedly perform double-tone ordering of 2m data, for example, if m=3, the second double-tone ordering module 12 is repeatedly invoked with the running time to repeatedly perform double-tone ordering of 2^3 data, thereby realizing double-tone ordering of 2^7 data.

In this embodiment, the first double-tone ordering module performs double-tone ordering of 16 data, and the second double-tone ordering module performs double-tone ordering of 2≡m data, where m is a positive integer and n > m > n/2, where the first double-tone ordering module sequentially inputs 16 data each time to provide 2≡n data, and the second double-tone ordering module is repeatedly invoked along with running time to repeatedly perform double-tone ordering of 2≡m data, thereby implementing double-tone ordering of 2≡n data, and solving the problem of occupying more idle resources when performing double-tone ordering by using FPGA.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an FPGA according to another embodiment of the application. The FPGA10 includes a first double-tone ordering module 11, a second double-tone ordering module 12, and a RAM13 (Random Access Memory ), the first double-tone ordering module 11 is connected with the RAM13, and the second double-tone ordering module 12 is connected with the RAM 13. The first double-tone ordering module 11 is used for executing double-tone ordering of 16 data; the second double-tone ordering module 12 is used for performing double-tone ordering of 2≡m data, wherein m is a positive integer, and n > m > n/2; the RAM13 is configured to buffer intermediate data generated when the first double-tone ordering module 11 is configured to perform double-tone ordering of the 2n data, for example, intermediate data generated when the second double-tone ordering module 12 is configured to perform double-tone ordering of the 2n data, or intermediate data generated when the RAM13 is configured to be repeatedly called with running time, for example, during the double-tone ordering of the 16 data by the first double-tone ordering module 11 or during the double-tone ordering of the 2n data by the second double-tone ordering module 12, so as to implement buffer intermediate data generated when the second double-tone ordering of the 2n data is performed.

In some embodiments, the first double-tone ordering module includes a sequence sub-module and an ordering sub-module, wherein the sequence sub-module is configured to arrange 16 data into a double-tone sequence, and the ordering sub-module is configured to order the double-tone sequence.

Taking the first double-tone sequencing module 11 of the FPGA10 as an example for illustration, the first double-tone sequencing module 11 may include a sequence sub-module and a sequencing sub-module, where the sequence sub-module is configured to arrange 16 data into a double-tone sequence, as shown in fig. 3, and fig. 3 is an effect schematic diagram of the sequence sub-module according to an embodiment of the present application, the sequence sub-module includes a module a1, a module a2 and a module a3, where 16 straight lines respectively correspond to 16 data, where the 16 data may be 16 numbers with different sizes, for example, may be the original sequence "65,9,5,24,6,30,7,8,20,10,28,19,35,3,15,40" in turn, the length of the sub-sequence is set to 2 in the module a1, for example, the first sequence may be "65,9", and the sub-sequences are sequenced in turn in order of monotonically increasing, monotonically decreasing, to obtain the intermediate sequences 1"9,65,24,5,6,30,8,7,10,

20,28,19,3,35,40,15"; Combining the subsequences with the length of 2 in the module a2 based on the intermediate sequence 1, wherein the length of the subsequences is 2 times that of the atomic sequence, such as the subsequence '9,65,24,5' with the length of 4, respectively reordering, and the monotonicity of the subsequences is monotonically increasing and monotonically decreasing in sequence to obtain intermediate sequences 2 '5, 9,24,65,30,8,7,6,10,19,20,28,40,35,15 and 3'; the subsequence of length 4 is further merged in module a3 based on intermediate sequence 2 to obtain a word sequence of length 8, e.g. subsequence "5,9,24,65,30,8,7,6,", and reordered to obtain a monotonically increasing sequence and a monotonically decreasing sequence, i.e. "5,6,7,8,9,24,30,65", "40,35,28,20,19,15,10,3", respectively, to obtain a bi-tone sequence a "5,6,7,8,9,24,30,65,40,35,28,20,19,15,10,3", i.e. 16 data are arranged into a bi-tone sequence by the sequence sub-module.

The sorting sub-module is configured to sort the double-tone sequences, that is, merge the double-tone sequences by the sorting sub-module, as shown in fig. 4, fig. 4 is an effect schematic diagram of the sorting sub-module according to the embodiment of the present application, where the sorting sub-module includes a module b1, a module b2, a module b3, and a module b4. Based on the double-tone sequence A '5,6,7,8,9,24,30,65,40,35,28,20,19,15,10,3', in a module b1, comparing and sequencing the ith data and the (i+8) th data in the double-tone sequence A according to a monotonically increasing order to obtain an intermediate sequence 3 '5, 6,7,8,9,15,10,3,40,35,28,20,19,24,30, 65'; in a module b2, dividing the intermediate sequence 3 into two subsequences with the length of 8, and comparing and sequencing the ith data and the (i+4) th data in the subsequences with the length of 8 according to a monotonically increasing sequence to obtain an intermediate sequence 4; in the module b3, dividing the intermediate sequence 4 into four subsequences with the length of 4, and comparing and sequencing the ith data and the (i+2) th data in the subsequences with the length of 4 according to a monotonically increasing sequence to obtain an intermediate sequence 5; in the module B4, the intermediate sequence 5 is divided into eight subsequences with the length of 2, the subsequences with the length of 2 are compared and sequenced according to the monotonically increasing sequence, and the double-tone sequencing result B '3,5,6,7,8,9,10,15,19,20,24,28,30,35,40,65' of 16 data is obtained through integration, namely, the double-tone sequences are sequenced through the sequencing submodule.

In some embodiments, RAM is used to cache 16 data inputs at a time by the first double-tone ordering module.

Continuing to take the FPGA10 as an example, the RAM13 is configured to buffer 16 data input by the first double-tone ordering module 11 each time, that is, when the first double-tone ordering module 11 performs double-tone ordering of 16 data, the first double-tone ordering module sequentially inputs 16 data for multiple times, for example, when n=7, the first double-tone ordering module 11 sequentially inputs 16 data for 8 times each time, so as to provide a double-tone sequence of 8 16 data of 2^7 data to the second double-tone module 12, where the RAM13 may be configured to buffer 16 data input by the first double-tone ordering module 11 sequentially for 8 times, for example, the sequence sub-module may arrange 16 data into a double-tone sequence a generated by the double-tone ordering sub-module, or may be an ordering result B obtained by the ordering sub-module by ordering the double-tone sequence a, that is, the double-tone sequence a and the ordering result B are buffered in the RAM13, so as to be repeatedly called along with the running time.

In some embodiments, the second bi-level ordering module includes an (i+1) th pair of tone sub-modules, wherein the (i+1) th pair of tone sub-modules is used to perform halving comparison exchange on 2^j data, i is 0 to n-m, j is n to m, j=n when i=0, and j=m when i=n-m; wherein, according to the preset sequence, each (i+1) th opposite tone sub-module is called 2^i times to realize the double tone ordering of 2m data.

Continuing with the above example of the second bi-tone ordering module 12 of the FPGA10, the second bi-tone ordering module 12 includes a preset number of opposite-tone sub-modules, when the FPGA10 is utilized to perform bi-tone ordering of 2 ^{^} n data, a bi-tone ordering module of 2m data is set, where m is a positive integer and n > m > n/2, and further, 1 opposite-tone sub-module of 2n data, 2 opposite-tone sub-modules of 2 (n-1) data are required to be called, wherein the second bi-tone ordering module 12 includes an (i+1) th opposite-tone sub-module, the (i+1) th opposite-tone sub-module is used to perform halving comparison exchange on 2^j data, i is 0 to n-m, j is n to m, and when i=0, j=n, when i=n-m, j=m, for example, n=7, m=5, when performing the double-tone ordering of 2 ^{^} 7 data using the FPGA10, a double-tone ordering module of 2^5 data is set, where i is 0 to 2, j is 5 to 7, when i=0, j=7, when i=2, j=5, i.e., the second double-tone ordering module 12 includes 3 pairs of tone sub-modules, i.e., the first pair of tone sub-modules may be a 2^7 data tone module, the second pair of tone sub-modules may be a 2-to-6 data tone module, and the third pair of tone sub-modules may be a 2^5 data tone module, wherein the first pair of tone sub-modules may be used to perform a half-comparison interchange of 2^7 data, the second pair of tone sub-modules may be used to perform a half-comparison interchange of 2-to 6 data, a third pair of tone sub-modules may be used to exchange 2^5 data in half-comparison. It should be noted that, as those skilled in the art can understand, a comparator is required to be used when performing the half-comparison exchange, and the present application is not limited to the comparator specifically.

Wherein, according to the preset sequence, each (i+1) th pair of tone sub-modules is called 2^i times, for example, when the FPGA10 is used for carrying out double-tone sequencing of 2 ^{^} data, a double-tone sequencing module of 2^5 data is set, at this time, the second double-tone sequencing module 12 includes 3 pairs of tone sub-modules, for example, the first pair of tone sub-modules may be 2^7 data tone modules, the second pair of tone sub-modules may be 2≡6 data tone modules, and the third pair of tone sub-modules may be 2^5 data tone modules, that is, 128 data tone modules, 64 data tone modules, and 32 data tone modules. According to a preset sequence, each (i+1) th pair of tone sub-modules is called 2^i times to realize double tone sequencing of 2m data, for example, a first pair of tone sub-modules is called 1 time, a second pair of tone sub-modules is called 2 times and a third pair of tone sub-modules is called 4 times to realize double tone sequencing of 2^5 data, namely, when the FPGA10 is used for double tone sequencing of 2 ^{^} 7 data, a double tone sequencing module of 2^5 data is set, and 1 2^7 data tone sub-modules, 2-6 data tone sub-modules and 2^2 2^5 data tone sub-modules need to be called.

In some embodiments, after the (i+1) th call to the debug sub-module 2^i times, RAM is called to cache the ordering data output by the (i+1) th call to the debug sub-module 2^i times.

Continuing with the FPGA10 as described above, when the FPGA10 is used to perform the double-tone ordering of 2^7 data, a double-tone ordering module of 2^5 data is set, where i is 0 to 2, i.e., the second double-tone ordering module 12 includes 3 pairs of tone sub-modules, for example, the first pair of tone sub-modules may be used to perform the double-tone comparison exchange of 2^7 data, the second pair of tone sub-modules may be used to perform the double-tone comparison exchange of 2≡6 data, and the third pair of tone sub-modules may be used to perform the double-tone comparison exchange of 2^5 data, where each (i+1) th pair of tone sub-modules is called 2^i times, for example, the first pair of tone sub-modules is called 1 time, the second pair of tone sub-modules is called 2 times, and the third pair of tone sub-modules is called 4 times, after the (i+1) th pair of tone sub-modules is called 2^i times, the RAM is called to buffer the ordered data outputted by 2^i times, for example, after the second pair of tone sub-modules is called 2 times, and the RAM is called 4 times of tone ordering module is called.

In some embodiments, when n=6, m=4, the second double-tone ordering module includes a first pair of tone sub-modules, a second pair of tone sub-modules, and a third pair of tone sub-modules, wherein the first pair of tone sub-modules is used for halving comparison interchange of 2≡6 data, the second pair of tone sub-modules is used for halving comparison interchange of 2^5 data, and the third pair of tone sub-modules is used for halving comparison interchange of 2^4 data; the first pair of the tone sub-modules is called 1 time, the second pair of the tone sub-modules is called 2 times, and the third pair of the tone sub-modules is called 4 times according to a preset sequence, so that double tone ordering of 2m data is realized.

Continuing with the above description of the FPGA10 as an example, when performing the double-tone ordering of 2 ^{^} n data by using the FPGA10, a double-tone ordering module of 2 ζ data is set, where m is a positive integer, and when n=6, m=4, the second double-tone ordering module 12 includes a first pair of tone sub-modules X, a second pair of tone sub-modules Y, and a third pair of tone sub-modules Z, where the first pair of tone sub-modules X is used for performing a half-comparison exchange on 2 ζ 6 data, the second pair of tone sub-modules Y is used for performing a half-comparison exchange on 2^5 data, and the third pair of tone sub-modules Z is used for performing a half-comparison exchange on 2^4 data; the first pair of the tuning sub-modules X is called 1 time, the second pair of the tuning sub-modules Y is called 2 times, and the third pair of the tuning sub-modules Z is called 4 times according to a preset sequence, so that double-tuning ordering of 2^4 data is realized.

Referring to fig. 5, fig. 5 is a schematic flow chart of a call pair tone sub-module according to an embodiment of the present application, when n=6, m=4, that is, when performing double tone sequencing of 64 data by using the FPGA10, a double tone sequencing module of 16 data is set, 16 data input in sequence for multiple times can be double tone sequenced by the first double tone sequencing module 11 in the initial module K, that is, four times of input 16 data can be respectively double tone sequenced to obtain four double tone sequences A1, A2, A3, A4, and the double tone sequences A1, A2, A3, A4 are sequentially buffered in the RAM module, for example, tmp64, that is, 64 data temporary data units.

Further, a second pair of tone sub-modules Y is called for 2 times, the second pair of tone sub-modules Y is used for performing halving comparison and exchange on 32 data, for example, a module Y1 in the second pair of tone sub-modules Y performs halving comparison and exchange on 32 data of double tone sequences A1 and A2 to obtain an intermediate sequence B1, a module Y2 performs halving comparison and exchange on 32 data of intermediate sequences A3 and A4 to obtain an intermediate sequence B2, as shown in fig. 6, fig. 6 is an effect schematic diagram of the tone sub-modules of an embodiment of the present application, namely, the 32 data halving comparison and exchange modules are rearranged from small to large after arrow representation comparison, and then the intermediate sequences B1 and B2 are sequentially buffered in a RAM module, for example, tmp64, namely, 64 data temporary storage data units.

Further, a third pair of tone sub-modules Z is called for 4 times, where the third pair of tone sub-modules Z is used to perform halving comparison and exchange on 16 data, for example, the module Z1 in the third pair of tone sub-modules Z may perform halving comparison and exchange on the first 16 data in the intermediate sequence B1 to obtain an intermediate sequence C1, the module Z2 performs halving comparison and exchange on the last 16 data in the intermediate sequence B1 to obtain an intermediate sequence C2, the module Z3 performs halving comparison and exchange on the first 16 data in the intermediate sequence B2 to obtain an intermediate sequence C3, and the module Z4 performs halving comparison and exchange on the last 16 data in the intermediate sequence B2 to obtain an intermediate sequence C4, and then sequentially buffers the intermediate sequences C1, C2, C3, and C4 in the RAM113, for example, tmp64, that is, 64 data temporary storage data units.

Further, a first pair of tone sub-modules X is called 1, and the first pair of tone sub-modules X is used for performing halving comparison and exchange on 64 data, for example, the first pair of tone sub-modules X may perform halving comparison and exchange on 64 data of the intermediate sequences C1, C2, C3, and C4, as shown in fig. 7, fig. 7 is a schematic diagram of an effect of another pair of tone sub-modules according to an embodiment of the present application, that is, the 64 data halving comparison and exchange modules, where an arrow indicates rearrangement from small to large after comparison.

In some embodiments, the preset sequence comprises: the order in which the second pair of tuning sub-modules was called 2 times, the third pair of tuning sub-modules was called 3 times, and the first pair of tuning sub-modules was called 1 time.

When n=6 and m=4, that is, when the FPGA10 is used for performing the double-tone sequencing of 64 data, a double-tone sequencing module of 16 data is set, a first double-tone sequencing module 11, and a second double-tone sequencing module 12 comprise a first pair of tone sub-modules X, a second pair of tone sub-modules Y and a third pair of tone sub-modules Z, wherein the first pair of tone sub-modules X is used for performing halving comparison exchange on 2≡6 data, the second pair of tone sub-modules Y is used for performing halving comparison exchange on 2^5 data, and the third pair of tone sub-modules Z is used for performing halving comparison exchange on 2^4 data; the first pair of the tuning sub-modules are called 1 time, the second pair of the tuning sub-modules are called 2 times, and the third pair of the tuning sub-modules are called 4 times according to a preset sequence, so that the double-tuning ordering of the 2 ^{^} data is realized, wherein the preset sequence can comprise that the first pair of the tuning sub-modules X are called 1 time, the second pair of the tuning sub-modules Y are called 2 times, and the third pair of the tuning sub-modules Z are called 4 times.

In some embodiments, the first double-tone ordering module includes a sequence sub-module and an ordering sub-module, wherein the sequence sub-module is configured to arrange 16 data into a double-tone sequence, and the ordering sub-module is configured to order the double-tone sequence; wherein the third pair of tuning sub-modules is multiplexed by the sorting sub-module.

Continuing with the example of the above-described double-tone ordering of 64 data using the FPGA10 when n=6 and m=4, the first double-tone ordering module 11 includes a sequence sub-module and an ordering sub-module, taking the original sequence "65,9,5,24,6,30,7,8,20,10,28,19,35,3,15,40" as an example, where the sequence sub-module is configured to arrange 16 data into a double-tone sequence, for example, a double-tone sequence a "5,6,7,8,9,24,30,65,40,35,28,20,19,15,10,3" may be obtained, and the ordering sub-module is configured to order the double-tone sequence a, for example, a double-tone ordering result B "3,5,6,7,8,9,10,15,19,20,24,28,30,35,40,65" may be obtained. The FPGA10 performs a double-tone ordering of 2 ^{^} n data, the first double-tone ordering module 11 is used for performing a double-tone ordering of 16 data, the second double-tone ordering module 12 is used for performing a double-tone ordering of 2m data, the (i+1) double-tone sub-module is required to be called, where i is 0 to n-m, when n=6, m=4, that is, when the FPGA10 performs a double-tone ordering of 64 data, the 16 data double-tone ordering module is set, the second double-tone ordering module 12 includes a first pair of tone sub-modules X, a second pair of tone sub-modules Y, and a third pair of tone sub-modules Z, where the third pair of tone sub-modules Z is multiplexed by the ordering sub-modules of the first double-tone ordering module 11, that is, the first double-tone ordering module 11 is used for performing a double-tone ordering of 16 data, and the third pair of tone sub-modules Z is used for performing a double-tone exchange of 2^4 data.

Referring to FIG. 8, FIG. 8 is a flow chart of a dual tone ordering method based on an FPGA, such as the FPGA10 described above, for dual tone ordering of 2 n data according to an embodiment of the present application. The execution subject of the method may be the FPGA10 as described above, and as shown in fig. 8, the method may include the steps of:

s11: the data are sequentially input multiple times according to 16 data input at a time to provide 2 n data.

The FPGA10 includes a first double-tone ordering module 11 and a second double-tone ordering module 12, where 16 data are sequentially input multiple times according to each input, that is, double-tone ordering of 16 data input each time is performed multiple times through the first double-tone ordering module 11, for example, an original sequence composed of 16 data is performed, double-tone ordering of 16 data is performed, that is, the original sequence is divided into two halves with equal length, for example, into a middle sequence X and a middle sequence Y, 8 data in the middle sequence X and 8 data in the middle sequence Y are compared one by one according to the original sequence, that is, data a _i and data a _i+n (i < n) are compared, a larger data is put into a MAX sequence, a smaller data is put into a MIN sequence, and thus the obtained MAX and MIN sequences are still double-tone sequences, and any element in the MAX sequence is not less than any element in the MIN sequence, that is the double-tone ordering of 16 data is completed once.

S12: the double-tone ordering of the 2 m data is repeatedly executed, so that the double-tone ordering of the 2 n data is realized.

When the FPGA10 is used for performing the double-tone ordering of 2n data, the double-tone ordering module of 2m data is repeatedly executed, that is, the double-tone ordering module of 2m data is set, that is, the double-tone ordering of 2m data is executed through the second double-tone ordering module 12, where m is a positive integer and n > m > n/2, so as to implement the double-tone ordering of 2n data, for example, when n=7, the FPGA10 is used for the double-tone ordering of 2 ^{^} 7 data, the double-tone ordering module 11 is used for executing the double-tone ordering of 16 data on each 16 data elements in 2 ^{^} data respectively, at this time, the second double-tone ordering module 12 is used for executing the double-tone ordering of 2m data, for example, m may be equal to 3 or 4, and if m=3, the second double-tone ordering module 12 is used for executing the double-tone ordering of 2^3 data, that is implemented by the second double-tone ordering module 12 for executing the double-tone ordering of 2^7 data on each 8 data elements in 2 ^{^} data respectively.

It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.

The foregoing description of various embodiments is intended to highlight differences between the various embodiments, which may be the same or similar to each other by reference, and is not repeated herein for the sake of brevity.

Those skilled in the art will readily appreciate that many modifications and variations are possible in the device and method while maintaining the teachings of the application. Accordingly, the above disclosure should be viewed as limited only by the scope of the appended claims.

Claims (10)

1. An FPGA for bi-tone ordering of 2 ^{^} n data, n being a positive integer, comprising:

The first double-tone ordering module is used for executing double-tone ordering of 16 data;

The second double-tone ordering module is used for executing double-tone ordering of 2 ^{^} m data, wherein m is a positive integer, and n is more than m and is more than n/2;

The first double-tone ordering module inputs the 16 data for multiple times in sequence according to each time of inputting the 16 data to provide the 2 ^{^} n data for the second double-tone ordering module, and the second double-tone ordering module is repeatedly called along with the running time to repeatedly execute the double-tone ordering of the 2 ^{^} m data, so that the double-tone ordering of the 2 ^{^} n data is realized.

2. The FPGA of claim 1, further comprising:

The RAM is used for caching intermediate data when the double-tone ordering of the 2 ^{^} n data is executed;

The RAM is repeatedly called with the running time to buffer intermediate data when the double-tone ordering of the 2 ^{^} n data is executed.

3. The FPGA of claim 2 wherein the first bi-level ordering module comprises a sequence sub-module and an ordering sub-module, wherein the sequence sub-module is configured to arrange the 16 data into a bi-level sequence, and the ordering sub-module is configured to order the bi-level sequence.

4. A FPGA as claimed in claim 2 or claim 3 wherein the RAM is used to buffer the 16 data input by the first double-tone ordering module at a time.

5. The FPGA of claim 2 wherein the second bi-level sequencing module comprises an (i+1) th pair of tone sub-modules, wherein the (i+1) th pair of tone sub-modules are configured to perform a binary comparison interchange of 2 ^{^} j data, i being 0 to n-m, j being n to m, j = n when i = 0, and j = m when i = n-m;

and each (i+1) th opposite-tone sub-module is called 2 ^{^} i times according to a preset sequence, so as to realize double-tone sequencing of the 2 ^{^} m data.

6. The FPGA of claim 5 wherein after the (i+1) th pair of debug sub-modules is invoked 2 ^{^} i times, the RAM is invoked to cache the ordering data output by the (i+1) th pair of debug sub-modules being invoked 2 ^{^} i times.

7. The FPGA of claim 6, wherein when n = 6, m = 4, the second bi-level ordering module includes a first pair of tone sub-modules for halving and comparing 2 ^{^} data for interchange, a second pair of tone sub-modules for halving and comparing 2 ^{^} 5 data for interchange, and a third pair of tone sub-modules for halving and comparing 2 ^{^} data for interchange;

the first pair of the tone sub-modules is called 1 time, the second pair of the tone sub-modules is called 2 times, and the third pair of the tone sub-modules is called 4 times according to a preset sequence, so that double tone ordering of the 2 ^{^} m data is achieved.

8. The FPGA of claim 7, wherein the predetermined sequence comprises: the order in which the second pair of tuning sub-modules is called 2 times, the third pair of tuning sub-modules is called 4 times, and the first pair of tuning sub-modules is called 1 time.

9. The FPGA of claim 7 or 8, wherein the first bi-level ordering module comprises a sequence sub-module and an ordering sub-module, wherein the sequence sub-module is configured to arrange the 16 data into a bi-level sequence, and the ordering sub-module is configured to order the bi-level sequence;

wherein the third pair of tuning sub-modules is multiplexed by the sorting sub-module.

10. A method of double-tone ordering based on an FPGA, wherein the FPGA is an FPGA according to any one of claims 1-9, for double-tone ordering of 2 ^{^} n data, comprising:

Sequentially inputting the 16 data for a plurality of times according to each time of inputting to provide 2 ^{^} n data;

The double-tone ordering of 2 ^{^} m data is repeatedly performed, so that the double-tone ordering of 2 ^{^} n data is realized.